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74ABT652 Octal Transceivers and Registers with 3-STATE Outputs
November 1992 Revised January 1999
74ABT652 Octal Transceivers and Registers with 3-STATE Outputs
General Description
The ABT652 consists of bus transceiver circuits with Dtype flip-flops and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. s A and B output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability
Features
s Independent registers for A and B buses s Multiplexed real-time and stored data
Ordering Code:
Order Number 74ABT652CSC 74ABT652CMSA 74ABT652CMTC Package Number M24B MSA24 MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignment for SOIC, SSOP and TSSOP
Pin Descriptions
Pin Names A0-A7 B0-B7 CPAB, CPBA SAB, SBA OEAB, OEBA Description Data Register A Inputs/3-STATE Outputs Data Register B Inputs/3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Inputs
(c) 1999 Fairchild Semiconductor Corporation
DS011512.prf
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74ABT652
Truth Table
Inputs OEAB L L X H L L L L H H H OEBA H H H H X L L L H H L CPAB H or L CPBA H or L H or L SAB X X X X X X X X L H H SBA X X X X X X L H X X H Output Output Input Output Input Input Output Output Output Input Input Inputs/Outputs (Note 1) A0 thru A7 Input B0 thru B7 Input Isolation Store A and B Data Not Specified Store A, Hold B Store A in Both Registers Hold A, Store B Store B in Both Registers Real-Time B Data to A Bus Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW to HIGH Clock Transition
Operating Mode
H or L X X X H or L H or L

X X X
Not Specified Input
H or L
H or L
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs.
Functional Description
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the ABT652. Data on the A or B data bus, or both, can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Note A: Real-Time Transfer Bus B to Bus A
Note B: Real-Time Transfer Bus A to Bus B
OEAB OEBA L L
CPAB CPBA SAB SBA X X X L
OEAB OEBA H H
CPAB CPBA SAB SBA X X L X
Note C: Storage
Note D: Transfer Storage Data to A or B
OEAB OEBA X L L H X H
CPAB CPBA SAB SBA X X X X X X X OEAB OEBA H L CPAB CPBA SAB SBA H or L H or L H H X

FIGURE 1.
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74ABT652
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current twice the rated IOL (mA) -500 mA -0.5V to +5.5V -0.5V to VCC -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Over Voltage Latchup (I/O)
10V
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100 mV/ns -40C to +85C +4.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage VOL VID Output LOW Voltage Input Leakage Test 4.75 2.5 2.0 0.55 V V A A A A Min 0.0 Min 2.0 0.8 -1.2 Typ Max Units V V V V Min Min VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA (Non I/O Pins) IOH = -3 mA, (An, Bn) IOH = -32 mA, (An, Bn) IOL = 64 mA, (An, Bn) IID = 1.9 A, (Non-I/O Pins) All Other Pins Grounded IIH Input HIGH Current 1 1 IBVI IBVIT IIL IIH + IOZH IIL + IOZL Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current 7 100 -1 -1 Output Leakage Current 10 A Max Max Max Max VIN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, B n) VIN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) 0V-5.5V VOUT = 2.7V (An, Bn); OEBA = 2.0V and OEAB = GND = 2.0V Output Leakage Current -100 -10 -275 50 100 250 30 50 A 0V-5.5V VOUT = 0.5V (An, Bn); OEBA = 2.0V and OEAB = GND = 2.0V IOS ICEX IZZ ICCH ICCL ICCZ Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current mA A A A mA A Max Max 0.0V Max Max Max VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW Outputs 3-STATE; All others at VCC or GND ICCT Additional ICC/Input 2.5 mA Max VI = VCC - 2.1V All others at VCC or GND ICCD Dynamic ICC (Note 6) No Load 0.18 mA/MHz Max Outputs Open (Note 5) OEAB = OEBA = GND One bit toggling, 50% duty cycle
Note 4: Guaranteed but not tested. Note 5: For 8 outputs toggling, ICCD < 1.4 mA/MHz. Note 6: Guaranteed, but not tested.
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74ABT652
DC Electrical Characteristics
(SOIC package) Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage -1.2 2.5 2.2 Min Typ 0.6 -0.9 3.0 1.8 0.8 0.4 Max 0.8 Units V V V V V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL = 50 pF, RL = 500 TA = 25C (Note 7) TA = 25C (Note 7) TA = 25C (Note 8) TA = 25C (Note 9) TA = 25C (Note 9)
Note 7: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 8: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 9: Max number of data inputs (n) switching. n - 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package) TA = +25C Symbol Parameter Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Max Clock Frequency Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay SBA or SAB to An to Bn Enable Time OEBA or OEAB to An or Bn Disable Time OEBA or OEAB to An or Bn 200 1.7 1.7 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 3.4 2.6 3.0 3.0 3.4 3.3 3.7 3.7 3.3 4.9 4.9 4.5 4.5 5.0 5.0 5.5 5.5 6.0 6.0 VCC = +5.0V CL = 50 pF Typ Max Min 200 1.7 1.7 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 4.9 4.9 4.5 4.5 5.0 5.0 5.5 5.5 6.0 6.0 ns ns ns ns TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF Max MHz ns Units
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74ABT652
AC Operating Requirements
TA = +25C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Pulse Width, HIGH or LOW 3.0 3.0 ns 1.0 1.0 ns 1.5 VCC = +5.0V CL = 50 pF Max Min 1.5 TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF Max ns Units
Extended AC Electrical Characteristics
(SOIC package): TA = -40C to +85C VCC = 4.5V-5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 10) Min tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay SBA or SAB to An or Bn Output Enable Time OEBA or OEAB to An or Bn Output Disable Time OEBA or OEAB to An or Bn 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max 5.5 5.5 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 (Note 13) (Note 13) ns TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 1 Output Switching (Note 11) Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Max 7.5 7.5 7.0 7.0 7.5 7.5 8.0 8.0 TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 8 Outputs Switching (Note 12) Min 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Max 10.0 10.0 9.5 9.5 10.0 10.0 11.5 11.5 ns ns ns ns Units
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 11: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 12: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: The 3-STATE delay times are dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
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74ABT652
Skew
(SOIC Package) TA = -40C to +85C VCC = 4.5V-5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 16) Max tOSHL (Note 14) tOSLH (Note 14) tPS (Note 18) tOST (Note 14) tPV (Note 15) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH-HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 2.5 4.5 ns 2.0 4.0 ns 2.0 4.0 ns 1.0 2.0 ns 1.3 TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 8 Outputs Switching (Note 17) Max 2.5 ns Units
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-toLOW (tOST). This specification is guaranteed but not tested. Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 17: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 18: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Symbol CIN CI/O (Note 19) Parameter Input Capacitance I/O Capacitance Typ 5.0 11.0 Units pF pF Conditions (TA = 25C) V CC = 0V (non I/O pins) V CC = 5.0V (An, Bn)
Note 19: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883D, Method 3012.
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74ABT652
AC Loading
*Includes jig and probe capacitance
FIGURE 2. Standard AC Test Load
FIGURE 3. Test Input Signal Levels
Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns
FIGURE 4. Test Input Signal Requirements
AC Waveforms
FIGURE 5. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 7. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 6. Propagation Delay, Pulse Width Waveforms
FIGURE 8. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT652
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24
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74ABT652 Octal Transceivers and Registers with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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