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CD4063BMS
December 1992
CMOS 4-Bit Magnitude Comparator
Pinout
CD4063BMS TOP VIEW
Features
* High Voltage Type (20V Rating) * Expansion to 8, 12, 16 . . . 4N Bits by Cascading Units * Medium Speed Operation - Compares Two 4-Bit Words in 250ns (Typ.) at 10V * 100% Tested for Quiescent Current at 20V * Standardized Symmetrical Output Characteristics * 5V, 10V and 15V Parametric Ratings * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Full Package Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
B3 (A < B) IN (A = B) IN (A > B) IN (A > B) OUT (A = B) OUT (A < B) OUT VSS
1 2 3 4 5 6 7 8
16 VDD 15 A3 14 B2 13 A2 12 A1 11 B1 10 A0 9 B0
Functional Diagram
4 WORD A
Applications
* Servo Motor Controls * Process Controllers
A>B CASCADING INPUTS A=B AA>B A=B ADescription
CD4063BMS is a 4-bit magnitude comparator designed for use in computer and logic applications that require the comparison of two 4-bit words. This logic circuit determines whether one 4-bit word (Binary or BCD) is "less than", "equal to", or "greater than" a second 4-bit word. The CD4063BMS has eight comparing inputs (A3, B3, through A0, B0), three outputs (A < B, A = B, A > B) and three cascading inputs (A < B, A = B, A > B) that permit systems designers to expand the comparator function to 8, 12, 16 . . . 4N bits. When a single CD4063BMS is used, the cascading inputs are connected as follows: (A < B) = low, (A = B) = high, (A > B) = low. For words longer than 4 bits, CD4063BMS devices may be cascaded by connecting the outputs of the less significant comparator to the corresponding cascading inputs of the more significant comparator. Cascading inputs (A < B, A = B, and A > B) on the least significant comparator are connected to a low, a high, and a low level, respectively. The CD4063BMS is supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1E H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3318
7-958
Specifications CD4063BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP Package . . . . . . . . . . . . . 80oC/W 20C/W Flatpack Package . . . . . . . . . . . . . . . . 20oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) NOTES: 1. All voltages referenced to device GND. 100% testing being implemented 2. Go/No Go test with limit applied to inputs VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25
oC
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 -
MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
+125oC -55oC +25o C
+125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC
+25oC, +125oC, -55oC 14.95 +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 0.53 1.4 3.5 -2.8 0.7
VOH > VOL < VDD/2 VDD/2
1.5 4 -
V V V V
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-959
Specifications CD4063BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1, 2) CONDITIONS VDD = 5V, VIN = VDD or GND GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -2.6 -2.4 -4.2 3 UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V +25oC +125oC, -55oC LIMITS MIN o
PARAMETER Propagation Delay Comparator Input to Output Propagation Delay Cascade Input to Output Transition Time
SYMBOL TPHL TPLH TPHL TPLH TTHL
MAX 1250 1688 1000 1350 200 270
UNITS ns ns ns ns ns ns
+25oC +125 C, -55 C +25oC +125oC, -55oC
o
-
+125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC
+125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC
+125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC
7-960
Specifications CD4063BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage High Propagation Delay Comparator Input to Output Propagation Delay Cascade Input to Output Transition Time SYMBOL VIH TPHL1 TPLH1 TPHL2 TPLH2 TTHL TTLH CIN CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V NOTES 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC, +125oC, -55oC +25oC +25oC +25 C +25oC +25oC +25oC +25oC
o
MIN +7 -
MAX 500 350 400 280 100 80 7.5
UNITS V ns ns ns ns ns ns pF
Input Capacitance NOTES:
1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K; input TR, TF < 20ns TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VNTH VPTH VPTH F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS= -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V (Worst Case) 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25
oC o
MIN -2.8 0.2 VOH > VDD/2 -
MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit
UNITS A V V V V V
+25 C +25
oC
+25oC +25oC +25oC
ns
NOTES: 1. All voltages referenced to device GND. 2. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF = 20ns 3. See Table 2 for +25oC limit. 4. Read and record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) METHOD 100% 5004 GROUP A SUBGROUPS 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A
7-961
Specifications CD4063BMS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 5% parametric, 3% functional; cumulative for static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 METHOD 5005 PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9, Deltas POST-IRRAD Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 5-7 5-7 5-7 GROUND 1, 2, 4, 8-15 3, 8 1, 2, 4, 8, 10, 11, 13 3, 8 VDD 3, 16 1, 2, 4, 9-16 3, 16 1, 2, 4, 9-16 5-7 12, 15 9, 14 9V -0.5V 50kHz 25kHz
A0 A1 A2 A3
A4 A5 A6 A7
A8 A9 A10 A11
VDD
CD4063 (A < B) IN
(A < B) OUT (A = B) OUT
CD4063
CD4063
(A = B) IN (A > B) IN (A > B) OUT
B0 B1 B2 B3
B4 B5 B6 B7
B8 B9 B10 B11
tP TOTAL = tP (COMPARE INPUTS) + 2 x tP (CASCADE INPUTS), AT VDD = 10V (3 STAGES) = 250 + (2 x 200) = 650ns (TYP.)
FIGURE 1. TYPICAL SPEED CHARACTERISTICS OF A 12-BIT COMPARATOR
7-962
CD4063BMS Logic Diagram
A3 B3 A0 10
* * * * * * * * * * *
A0 A0 A1 A1 A2 A2 A3 A3 B0 B0 B1 B1 B2 B2 B3 B3
A3 B3 A2 B2 A2 B2 A1 B1 A1 B1 A0 B0 A0 B0 (A < B) i - I
AA1 12
A2 13
A3 15 COMPARING INPUTS B0 9
B1 11
7
(A < B) OUT
B2 14
6 B3 A3
(A = B) OUT
B3 1
(A < B) IN 2 CASCADING INPUTS (A > B) IN 4
(A < B) i - I
B3 A3 B2 A2 B2 A2 B1 A1 B1 A1 B0 A0 B0 A0
A>B
5
(A > B) OUT
(A > B) i - I
(A = B) IN 3
VDD
*
ALL INPUTS PROTECTED BY THE CMOS PROTECTION NETWORK INPUT TERMINAL VSS
(A > B) i - I
FIGURE 2. LOGIC DIAGRAM TRUTH TABLE INPUTS COMPARING A3, B3 A3 > B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 < B3 X = Don't Care A2, B2 X A2 > B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 < B2 X Logic 1 = High Level A1, B1 X X A1 > B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 < B1 X X A0, B0 X X X A0 > B0 A0 = B0 A0 = B0 A0 = B0 A0 < B0 X X X A B X X X X 1 0 0 X X X X AB 1 1 1 1 1 0 0 0 0 0 0
Logic 0 = Low Level
7-963
CD4063BMS Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
0
0 -5 -10 -15
0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tTHL, tTLH) (ns) 700 600 500 AMBIENT TEMPERATURE (TA) = +25oC 400 300 200 100 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE (CL) (pF) 90 10V 15V
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tTHL, tTLH) (ns) 1750 1500 1250 1000 750 500 250 AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50pF
SUPPLY VOLTAGE (VDD) = 5V
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
SUPPLY VOLTAGE (VDD) (V)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE ("COMPARING INPUTS" TO OUTPUTS)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs SUPPLY VOLTAGE ("COMPARING INPUTS" TO OUTPUTS)
7-964
CD4063BMS Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
(Continued)
POWER DISSIPATION PER GATE (PD) (W) 104
6 4 2
AMBIENT TEMPERATURE (TA) = +25oC
103
6 4 2
200 SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 15V LOAD CAPACITANCE (CL) = 50pF 10V, 50pF
150
102
6 4 2
10V, 15pF 5V, 50pF
100 10V 50 15V
10
6 4 2
1 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF)
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
0.1
1 10 102 INPUT FREQUENCY (f) (kHz)
103
FIGURE 9. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE
FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: PASSIVATION:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
965

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