View CXA1843Q_144946.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXA1843Q
High-Speed Sample-and-Hold IC For the availability of this product, please contact the sales office.
Description The CXA1843Q is a bipolar IC designed to sampleand-hold video and various other signals with high speed. It is ideal for video and other signal conversions. Features * Maximum operating rate = 33MHz (min.) * Low power consumption: 320mW * S/H clock pulse generator circuit * Built-in clock pulse generator for A/D converter Applications When used in combination of the CXA1844Q, the CXA1843Q achieves A/D conversion. Absolute Maximum Ratings (Ta = 25C) * Supply voltage VCC 7 V VEE -7 V * Input voltage (VIN pin) VIN VEE to AVCC + 0.3 V (REFIN pin) VREFIN +1 to AVCC + 0.3 V (CLKIN pin) VCLK GND - 0.5 to DVCC + 0.3 V (REX 2, 3, 4 pins) VREX2, 3, 4 GND to GND + 4 V * Reference voltage (REFFB pin) VREFFB VEE to +3 V (REFOUT pin) VREFOUT VEE to AVCC + 0.3 V * Output current (REFFOUT pin) IREFOUT -1 to +1 mA (SHOUT pin) ISHOUT -12 to +12 mA (CLKOUT pin) IADC -1.5 to +1.5 mA * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 1.1 W Operating Conditions * Supply voltage VCC VEE * Operating temperature Topr 32 pin QFP (PIastic)
Structure Bipolar silicon monolithic IC Block Diagram and Pin Configuration
CLKOUT REF IN DVCC2 DVCC1 AVCC4
17 NC REFFB REFOUT AVEE3 AVCC3 SHOUT AVEE2 NC 14 SAMPLE HOLD PULSE GENERATOR 13 12 11 SAMPLE HOLD 10 9 1 2 3 4 5 6 7 8
GND
NC
24 NC 25 DVEE1 26 REX3 27 REX4 28 DVEE2 29 DVCC3 30 CLK IN 31 NC 32
23
22
21 20
19 18
REX2 NC
A/D CONVERTER PULSE GENERATOR
REF DC 16 SHIFT 15
AVCC1
CGND
AVEE1
HGND
VIN
4.75 to 5.25 -4.75 to -5.25 -20 to +75
V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
NC
NC
E92855B7Y
CXA1843Q
Pin Description Pin No. 1 Symbol AVCC1 Pin voltage 5V (Typ.)
AVCC1
Equivalent circuit
Description Analog positive power supply.
2
HGND
0V
Internal resistance GND for sample-and-hold.
HGND VIN 130 30k
3
VIN
--
DVEE2
Sample-and-hold-input.
4
AVEE1
-5V (Typ.)
Analog negative power supply.
5
CGND
0V
AVCC1 AVEE1 500 500 CGND
Internal capacitance GND for sample-and-hold.
DVEE2
6 7 8 9 10
NC NC NC NC AVEE2
-- -- -- -- -5V (Typ.)
AVCC3
Connect to AGND. Connect to AGND. Connect to AGND. Connect to AGND. Analog negative power supply.
11
SHOUT
SHOUT
Sample-and-hold output.
DVEE2
-2-
CXA1843Q
Pin No. 12 13
Symbol AVCC3 AVEE3
Pin voltage 5V (Typ.) -5V (Typ.) -2.8V As shown in the Application Circuit, PNP TR. is connected and 2.5V is applied to Pin18. -2V As shown in the Application Circuit, PNP TR. is connected and 2.5V is applied to Pin18. -- 5V (Typ.)
AVCC4
Equivalent circuit
Description Analog positive power supply. Analog negative power supply.
AVCC4 400 130 REFFB REFOUT
14
REFOUT
Connect the base of the external PNP transistor to create a -2V power supply.
15
REFFB
AVEE3
DVEE2
Connect the emitter of the external PNP transistor to create a -2V power supply.
16 17
NC AVCC4
Connect to AGND. Analog positive power supply.
18
REFIN
2.5V (Typ.)
REFIN 130 GND DVEE2 300
External DC input for adjusting the -2V power supply.
DVCC2
19
REX2
Approx. 0.5V When external resistor is connected between Pin 19 and AGND
REX2 GND DVEE2
1k 130 0.5V
Connect external resistor that determines the time interval (T2) between master clock (MCLK) rise and A/D converter clock (A/D CLK) fall. (Normally connect to 1.6k)
20
NC
--
Connect to AGND.
-3-
CXA1843Q
Pin No. 21
Symbol GND
Pin voltage 0V
Equivalent circuit GND
DVCC2
Description
H: DVCC2 - 0.78V 22 CLKOUT L: DVCC2 - 1.52V (Typ.)
600 CLKOUT 2.2mA GND DVEE2
A/D converter clock (A/D CLK) output.
23 24 25 26
DVCC1 DVCC2 NC DVEE1
5V (Typ.) 5V (Typ.) -- -5V (Typ.) Approx. 0.5V When external resistor is connected between Pin 27 and DGND Approx. 0.5V When external resistor is connected between Pin 28 and DGND -5V (Typ.) 5V (Typ.)
DVCC3 DVCC2
Digital positive power supply. Digital positive power supply. Connect to DGND Digital negative power supply. Connect external resistor that determines the time interval (T3) between master clock (MCLK) rise and sample-and-hold internal clock (S/H CLK) rise. (Normally connect 2.7k)
1k 130 0.5V
27
REX3
1k REX3 REX4 GND DVEE2 130
28
REX4
Connect external resistor that determines the time interval (T4) between master clock (MCLK) rise and sample-and-hold internal clock (S/H CLK) rise. (Normally connect 1.5k) Digital negative power supply. Digital positive power supply.
29 30
DVEE2 DVCC3
31
CLKIN
--
CLKIN GND
130
Master clock (MCLK) input. TTL level. (Vth = 1.5V)
300
DVEE2
32
NC
--
Connect to DGND.
-4-
CXA1843Q
Electrical Characteristics Item Maximun operating rate Current consumption S/H Amplifier Block VIN input current VIN input voltage range Droop Feed through IVIN VIN HMDR HMTH VIN = -1V FIN = 1kHz, distortion factor -55dB VIN = -2V to 0V FIN = 16.5MHz (2Vp-p) VIN = -1V, FCLK = 33MHz FIN = 1kHz (2Vp-p), FCLK = 33MHz 20Log (VO (16.5MHz)/VO (200kHz)), Sampling time = 14ns CL = 50pF Symbol FC ICC IEE Conditions
(Ta = 25C, VCC = 5V, VEE = -5V) Min. 33 32 -28 41 -23 50 -18 Typ. Max. Unit MHz mA mA
1 -2.2 -20 -40 55 -0.5 -1 140
20
50 0.2
A V mV/s dB mV dB dB V/s
20 -50 90 0.3 0.2 160
80 -70 120 0.5 1 200
S/H output offset voltage VOFFSET S/H output gain S/H output frequency response S/H output slew rate Reference Amplifier Block REFIN input current REFFB output voltage Digital I/O Block CLKIN input current ICLKL ICLKH VCLKL VCLKH CLKIN clock width A/D clock low level A/D clock high level TPWH TPWL VADCL VADCH IREFIN VREFFB Gsh Fsh SR
VREFIN = 2.5V VREFIN = 2.5V
0 -2.2
1 -2.0
10 -1.8
A V
VCLKIN = 0V VCLKIN = 5V
-10 0
-6 0
0 1 0.8
A A V V ns ns
CLKIN input voltage
2.0 9 9 VCC - 1.52 VCC - 1.40 VCC - 0.90 VCC - 0.78
V V
-5-
CXA1843Q
Timing Chart
VIN (Pin 3) (0 to -2V) Tsd TPWL MCLK(Pin 31) (TTL) T4 T3 S/H CLK (Not output to outside) Hold Sample Hold Sample
N+1 N+2 N Tsd TPWH Threshold voltage = 1.5V Tsd
Hold
Sample
Hold
Threshold voltage
taqr tdr S/H OUT (Pin 11) (0 to -2V) 10% N-1 tdf taqf A/D CLK (Pin 22) (PECL) Threshold voltage = VCC - 1.2V T2 tD (max) tD (min) Threshold voltage = 1.5V N 90% 10% 90% N+1 2Vp-p N+2
T1 = 6ns
A/D output (CXA1844Q) (TTL)
DN - 3
DN - 2
DN - 1
DN
TS Th MCLK (Clock pulse for the device next to the ADC in order to latch the A/D output) Threshold voltage = 1.5V
System master clock. This clock actuates the internal sample-and-hold circuit. The internal clock pulse circuit generates the S/H CLK, which is not output outside the IC. A/D CLK: This clock actuates the A/D converter. The internal clock buffer circuit generates the A/D CLK. This clock has the level where +5V is shifted from the ECL level. TPWH, TPWL: S/H CLKIN input clock width Tsd: S/H sampling delay for the S/H internal clock T1: Fixed time interval between master clock rise and A/D CLK rise, T1 = 6ns (typ.) T2: Time interval between MCLK rise and A/D CLK fall T3: Time interval between MCLK rise and S/H CLK rise T4: Time interval between MCLK rise and S/H CLK fall taqf, tdf: 10%/90% falling output delay of S/H from MCLK rise taqr, tdr: 10%/90% rising output delay of S/H from MCLK rise tD (min., max.): Minimum/maximum output delay of A/D converter (Refer to the CXA1844Q specification.) Ts: Setup time of A/D output and MCLK Th: Hold time of A/D output and MCLK -6-
MCLK: S/H CLK:
Application Circuit
AGND 62 5V 1k 430 2k 47 0.1 AGND 17 AGND AGND AGND AGND AGND AGND (NC) 16 AGND 0.1 0.1 0.1 32 31 30 29 27 26 28 25 REFFB 15 36 34 33 35 0.1 0.1 47 DGND DGND 5V 0.1
DGND
0.1 20 19 18
5V
5V
DGND DGND
DGND
24
23
22
21
GND
(NC)
REX2 REX2
0.1
0.1
DGND
DGND
-5V
26
DVEE1
0.1 DGND
(NC)
VREF3
VREF2
VREF1
VREFB
VREFT
VREFBS
VREFTS
(NC)
(NC)
DGND -5V 0.1 38 50 39 50 40 AVEE2 10 0.1 5V 41 200 AGND D1 AGND AGND 43 (NC) 42 0.1 (NC) (NC) 9 AGND -5V VINH VINL (NC) AVCC3 12 5V 0.1 SHOUT 11 AGND
REX3 0.1 DGND 47 AVEE3 13 AGND 37 (NC)
DGND3
DGND4
DGND 14
27
REX3 REFOUT
CLKOUT
DGND
25
(NC)
DVCC2
DVCC1
REFIN
AVCC4
P1 25A1005 AGND AGND PS
24
PS
28
REX4
-5V
REX4 0.1 DGND
CXA1843Q
ENABLE
23
ENABLE
29
DVEE2
CLK
22
30
DVCC3
0.1 DGND 5V 0.1 DGND
MINV
21
MINV
MCLK
31
CLKIN
LINV
20
LINV
TTL DGND
32
(NC)
AVEE1
D0 1
D1 2
D2 3
D3 4
D4 5
DGND1
DGND1
-7-
CGND (NC) (NC) (NC)
5 6 7 8
AVCC1
HGND
VIN
(NC)
19
1
2
3
4
CXA1844Q
DGND2 18 DGND
0.1 -5V 44 0.1 5V AGND 45 DVCC2 0.1 DGND 46 UNDER AVEE
AGND
0.1 AGND AGND AGND AGND
DVEE
17 0.1 DGND DGND1 16
AGND
-5V
AGND
5V
VIN
DGND
-5V
VIN = 2Vp-p (max) DC - 1V
DVCC1 15 0.1 DGND DGND1 14
5V
47
OVER
DGND
48
DGND1
DGND1 D5 6 7 8 D6 9 D7 10 D8 11 D9 12
13
DGND
CXA1843Q External Resistance
DGND DGND
Symbol
External resistance
UNDER OVER D0 D1 D2 D3 D4
REX2
1.6k
D5
D6
D7
D8
D9
REX3
2.7k
REX4
1.5k Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXA1843Q
Metal film resistors must be connected to the REX2 to REX4 pins.
CXA1843Q
Notes on Operation (1) In circuit board layout, it is necessary that the AGND and DGND patterns be as large as possible and that double or more layer pattern be used to make low impedance. (2) To prevent digital system noise interference with the analog system, the AGND and DGND, AVCC and DVCC, AVEE and DVEE on the PCB must be separated from each other. However, connect the AVEE and DVEE with coil and others to prevent the generation of differential voltage. (3) The AVCC, DVCC, AVEE and DVEE pins must be connected to the AGND or DGND respectively via ceramic chip capacitors those are 0.1F or more, as close to the pin as possible. (4) The length of the wiring between the S/H SHOUT and A/D converter VIN should be as short as possible. (5) The range of the signal input to VIN (Pin 3) of the sample-and-hold circuit is 0 to -2V. (6) Adjust the VREFIN applied voltage so that VREFFB = f - 2V. (7) As shown in the Block Diagram, the amplifier input and output are internally connected to the REFOUT and REFFB pins. To generate REFFB voltage for the reference voltage of A/D converter, the connection of an external PNP transistor (hFE 100 (typ.)) is required as shown in the Application Circuit. (8) Make the S/H DVCC2 voltage equal to the A/D converter DVCC1 voltage.
-8-
CXA1843Q
Example of Representative Characteristics
ICC vs. Ta
42 -21
IEE vs. Ta
41
-22
ICC [mA]
40
IEE [mA]
-23 39 -25 0 25 Ta [C] 50 75 -24 -25
0
25 Ta [C]
50
75
ICC vs. VCC
43 42 41 -21 -19
IEE vs. VEE
-20
ICC [mA]
IEE [mA]
40 39 38 37 36 4.75
-22
-23
-24
5 VCC [V]
5.25
-25 -5.25
-5 VEE [V]
-4.75
VOFFSET vs. VCC
100 VIN = -2V 95 95 100
VOFFSET vs. VEE
VIN = -2V
VOFFSET [mA]
VOFFSET [mA]
VIN = -1V 90
VIN = -1V 90
VIN = 0V 85 85
VIN = 0V
80 4.75
5 VCC [V]
5.25
80 -5.25
-5 VEE [V]
-4.75
-9-
CXA1843Q
VOFFSET vs. Ta
VREFFB - A/D converter reference voltage [V]
120 110 VIN = -2V
A/D converter reference voltage vs. Input voltage
-1.4
-1.6
VOFFSET [mV]
100 VIN = -1V 90 VIN = 0V
-1.8
-2
80
-2.2
70
-2.4 -2.6
60 -25
0
25 Ta [C]
50
75
2
2.5 VREFFIN - Input voltage [V]
3
A/D converter reference voltage vs Ta (VREFFIN = 2.5V)
-1.99 -2.004
A/D converter reference voltage vs. VCC (VREFFIN = 2.5V)
VREFFB - A/D converter reference voltage [V]
VREFFB - A/D converter reference voltage [V]
-2.005
-1.995
-2.006
-2
-2.007
-2.008
-2.005
-2.009
-2.01 -25
0
25 Ta [C]
50
75
-2.01 4.75
5 VCC [V]
5.25
A/D converter reference voltage vs. VEE (VREFFIN = 2.5V)
-2.004
VREFFB - A/D converter reference voltage [V]
-2.005
-2.006
-2.007
-2.008
-2.009 -2.01 -5.25
-5 VEE [V]
-4.75
- 10 -
CXA1843Q
T2 vs. REX2
40
A/D clock width Tpwh (T2-T1) variation vs. Ta (Ta = 25C typ.)
1
35
A/D clock width Tpwh variation [ns]
0.5
30
T2 [ns]
25
0
20
-0.5
15
10 0
1
2
3
-1 -25
0
REX2 [k] For normal use. REX = 21.6k
25 Ta [C]
50
75
A/D clock width Tpwh (T2-T1) variation vs. VCC (VCC = 5.0V typ.)
1
A/D clock width Tpwh (T2-T1) variation vs. VEE (VEE = -5.0V typ.)
1
A/D clock width Tpwh variation [ns]
0.5
A/D clock width Tpwh variation [ns]
0.5
0
0
-0.5
-0.5
-1 4.75
5 VCC [V]
5.25
-1 -5.25
-5 VEE [V]
-4.75
S/H output delay (tdr, tdf) vs. REX3 (taqr, taqf) vs. REX4
45 1.5
S/H output delay variation vs. Ta (Ta = 25C typ.)
taqf
35
taqr
S/H output delay variation [ns]
5 REX3 [k] 2.8 REX4 [k]
40
1 0.5
tdr, tdf, taqr, taqf [ns]
30 tdr 25 tdf 20 15 2 1.1 3 4 2 For normal use, REX3 = 2.7k REX4 = 1.5k
0
-0.5
-1 -1.5 -25
0
25 Ta [C]
50
75
- 11 -
CXA1843Q
S/H output delay variation vs. VCC (VCC = 5.0V typ.)
1 1
S/H output delay variation vs. VEE (VEE = -5.0V typ.)
S/H output delay variation [ns]
S/H output delay variation [ns]
5 VCC [V] 5.25
0.5
0.5
0
0
-0.5
-0.5
-1 4.75
-1 -5.5
-5 VEE [V]
-4.5
Input frequency vs. S/N ratio for CXA1843Q + CXA1844Q (clock frequency = 33MHz)
60 Amplitude = 2Vp-p Amplitude = 1Vp-p
55
50
S/N ratio [dB]
45
40
35
30 0.001
0.01
0.1 Input frequency [MHz]
1
10
20
- 12 -
CXA1843Q
S/H + A/D EVALUATION BOARD The S/H + A/D Evaluation Board is a printed circuit board for evaluating the 10-bit 33MSPS high speed sample-and-hold IC (CXA1843Q) and 2-step A/D converter (CXA1844Q). This board is designed to enable users to make full use of the performance of CXA1843Q + CXA1844Q and evaluate them easily. Features * Resolution * Maximum operating conversion speed * 2 types analog input * Analog input dynamic range * Digital output level * Power supply voltage * Built-in D/A converter (For evaluation) Block Diaram
10bit 33MSPS VIN input (OP AMP input) and DIR. IN input (AC coupled input) are available. 2Vp-p TTL 5V Generates the analog waveform.
S2 CLK input (CON4) 50 Counter CLK/16 CLK/8 CLK/4 CLK/2 CLK/N
10 DGND Buffer Buffer CLK Latch
10
CON
ENABLE
SW1 A/D CLK VREFBS
MINV LINV DAINV
PS
FULSCAL ADJ VR2 A/D OUT 10 CLK/N Latch 10 TTL ECL 10 10bit D/A AGND VEE D/A OUT (CON3)
10bit A/D VRBS VRB VIN L VIN H 18 REX2 1.6k 2.7k 1.5k
-2.0V
REF IN REFB S/H MCLK 2.5V AGND OFFSET ADJ OP VR1 AMP AGND x 2 Analog input VIN (CON1) 50 AGND Analog input DIR.IN (CON2) VIN A S1 B
S/H OUT
REX3 REX4
VEE GND VCC (-5V) (+5V)
50 AGND
S/H + A/D Evaluation Board Block Diagram
- 13 -
CXA1843Q
Connection and Setting for S/H + A/D Evaluation Board 1. Power supply voltage (CON6) Item Vcc VEE Min. +4.75 -5.25 Typ. +5.0 -5.0 Max. +5.25 -4.75 Unit V V Typical current 220 -400 Unit mA mA
2. Analog input (CON1, CON2) and offset adjustment (VR1) [VIN Input] (CON1) When the amplitude of an analog input signal supplied to the sample-and-hold is 1Vp-p and its input range is within 1.0V to -0.9V, the board is able to amplify its amplitude by two times using the operation amplifier. The S1 selector should be short-circuited at side A and opened at side B, and the analog input is added from CON1. In this case, offset adjustment is required at the VR1, so that the dynamic range of the analog input signal can be set to a value between 0V to -2V by monitoring the VIN pin. [DIR IN. Input] (CON2) When the input supplied to the sample-and-hold is a recurring signal (sine wave, etc.) without offset, it is added using the AC coupled input from CON2 by connecting a 10k resistor to side A and a 0.1F capacitor to side B of the S1 selector. In this case, offset adjustment is required at the VR1, so that the dynamic range of the analog input signal can be set to a value between 0V to -2V by monitoring the VIN pin. S1 setting Item VIN input (CON1) DIR. IN input (CON2) Min. -0.9 -2.0 0 Typ. Max. 1.0 2.0 Amplitude 1.0 2.0 Unit V V A short 10k B open 0.1F
(CON1 and CON2 are terminated to AGND at 50 on the board.)
3. Clock input (CON4) TTL compatible Use in the 30 to 70% CLK duty range (CON4 is terminated to DGND at 50 on the board.) 4. Digital output (CON5) TTL compatible C-MOS (ACT series) output
- 14 -
CXA1843Q
5. D/A out (CON3) and full-scale adjustment (VR2) The output waveforms of the D/A converter are output from CON3. When an oscilloscope or other such instrument is used for monitoring, a 50 terminating resistor is required. The full-scale output voltage must also be adjusted. And the output amplitude should also be adjusted to 1Vp-p by the VR2. Item D/A OUT Min. -1.0 Typ. Max. 0 Unit V
6. SW1 setting These are the switches for PS, ENABLE, MINV, and LINV of the A/D converter and the DAINV of the D/A converter. Normally all are used ON. 7. S2 setting This is the selection of the frequency division ratio for the clock which is supplied to the D/A converter. Normally, 1/1 is used but the ratios from 1/2 to 1/16 are also used for the envelope test or other tests.
- 15 -
CXA1843Q
CXA1843Q + CXA1844Q PCB Timing Chart
N Analog input (0 to -2V) N+1 N+2
CLK input (TTL)
MCLK (TTL) T4 SH CLK (internal) SH Analog out (0 to -2V) T2 AD CLK (PECL) T1 Tpwh tdmax AD Data out (TTL) tdmin N-2 N-1 N Tpwl T3 Sample Hold N N+1 TH TL N+2 S H S H
Latch CLK input (TTL) Latch Data out (TTL)
N-3
N-2
N-1
CON5 Data out (TTL) DAC Data input (ECL)
N-4
N-3
N-2
N-3
N-2
N-1
DAC CLK input (ECL)
N-2 DAC Data OUT (0 to -1V) N-3 N-4
Item S/H CLK delay
Symbol T3 T4
Min.
Typ. 20 33 6 20
Max.
Unit ns ns ns ns ns ns
A/D CLK delay
T1 T2
A/D CLK width A/D output data delay
tpwh tpwl td
14 13 4 - 16 - 18
ns
CXA1843Q
S/H + A/D Evaluation Board Parts List
(No.) IC.1 IC.2 IC.3 IC.4 IC.5 IC.6 IC.7 IC.8, 9 D1, 3 D2 P1 SW.1 CON.5 CON.6 S1.3 VR1.2 C1 to 11 (Product Name) CXA1843Q CXA1844Q CLC505 CX20201A-1 74ACT34 74ACT163 74ACT16821 MB767 TL431CP 1S1555 2SA1175 DSS-105 FAP-2601-1201 TJ-563 JX-1 RJ-6P LS-2S (Function) Sample Hold 10bit ADC OP-AMP DAC Buffer Counter Latch ECL TTL level translator 3-pin shunt regulator Diode PNP transistor Switch SMA connector Flat cable connector Power supply connector Short-pin 2k volume resistor Check pin (No.) R1, 13, 38 R21, 25 R2, 22 R3, 4 R23 R12 R5, 8, 15, 16, 18, 19 R24 R11 R9 R14 R10 R6, 7, 17, 20 RN1 to 3 C2, 9 to 17, 19, 23 to 32 34 to 40, 42 to 60 C1, 6 to 8, 33, 41 C3 to 5, 20 to 22 C18 L1 to 4 Ceramic capacitor SF-T5-30-03 Tantalum capacitor 1F (Voltage proof of 35V) 33F (Voltage proof of 35V) 100pF 30F (Product Name) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) SN14C2F SN14C2F SN14C2F Chip resistor RGLD 4X621J Chip capacitor 620 0.1F (Function) 51 100 270 470 1k 4.7k 10k 51k 150k 1.5k 1.6k 2.7k
CON.1 to 4 TMA5502-10
Precautions 1. The monitoring pins are designed to be easily grounded in order to minimize distortions occurring when monitoring waveforms on an oscilloscope. Waveform monitoring is facilitated by using the grounded tip (part No. 013-1185-00) made by Tektronix at the end of the probe. 2. VR1 and VR2 are optimally adjusted and set before the board is shipped. 3. REX2, REX3, REX4 (R14, R10, R9) on the board use metal-oxide resistor, and T2, T3, T4 are optimally adjusted and set within the range of 1MHz to 33MHz.
- 17 -
CXA1843Q
S/H + A/D EVALUATION BOARD (Component Side)
S/H + A/D EVALUATION BOARD (Solder Side) - 18 -
S/H + A/D Evaluation Board
GND MINV DAINV PS LINV ENABLE DGND 1/1 1/2 1/4 1/8 1/16 S2 DVCC DGND2 DVCC2
6 5 4 3 16 15 14 13 12 11 10 9 2 1
VCC DGND2
CON.4
CLK
VEE DVEE2 (-5V) C5 L2 7H DVEE2 C5 33 DGND2 DVEE (-5V) C7 SW1
3A
2A
3Y
2Y
GND
1Y
1A
C37
EN T
0.1
A OUT
C40 0.1
L4 C6 DVCC2 (+5V) 7H DVCC2 CON.6 C22 33 DGND2 GND C8 DVCC (+5V) L1 L3 DVCC DVEE C21 7H C4 7H C11 33 33 DGND DGND AVEE (-5V) C9 C10 AVCC (+5V) AGND DGND2 AVCC AVEE DGND C3 C20 33 33 AGND AGND DGND 74ACT34 IC.5 74ACT163 IC.6 24
C45 0.1
4Y
5Y
6Y
4A
5A
6A
VCC
A IN
B IN
D IN
EN P
PS
NC
25 12 D9
12
GND1 GND1
ENABLE CLK
DGND2
DGND1
DVCC1
DGND4 DVCC2
MINV
DVEE
25
LINV
8
8 11 1 2 3 4 5 6 7 8 9 10 12 14 13
VCC CLEAR RCarry CLK
C IN
GND
8
24
23 22 20 21 17 16 15 14
19
18
13
DGND 13 14 DVCC2 1
C54 0.1
R38 51
ADCLK P4
26 11 27
DGND3 NC
10
D8 D7 DGND2 DGND2 D6
9
B OUT
C OUT
D OUT
DGND2
DGND
28 C2 29 8
NC VREFTS VRFET CXA1844Q IC.2 DGND D4
5 7
D5 GND1 GND1
6
AGND
31
VREFTS C36 0.1
30
VRFE1 VRFE2 VRFE3
4
AVCC
32
C35 0.1 C34 0.1
33
C25 0.1 D3 D2
3
C26 0.1 AGND
C27 0.1
34
VRFEB DGND2
2
MSB C8 C7 C6 C5 C4 C3 C2 C1 LSB DGND2
51 47 50 49 48 46 45 44 43 42 41
LOAD
R15R18 10k 10k DVEE DVCC
7
7
1 16 9
C56 0.1
R16R19 10k 10k DGND2
DGND2
40 39 38 37 36 35 34
DGND2
33 32 31 30 29
35
VREFBS 56
1 56 54 55 52 53
D1
NC
VINH
AVF
AVEE
UNDER
VCC
VCC
1D2
1D3
1D6
1D9
2D1
2D3
2D4
2D6
2D7
1D1
1D4
1D5
1D7
1D8
2D2
2D5
2D8
GND
NC
16
GND
REX2
C44 0.1
DVCC2 DVCC1
REFIN
AVCC4
C38 0.1
R17
R20
1OE_ 1CLK
1Q1
CLK OUT
C32 0.1 AGND P1
1 2 3 4 5 6
GND
1Q4
C59
AVCC
0.1
0.1
29
DVEE2
12
IC.1
10
AVCC3 AVCC
P2 NC
9
DGND DVEE C11 DVCC DVCC 0.1 C10 R7 0.1 R6 C28 0.1 9 AVEE
31
CLK IN
AVEE2
32
NC
UNDER
OVER
MCLK
30
DVCC3
SHOUT 11
C31 0.1 C30 0.1 C29 0.1 S/H out P3 DGND2 DGND2
DVCC DGND D2 AVEE C3 C4 AGND 1
DVCC2
CXA1843Q
DGND2
DGND2
DVCC2
25 25 NC C13 0.1 26 C12 DVEE1 0.1 27 REX3 C9 0.1 28 REX4
AVEE3
13
C59
R10 2.7k R9 1.5k
7
1Q5
REFOUT 14
R21 100
8
9
1Q7
10
11
1Q8
12
13
1Q10 1D10
14
15
2Q2
16
17
GND
18
19
2Q5
20
21
VCC
22
23
2Q8
24
25
2Q9
26
27
2OE_ 2CLK GND 1Q6 GND 1Q9 2Q1 2Q3 2Q4 2Q6 2Q7 GND 2Q10 2D10
ACT1682 1 IC.7 DGND2 DGND2 DGND2
AVEE1
VIN
AVCC1 HGND
CGND
NC
NC
NC
0.1
C57
C52
0.1
DGND2 AGND 20 20
19 18 17 16 15 14 13 12 11
DGND2 11 20 20
19 18 17 16 15 14 13 12 11
MSB 11 D8
D9
S
IN1
IN2
IN4
IN6
IN1
IN3
IN5
IN7
IN8
IN2
IN4
VCC
IN6
IN8
R24 51k
R25 100
VCC
DVEE
15
IN3
IN5
IN7
D7 MB767 IC.8 MB767 IC.9 D6
DVEE
14
CLKB DVEE
13
D7 D6
C42 0.1
OUT8
OUT6
OUT4
GND
OUT3
VEE
OUT5
OUT7
VEE
OUT5
OUT2
C46 0.1
OUT1
OUT3
OUT1
OUT2
OUT4
GND
OUT6
0.1
DGND
18
17
DGND AGND1 NC OUT NC NC NC NC NC AVEE VREF AGND2
C48
DGND C51 0.1 RN1 C50 0.1 CLK 1 LSB D1 DGND RN2 C49 0.1 D2 D3 D4 D5 DGND D6 D7 D8
OUT7
OUT8
16
INV
CLK
D5
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
D5
C53 0.1
C58 0.1
10 1
10 DGND2
D4 D3 D2 D1 LSB
D4 D3
AGND
19
CON.3 D/A out
20
DVEE2
DGND2
DVEE2
D2 D1 D0
DGND DGND DGND DGND CLK CLK
AGND
22 23
24
AGND AVEE
A
CX20201A-1
1 C2 AVCC 0.1 C23 C19 R2 R3 0.1 0.1 C1 270 470 C6 1 AVCC AVEE C 1 D1 R5 AGND A Vref 10k AVCC AGND VR1 AGND 2K C15 C8 OFFSET 0.1 1 VIN P1 AGND ADJ R8 10k AGND AGND CON.1 VIN R12 7 15 R4 S1 2 47 4.7k R1 8 IC.3 A 51 6 3 4 R11 C18 AGND B 150k 100P C14 C7 R13 AGND 0.1 1 51 CON.2 AVEE AGND AGND AGND DIR.in 15 14
21
S
DGND2
D3
C
Vref
R1 21 AGND
FULL 25 C43 0.1 SCALE ADJ 26 VR2 2K 27 C47 C41 1 R23 1k 0.1 28 28
R37 620 NC 12 R36 DGND 620 NC 11 R35 620 D10 10 R34 620 D9 9 R33 620 D8 8 R32 620 D7 7 R31 620 D6 6 R30 620 D5 5 R29 620 D4 4 R28 620 D3 3 R27 620 D2 2 R26 620 D1 1 1
CXA1843Q
RN3
MSB
DGND2
D8
C60 0.1
- 19 -
C39 0.1
NC
16
36 37 48
37 38 39 41 47 42 43 44 45 48 46
40
REFFB 15
1Q2
1Q3
VCC
DGND DVEE
GND
GND
2D9
24
23 17
22
21
20
19
18
C33 1 C1 AGND VREFBS 17 AGND
NC
VINL
NC
NC
DVCC2
OVER GND1
DGND
36
C17 DVCC R14 0.1 DGND 1.6k C24 0.1 C16 0.1 24 NC 1 D0
29
28
28 DGND2
DGND DGND
8
32 8
DVCC2
DVCC2
CON.5 DVCC
DVCC2
1
2
3
4
5
6
7
CXA1843Q
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.24
M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
- 20 -
0.50
(8.0)

▲Up To Search▲

Price & Availability of CXA1843Q

	To Download CXA1843Q Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .