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CXA2055P
Preamplifier for High Resolution Computer Display
Description The CXA2055P is a bipolar IC developed for high resolution computer displays. Features * Built-in wide band amplifier (130 MHz/-3 dB typ.@4 Vp-p) * Input dynamic range : 1.0 Vp-p (typ.) * R, G and B in a single package * I2C bus control Contrast control Subcontrast control Brightness control OSD contrast control Power save function Input clamp pulse polarity selection Output composite sync polarity selection 5-channel, 8-bit D/A Blanking level control * Built-in sync separator (G channel only) * Built-in blanking mixing function * Built-in OSD mixing function * Built-in ABL function * Video interval detection function Applications High resolution computer displays Structure Bipolar silicon monolithic IC 28 pin DIP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VCC 14 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 1794 mW (when mounted on a 11.5 cm x 12.0 cm substrate) Operating Conditions Recommended supply voltage VCC1 VCC2
1 SDA VDET/COFF-RGB 28 2 SCL 3 COFF-R 4
COFF-G DA/CSYNC/ABL 27 R-S/H 26 R-OUT 25 GND-R 24 G-S/H 23 G-OUT 22 GND-G 21 VCC1 20 B-S/H 19 B-OUT 18 GND-B 17 BLK 16 YS 15
120.5 50.25
V V
5 COFF-B 6 RIN 7 VCC2 8 GIN 9 SYNC CON
10 BIN 11 CLP 12 OSD-R 13 OSD-G 14 OSD-B
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E96Z18-TE
CXA2055P
SDA
1
I2C BUS DECODER
D/A CONVERTER
CUTOFF (RGB) CONTRAST SUB CONTRAST (R) SUB CONTRAST (G) SUB CONTRAST (B) OSD GAIN BRIGHTNESS (R) BRIGHTNESS (G) BRIGHTNESS (B)
28
PINSW1
VDET /COFF-RGB DA /CSYNC /ABL
SCL
2
To each MODE switch
BLANKING VDET LEVEL CUTOFF (R) CUTOFF (G) CUTOFF (B)
27
PINSW LOGIC PINSW0, 2
COFF-R
3
Rch
BRIGHTNESS (R, G, B)
26
R-S/H
COFF-G
4
25
SUB CONTRAST ABL (27PIN) CONTRAST
R-OUT
COFF-B
5
GAIN CONTROL DATA GAIN CONTROL AMP
BLANKING
BRIGHTNESS
24
GND-R
RIN
6
OSD GAIN
BLANKING BUFFER AMP
BLANKING PULSE
OSD YS GENERATOR OSD LOGIC OSD PULSE (12PIN) YS PULSE (15PIN)
23
G-S/H
VCC2
7
5V
22 VDET, SYNC SEP
VDET COMPARATOR SYNC COMPARATOR SYNC POL 12V
G-OUT
GIN
8
21
GND-G
VDET LEVEL
SYNC CON
9
Gch
20
VCC1
BIN 10
CLP POL
19 Same as R channel 18
B-S/H
CLP 11
B-OUT
OSD-R 12
to OSD LOGIC
Bch Same as R channel
17
GND-B
OSD-G 13
to OSD LOGIC
16
BLK
OSD-B 14
to OSD LOGIC to OSD LOGIC
15
YS
--2--
CXA2055P
Pin Description Pin No. Symbol Pin voltage
VCC2 50A 4k 5k 10k 10k
Equivalent circuit
Description
1
SDA
--
1
7.5k 7.5k GND
I2C bus address and data input.
15k
VCC2 50A 4k 5k 10k 10k GND 10k
2
SCL
--
2
I2C bus clock signal input.
15k
3
COFF-R
100 60k
VCC2
4
COFF-G
--
50k 100
3 4 5
D/A converter outputs. The variable range is 1 to 4 V. Use as cut-off control voltages is recommended.
5
COFF-B
GND
6
RIN
VCC1 VCC2
1k
1k
8
GIN
--
6 8
10
124
5k 2k 2k 50A 1mA 1k
10
BIN
GND
R, G and B inputs. When clamped, the input voltage black level is approximately 3.2 V. Connect 0.1 F or more in series as a clamp capacitor.
7
VCC2
5V
5 V power supply.
--3--
CXA2055P
Pin No.
Symbol
Pin voltage
VCC2
Equivalent circuit
Description
24k
70k
9
SYNC CON
9
10k 50A 50A 1k GND VCC1 22A 30k
Sync signal separation circuit block during sync-on-video signal input. Connect a sampleand-hold capacitor.
11
CLP
--
11 1.3V
Clamp pulse input. The polarity can be switched via the I2C bus. The threshold level is approximately 1.3 V.
GND
12
OSDR
VCC1 150A
13
OSDG
--
124 12 13 14 1.25V
R, G and B OSD pulse inputs. The threshold level is approximately 1 V.
14
OSDB
GND
VCC1 150A
15
YS
--
124 15 1.25V
OSD-BLK pulse input. The threshold level is approximately 1.7 V.
GND VCC1
49k
16
BLK
--
124 16
BLK pulse input. The threshold level is approximately 1.5 V.
1.5V
100A GND
--4--
CXA2055P
Pin No. 17 21 24
Symbol GND-B GND-G GND-R
Pin voltage
Equivalent circuit
Description
0V
R, G and B independent GND.
18
B-OUT
VCC1
22
G-OUT
--
200
18 22 25
R, G and B outputs.
25
R-OUT
GND
19
B-S/H
1k
1k
1k 1k
VCC1
23
G-S/H
--
19 23 26 225A 2.5V GND
Connection for external sampleand-hold capacitor (0.1 F).
26
R-S/H
21
VCC1
12 V
12 V power supply. General-purpose D/A converter output. Composite sync output. TTL drive is possible. VL=0.5 V or less, VH=4.0 V or more RGB output amplitude gain compensation input. (common for all three channels) Function switching is performed via the I2C bus. Video signal detection output. VL=0.5 V or less, VH=4.0 V or more General-purpose D/A converter output. The variable range is 1 to 4 V. Function switching is performed via the I2C bus.
VCC2 5k 100 4k 50k 1V
27
DA /CSYNC /ABL
100 27
100k GND
7.4k
VCC2 100 5k
28
VDET /COF-RGB
--
100 100
28
GND
--5--
CXA2055P
Electrical Characteristics Measurement Circuit
1 SDA VDET/COFF-RGB 28
I2C bus control
Video detector output DAC4 output
2 SCL
DA/CSYNC/ABL 27
Composite sync output DAC5 output S2
DAC1 output
3 COFF-R
R-S/H 26 0.1
ABL input
DAC2 output
4 COFF-G
DAC3 output
R-OUT 25
Rch OUT
5 COFF-B
75 0.1 0.1 5V 10 0.1 75
GND-R 24
6 RIN
G-S/H 23 0.1
7 VCC2
G-OUT 22
Gch OUT
8 GIN
GND-G 21
0.01
9 SYNC CON
VCC1 20
12V 10
75
0.1
0.1 10 BIN B-S/H 19 0.1 S1 11 CLP B-OUT 18 Bch OUT
12 OSD-R
GND-B 17
13 OSD-G
BLK 16
14 OSD-B
YS 15
--6--
CXA2055P
Electrical Characteristics Measurement Circuit (For AC Measurement)
1 SDA VDET/COFF-RGB 28
I2C bus control
Video detector output DAC4 output DAC5 output
2 SCL
DA/CSYNC/ABL 27
Composite sync outpt ABL input
DAC1 output
3 COFF-R
R-S/H 26
DAC2 output
4 COFF-G
DAC3 output
R-OUT 25
Rch OUT
5 COFF-B
50 0.1 5k
GND-R 24
6 RIN
G-S/H 23
5V 10 50 0.1 0.1 5k
7 VCC2
G-OUT 22
Gch OUT
8 GIN
GND-G 21
9 SYNC CON
0.01 50 0.1 5k 11 CLP 10 BIN
VCC1 20
12V 10 0.1
B-S/H 19
B-OUT 18
Bch OUT
12 OSD-R
GND-B 17
13 OSD-G
BLK 16
14 OSD-B
YS 15
--7--
CXA2055P
Electrical Characteristics No. Measurement item Current consumption Symbol ICC1 (12 V) ICC2 (5 V)
Input continuous 1 MHz and 130 MHz sine waves at 0.7 Vp-p. Measure the output amplitude gain difference at this time. VOUT 130M VOUT 1M
Ta=25 C VCC1=12 V VCC2=5 V Measurement contents
S1 : GND, S2 : OFF Input signal : none
Min. -- --
Typ. 82 40
Max. 115 55
Unit mA mA
1
2
Frequency response
Gain difference [dB] =20log
(
)
-- -3.0 -- dB
f 130 MHz
RGB input signal (RGB input pins)
0.7Vp-p 0.35V CLP potential (approximately 3.2 V) GND
S1 : Pulse, S2 : OFF Measure the output signal amplitude VOUT when a 0.7 Vp-p video signal is input. Calculate the contrast gain from this VOUT. VOUT 0.7
3
Contrast control
CONTMAX [dB] =20log
(
)
16.0 16.5 -- dB
CONTMAX
RGB input signal 0.7Vp-p
Either with or without sync-on-green (sync signal)
S1 : Pulse, S2 : OFF Measure the variable width of the output signal amplitude VOUT when a 0.7 Vp-p video signal is input. Gain difference [dB]=
4
Subcontrast gain
SUBgain
CONTMAX [dB] -20log
RGB output signal
( VOUTSUBmin ) 0.7
SUBmax SUBmin
10.5
13.5
--
dB
Either with or without sync-on-green (sync signal)
--8--
CXA2055P
No.
Measurement item
Symbol
Measurement contents
S1 : Pulse, S2 : OFF
Min.
Typ.
Max.
Unit
BRTmax 5 Brightness control BRTmin
CLP pulse width: 350 ns Measure the black level of the RGB output signal.
RGB output signal
3.4
3.7
-- V
Black level GND Either with or without sync-on-green (sync signal)
--
0.5
0.7
S1 : Pulse, S2 : OFF
6
Input dynamic range
Drang
Measure the level at which the output gain can be secured when the input video signal level is varied. S1 : Pulse, S2 : OFF Measure the clamp pulse width over which the black level of the output signal VOUT
0.9
1
1.2
Vp-p
7
Minimum clamp pulse width
does not change.
CLPmin
Video input Pulse width CLP pulse
200
--
--
nsec
S1 : Pulse, S2 : OFF Measure the variable width of the output signal VOUT when a 0.7 Vp-p video signal is input. OSDmax OSDmin
8
OSD control range
OSDcont
Gain difference [dB] =20log
(
)
4.0
5.0
--
dB
OSD interval RGB output signal OSDmax
OSDmin
S1 : Pulse, S2 : OFF Measure the BLK level of the output signal
BLKmax
when a 5.0 Vp-p BLK signal is input
1.7
1.9
--
9
BLK control
RGB output signal
V
BLKmin
VBLK GND
--
0.1
0.4
--9--
CXA2055P
(I2C BUS Logic System) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Item High level input voltage Low level input voltage Low level output voltage SDA, during current inflow of 3 mA Maximum clock frequency Minimum waiting time for data change Minimum waiting time for data transfer start Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation Symbol VIH VIL VOL fSCL tBUF tHD ; STA tLOW tHIGH tSU ; STA tHD ; DAT tSU ; DAT tR tF tSU ; STO Min. 3.0 0 0 0 4.7 4.0 4.7 4.0 4.7 5 250 -- -- 4.0 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 0.4 100 -- -- -- -- -- -- -- 1000 300 -- Unit V V V kHz s s s s s s ns ns ns s
I2C BUS Control Signal
1
SDA tBUF tR tF tHD;STA
2
SCL
P
S
tLOW tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
Sr
tSU;STO
P
--10--
CXA2055P
1. Application The CXA2055P is a preamplifier for computer displays, and combines three R, G and B channels into a single package. All controls such as the contrast and black level for each channel are performed via I2C bus control. 1) I2C bus Two wires (SDA, SCL) provide control over start, stop, data transfer, synchronization and collision avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR format. The bus signal configuration is as follows.
SDA
D
A
T
A
A
D
A
T
A
MSB SCL S 1 START 2 3 4 5 6 7
LSB
MSB
LSB
P 8 9 1 2 3 9 STOP S : Start condition; SDA is set at "low" when SCL is "high". P : Stop condition; SDA is set at "high" when SCL is "high". A : Acknowledge; Signal sent from the slave.
Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave 1 IC receives data at the rising edge of SCL and the master 2 IC changes data at the falling edge of SCL. The actual data format is as follows. Slave address 40H Subaddress H
S
A
A
DATA0
A
DATA1
A
DATA2
A
P
Slave address configuration BIT8 BIT7 BIT6 BIT5 BIT4 Slave address BIT3 BIT2 BIT1 R/W
The slave address is an address unique to each IC, and is assigned according to the IC functions. The upper 7 of the 8 bits are the unique address and the final bit is the R/W bit. The R/W bit indicates read 3 when 1 and write 4 when 0. 40H is allotted as the slave address for the CXA2055P. (This is write only and there is no read mode.) The subaddress is the assigned address within the IC, and is used for the various IC adjustments. The subaddress is sent just once following the slave address, and is automatically incremented thereafter until a stop condition is sent. 1 Slave : An IC that is placed under the control of the master. In a normal system, all devices excluding the central microcomputer are slaves. 2 Master : A central microcomputer or other controlling IC. 3 Read : Mode where data is read from master to slave. 4 Write : Mode where data is written from master to slave. --11--
CXA2055P
2) Register map * Slave address : 40H * "" indicates undefined. * Values inside parentheses ( ) are the initial setting values (during power-on reset) (undetermined when not indicated) Slave address configuration BIT8 0 BIT7 1 BIT6 0 BIT5 0 BIT4 0 BIT3 0 BIT2 0 BIT1 R/W
SUB ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH
BIT7
BIT6
BIT5
BIT4 BIT3 CONTRAST SUB CONTRAST R SUB CONTRAST G SUB CONTRAST B OSD GAIN BRIGHTNESS R (DA) BRIGHTNESS G BRIGHTNESS B CUT OFF RGB CUT OFF R CUT OFF G CUT OFF B
BIT2
BIT1
BIT0
BRT MODE (2)
BLK (0) MODE BRT SW (0)
SYNC POL (0) VDET POWER MODE (0) SAVE (0)
BLANKING LEVEL (0) D/A TEST (0) CLP (0) PINSW2 (0) VDET LEVEL PINSW1 (0) PINSW0 (0)
--12--
CXA2055P
3) Description of registers (Numbers inside parentheses ( ) indicate the number of bits.) CONTRAST (8) : Adjusts the R, G and B-OUT (Pins 25, 22 and 18) output amplitude gain commonly for all three channels. Adjusts the R, G and B-OUT (Pins 25, 22 and 18) output amplitude gain independently for each channel. Adjusts the OSD R, G and B (Pins 12, 13 and 14) OSD interval output signal gain commonly for all three channels. This register changes the output dynamic range. The 2H setting is recommended. 0H : Output dynamic range 0.5 V to 4.5 V 1H : Output dynamic range 0.5 V to 5.5 V 2H : Output dynamic range 1.0 V to 6.5 V (recommended) 3H : Output dynamic range 2.0 V to 7.5 V Controls the output black level potential. (Three-channel independent and common control can be selected by BRTSW. During three-channel common mode, control is performed by the G channel.) This is a general-purpose DAC. Use as a cut-off control is recommended. Switches the blanking level mode 0H : BLK LEVEL=fixed 1H : BLK LEVEL=variable Sets the blanking level when BLK MODE is set to 1H. Switches the brightness control between three-channel independent and three-channel common control. When using three-channel common mode, the BRIGHTNESS G channel is valid. 0H : Three-channel independent mode 1H : Three-channel common mode Switches the sync separator output polarity during sync-on-green input. 0H : Positive polarity 1H : Negative polarity Switches the video signal detection mode. 0H : B channel only is detected 1H : Signal obtained by adding R, G and B signals is detected Power save mode selector switch. 0H : Power save not performed 1H : Power save performed --13--
SUB CONTRAST (8)
:
OSD GAIN (4)
:
BRTMODE (2)
:
BRIGHTNESS (8)
:
CUT OFF (8) BLK MODE (1)
: :
BLANKING LEVEL (6) BRTSW (1)
: :
SYNC POL (1)
:
VDET MODE (1)
:
POWER SAVE (1)
:
CXA2055P
CLP (1)
:
Selects the input clamp pulse polarity. 0H : Positive polarity input 1H : Negative polarity input Threshold level selector switch for video interval detection. The threshold level changes as follows. (An input pulse width of as narrow as 10 ns can be detected.) When VDET MOD=0H When VDET MOD=1H 0H : 300 mV or more 0H : Undetectable 1H : Undetectable 1H : Undetectable 2H : Undetectable 2H : 300 mV or more 3H : Undetectable 3H : 600 mV or more Note) The threshold level when VDET MOD=1H is the total of the three channel inputs. DA TEST switch for IC measurement. Set to 0H. Switches the Pins 27 and 28 functions. ("" indicates don't care.)
VDET LEVEL (2)
:
D/A TEST (1) PINSW
: :
2 0 1 0 1
PINSW 1 0 0 1 1 0 1
0 0 0 0 0 1 1
Pin 28 output DA (COFF_RGB) DA (COFF_RGB) VDET VDET DA (COFF_RGB) VDET
Pin 27 output C-SYNC ABL (CONTRAST) C-SYNC ABL (CONTRAST) DA (BRIGHTNESS) DA (BRIGHTNESS)
Note) When the Pin 27 output is set to DA (BRIGHTNESS), BRIGHTNESS is forcibly set to the three-channel common mode.
--14--
CXA2055P
2. Blanking addition function The output is blanked while the BLK pin (Pin 16) is high level. The BLK pin threshold level is approximately 1.5 V. 3. OSD addition function and OSD contrast control OSD can be added to the video signal while the OSD-R, G and B pins (Pins 12, 13 and 14) are high level. OSD blanking is added when any of these three channels is high level. OSD blanking is also added to all three channels while the YS pin (Pin 15) is high level. See the following logic.
Ys Circuit (R, G, B) YS PULSE
from 15pin
1 : Active 0 : Passive OSD Circuit (R) 1 : Active 0 : Passive OSD Circuit (G) 1 : Active 0 : Passive
OSD PULSE (R)
from 12pin
OSD PULSE (G)
from 13pin
OSD PULSE (B)
from 14pin
OSD Circuit (B) 1 : Active 0 : Passive
4. CONTRAST function The CONTRAST function performs gain control for the R, G and B-OUT output amplitudes. 5. ABL function ABL control can be performed by Pin 27 by setting PINSW. The variable range is approximately 13.7 dB. See the characteristics diagrams hereafter for the control characteristics.
--15--
CXA2055P
I/O Signal Example
0.7Vp-p (typ) Video In Clamp DC voltage Approximately 3.2 V tCLP 200nsec
GND Clp Pulse
Blanking Pulse
Ys Pulse
OSD Pulse
Video Out
C-Sync Out
Vdet Out
--16--
CXA2055P
Application Circuit
DAC1 output DAC2 output DAC3 output
1 SDA VDET/COFF-RGB 28
I2C bus control
Video detector output DAC4 output
2 SCL
DA/CSYNC/ABL 27
Composite sync output ABL input (0V to 4V) DAC5 output
3 COFF-R
R-S/H 26 0.1 Rch DISPLAY POWER AMP
Rch to CRT cathode
4 COFF-G
R-OUT 25
5 COFF-B
GND-R 24
0.1 Rch video input 75 0.1 5V 10 0.1 Gch video input 75 0.1 12V 10 0.1 75 0.1 Clamp pulse input 11 CLP B-OUT 18 Bch DISPLAY POWER AMP Bch to CRT cathode 0.1 10 BIN B-S/H 19
6 RIN
G-S/H 23 0.1 Gch to CRT cathode
7 VCC2
G-OUT 22
8 GIN
GND-G 21 Gch DISPLAY POWER AMP
9 SYNC CON
VCC1 20
Bch video input
Rch OSD input
12 OSD-R
GND-B 17
Gch OSD input
13 OSD-G
BLK 16
BLANKING pulse input
Bch OSD input
14 OSD-B
YS 15
YS input
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
--17--
CXA2055P
Notes on Board Pattern and Layout 1. When not using the OSD, YS or BLK pins, connect these pins to GND. 2. Care should be taken for the following items regarding the output signals from R, G and BOUT. 1) Connect these signal lines so that they are high impedance to external circuits. 2) Do not allow current to flow into the IC side. 3) Arrange the signal lines so that the distance to the power amplifier is as short as possible. 3. The VCC1 and VCC2 decoupling capacitors should consist of ceramic capacitors and electrolytic capacitors connected in parallel, and should be connected as close to the IC as possible. 4. The R, G and BIN clamp capacitors should be located as close to the IC as possible. 5. The sample-and-hold capacitors connected to the R, G and B-S/H pins should be connected as close to the IC as possible. 6. The output signals from COFF-R, G and B should be arranged so that capacitance of 20 pF or more is not applied to the pins or the pattern.
--18--
CXA2055P
Contrast control characteristics, subcontrast control characteristics Input amplitude 700mVp-p mVp-p 5000 4500 4000
Subcontrast Control=FFH
ABL characteristics mVp-p 5000 4500 4000
Output amplitude
3000 2500 2000 1500
Subcontrast Control=7FH
Output amplitude
Subcontrast Control=00H
3500
3500 3000 2500 2000 1500 1000 500 0 0 1 2 3 4 5 Control voltage V
1000 500 0 0 32 64 96 128 160 192 224 BUS DATA
Brightness control characteristics V 4.000 3.500
BLK control characteristics mV 2000 1800 1600
Output black level
3.000 2.500 2.000 1.500 1.000 0.500 0.000 0 32 64 96 128 160 192 224 BUS DATA
Output BLK level
1400 1200 1000 800 600 400 200 0 0 8 16 24 32 40 48 56 BUS DATA
OSD control characteristics mVp-p 6000 5500 5000
Subcontrast Control=FFH
4500 4000
OSD interval output amplitude
3500 3000 2500 2000 1500 1000 500 0 0 2 4 6 8
Subcontrast Control=00H Subcontrast Control=7FH
10
12
14
BUS DATA
--19--
CXA2055P
Package Outline
Unit : mm
28PIN DIP (PLASTIC)
+ 0.1 0.05 0.25 -
15
+ 0.4 37.8 - 0.1
28
+ 0.3 13.0 - 0.1
1 2.54
14
0.5 0.1 1.2 0.15
Two kinds of package surface: 1.All mat surface type. 2.Center part is mirror surface.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER ALLOY 4.2g
SONY CODE EIAJ CODE JEDEC CODE
DIP-28P-03 DIP028-P-0600
--20--
3.0 MIN
0.5 MIN
LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
+ 0.4 4.6 - 0.1
15.24
0 to 15

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