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| CXG1030N Power Amplifier for PHS Description The CXG1030N is a power amplifier for PHS. This IC is designed using the Sony's GaAs J-FET process and operates at a single power supply. Features * Output power 21 dBm * Positive power supply 3.0 V * Low current consumption 170 mA * High power gain 39 dB Typ. * Small mold package 16-pin SSOP Structure GaAs J-FET MMIC 16 pin SSOP (Plastic) Absolute Maximum Ratings (Ta=25 C) * Supply voltage VDD 6 V * Voltage between gate and source Vgs0 1.5 V * Drain current IDD 500 mA * Power dissipation PD 3 W * Channel temperature Tch 175 C * Operating temperature Top -35 to +85 C * Storage temperature Tstg -65 to +150 C Electrical Characteristics VDD=3.0 V, VCTL=2.0 V, f=1.90 GHz Item 1 Current consumption 1 Gate voltage adjustment value Output power 2 Power gain 2 Adjacent channel leak power ratio (600 kHz 100 kHz) Symbol IDD VGG2 POUT GP ACPR600 Min. 0 21 36 Typ. 170 0.4 39 -59 -54 Max. 0.8 (Ta=25 C) Unit mA V dBm dB dBc 1 Values where VGG1 and VGG2 are adjusted so that IDD becomes 170 mA when 21.0 dBm is output. 2 When 21.0 dBm is output. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. --1-- E96706-TE CXG1030N Block Diagram Pin Configuration 1 GND RFIN GND 16 GND VGG1 VCTL GND VGG2 GND RFOUT GND VDD1 VDD2 VDD3 RFIN RFOUT VDD1 GND VDD2 GND VGG1 VCTL VGG2 VDD3 Gate Bias Circuit Gate adjustment pin VGG2 1k VGG1 Recommended Current Adjustment Method (1) VGG2/PIN separate adjustment (VGG2 adjustment 1) When the RF input (PIN) is off, the current consumption (IDD) is adjusted to 170 mA. Variation of IDD and POUT due to adjustment (2) Simple adjustment (IDD read) When the RF input (PIN) is off, the gate voltage (VGG2) is set to 0.4 V and IDD is read. Variation of IDD and POUT due to adjustment (VGG2 setting) The formula1 where VGG2=f (IDD: VGG2=0.4 V) is used to set VGG2. 1 e.g. VGG2=a-b x IDD (PIN adjustment) (PIN adjustment 1) The output power (POUT) is adjusted to 21.0 dBm. IDD=17020 mA POUT=21.0 dBm (VGG2 adjustment 2) The current consumption (IDD) is finely adjusted to 170 mA. IDD=170 mA POUT=21.00.2 dBm (PIN adjustment 2) The output power (POUT) is finely adjusted to 21.0 dBm. IDD=1705 mA POUT=21.0 dBm The output power (POUT) is adjusted to 21.0 dBm. IDD=1705 mA POUT=21.0 dBm --2-- CXG1030N Recommended Evaluation Circuit VCTL VGG2 3.0V C2 GND C2 100 6.8k 1k L4 RFIN C2 L1 C2 C1 C2 C1 L5 C4 L3 C3 C1 Variable resistor RV 10k (Max.) RFOUT 1k 180 L2 Via Hole GND C2 Glass fabric-base epoxy board GND for the overall back side Dimension : 5cm x 5cm Thickness : 0.2mm C1=100pF L1=18nH C2=1nF L2=10nH C3=10nF L3=1.8nH C4=1pF L4=3.9nH VDD L5=2.7nH Recommended Gate Bias Circuit and Circuit Characteristics 3.0V (V) VGG2 100 RV1 VGG2 RV2 6.8k 0.5 Variable resistor RV 10k (Max.) 180 1k 0 5 10 RV1 (V) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. --3-- CXG1030N Example of Representative Characteristics (Ta=25 C) POUT, ACPR vs. PIN VDD=3.0V, VCTL=2.0V, VGG=const., IDD=170mA (@POUT=21.0dBm) 25 -40 20 -45 POUT ACPR 15 -50 10 -55 5 -60 0 -65 -5 -45 -70 -40 -35 -30 -25 -20 -15 -10 -5 PIN-Input power (dBm) ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset) Gp, ACPR vs. IDD VDD=3.0V, VCTL=2.0V, POUT=21.0dBm, VGG=var. 41 -54 -55 40 -56 -57 POUT, ACPR vs. VDD VDD=3.0V, VCTL=2.0V, PIN=-18.0dBm, VGG=const., IDD=170mA (@POUT=21.0dBm) 23 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 5.0 5.5 ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset) POUT-Output power (dBm) POUT-Output power (dBm) 22 POUT ACPR 21 39 Gain ACPR -58 -59 38 -60 -61 37 -62 -63 20 36 -64 -65 -66 35 110 120 130 140 150 160 170 180 190 200 210 220 230 IDD-Current consumption (mA) 19 2.0 2.5 3.0 3.5 4.0 4.5 VDD-Drain voltage (V) --4-- ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset) Gp-Power gain (dB) CXG1030N Package Outline Unit : mm 16PIN SSOP (PLASTIC) 5.0 0.1 + 0.2 1.25 - 0.1 0.1 16 9 A 4.4 0.1 1 + 0.1 0.22 - 0.05 8 0.65 0.12 + 0.05 0.15 - 0.02 0.1 0.1 0 to 10 DETAIL A NOTE: Dimension "" does not include mold protrusion. : PALLADIUM PLATING This product uses PdPPF PACKAGE (Palladium Pre-Plated Lead Frame). SONY CODE EIAJ CODE JEDEC CODE SSOP-16P-L01 SSOP016-P-0044 0.5 0.2 STRUCTURE EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.1g PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT --5-- 6.4 0.2 |
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