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| KS57C4104/P4104/C4204/P4204/C4304/P4304 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The KS57C4104/KS57C4204/KS57C4304 single-chip CMOS microcontroller has been designed for very high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontroller). With an A/D converter, LED direct drive pins, an 8-bit serial I/O interface, and an 8-bit timer/counter, the KS57C4104/KS57C4204/KS57C4304 offers you an excellent design solution for a wide variety of home appliance applications -- electric fans, cookers, boilers, and air conditioners, for example. Up to 35 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events. In addition, the KS57C4104/KS57C4204/KS57C4304's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The KS57C4104/KS57C4204/KS57C4304 microcontroller is also available in OTP (One Time Programmable) version, KS57P4104/KS57P4204/KS57P4304. KS57P4104/KS57P4204/KS57P4304 microcontroller has an onchip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The KS57P4104/KS57P4204/KS57P4304 is comparable to KS57C4104/KS57C4204/KS57C4304, in function, in D.C. electrical characteristics and in pin configuration. DEVELOPMENT SUPPORT The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for KS57-series microcontrollers that is powerful, reliable, and portable. In addition to its window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction timing, and performance measurement applications. The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard hex files that also contain program control data for SMDS compatibility. 1-1 PRODUCT OVERVIEW KS57C4104/P4104/C4204/P4204/C4304/P4304 FEATURES SUMMARY Memory * * 256 x 4-bit RAM 4,096 x 8-bit ROM Built-in reset circuit (KS57C4304 only) * Built-in power-on reset circuit Interrupts * * * Five internal vectored interrupts (INTB, INTT0, INTT1, INTS, INTAD) Three external vectored interrupts (INT0, INT1, INT4) Two quasi-interrupts (INT2, INTW) 35 I/O Pins * I/O: 31 pins including 8 LED direct drive pins (KS57C4104/C4304) 18 pins including 8 LED direct drive pins (KS57C4204) Input only: 4 pins * Bit Sequential Carrier A/D Converter * * 6-channel with 8-bit resolution 22.89 s conversion speed at 4.19 MHz * Supports 16-bit serial data transfer in arbitrary format Memory-Mapped I/O Structure * Data memory bank 15 Basic Timer * * * One 8-bit basic timer Watchdog timer functions Four interval clock selection Two Power-Down Modes * * Idle mode (only CPU clock stops) Stop mode (system oscillation stops) Timer/Counters * * * * * Two 8-bit timer/counter (TC0, TC1) Programmable 8-bit timer External event counter Arbitrary clock frequency output PWM output mode (TC1) Oscillation Sources * * * * Crystal, Ceramic, or RC for system clock Crystal, Ceramic: 0.4-6.0 MHz RC: 4 MHz (typ) CPU clock divider circuit (by 4, 8, or 64) Instruction Execution Times Watch Timer * * * One watch timer 8-bit Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz Four frequency outputs to BUZ pin * * 0.95, 1.91, 15.3 s at 4.19 MHz 0.67, 1.33, 10.7 s at 6.0 MHz Operating Temperature * - 40 C to 85 C 8-bit Serial I/O Interface * * * * 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock source Operating Voltage Range * * 1.8 V to 5.5 V (KS57C4104/C4204) 2.5 V to 5.5 V (KS57C4304) Package Type * 42-pin SDIP, 44-pin QFP (KS57C4104/C4304) 30-pin SDIP, 28-pin SOP (KS57C4204) 1-2 KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA 14 OVERVIEW ELECTRICAL DATA In this section, information on KS57C4104/C4204/C4304 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- System clock oscillator characteristics -- Operating voltage range -- A.C. electrical characteristics -- A/D converter electrical characteristics -- I/O capacitance Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request Miscellaneous Timing Waveforms -- A.C timing measurement points (except for XIN) -- Clock timing measurement at XIN -- TCL0/1 timing -- Input timing for RESET signal -- Input timing for external interrupts and quasi-interrupts -- KS57C4304 power-on RESET timing -- Serial data transfer timing 14-1 ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 Table 14-1. KS57C4104/C4204 Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL One pin All output pins Output Current Low One pin peak value rms value All pins Operating Temperature Storage Temperature TA Tstg peak value rms value - - Duty . (note) (note) Conditions - All I/O ports - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 35 + 30 + 15 + 100 + 60 - 40 to + 85 - 65 to + 150 Units V V V mA mA C C NOTE: The values for Output Current Low (IOL) are calculated as Peak Value x 14-2 KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA Table 14-2. KS57C4104/C4204 D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage Output Low Voltage VOH Conditions All input pins except those specified below for VIH2-VIH3 Ports 0, 1, 3, 6 and RESET XIN, XOUT All input pins except those specified below for VIL2-VIL3 Ports 0, 1, 3, 6 and RESET XIN, XOUT VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 2-8 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4 and 5 only IOL = 4 mA All output ports except ports 4 and 5 VI = VDD All input pins except those specified below for ILIH2 VI = VDD XIN and XOUT only VI = 0 V All input pins except XIN and XOUT, RESET Min 0.7 VDD 0.8 VDD VDD - 0.1 - Typ - Max VDD VDD VDD Units V - 0.3 VDD 0.2 VDD 0.1 V VDD - 1.0 - - V VOL - 0.4 2 V 0.2 - - 3 A Input High Leakage Current ILIH1 ILIH2 Input Low Leakage Current ILIL1 20 - - -3 A ILIL2 Output High Leakage Current Output Low Leakage Current Pull-up Resistor ILOH ILOL RL1 RL2 VI = 0 V XIN and XOUT only VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 5 V except RESET VI = 0 V; VDD = 3 V except RESET VI = 0 V; VDD = 5 V; RESET VI = 0 V; VDD = 3 V; RESET - - 25 50 100 200 - - 50 100 250 500 - 20 3 -3 100 200 400 800 k A A k Pull-up Resistor 14-3 ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 Table 14-2. KS57C4104/C4204 D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 Conditions Run mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz Min - Typ 3.0 2.3 1.4 1.1 Max 8.0 5.5 4.0 3.0 2.5 1.8 1.5 1.0 5.0 3.0 Units mA IDD2 Idle mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% - 1.1 1.0 0.5 0.4 mA IDD3 Stop mode; VDD = 5.0 V 10% Stop mode; VDD = 3.0 V 10% - 0.1 0.1 A NOTES: 1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers, 2. output port drive currents and ADC. The supply current assumes a CPU clock of fx/4. 14-4 KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA Table 14-3. KS57C4104/C4204 System Clock Oscillator Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration Xin Xout Parameter Oscillation frequency (1) Test Condition VDD = 2.7 V to 5.5 V Min 0.4 Typ - Max 6.0 Units MHz C1 C2 VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V Stabilization time Crystal Oscillator Xin Xout (2) 0.4 0.4 - 0.4 - - - - 4.2 3.0 4 6.0 ms MHz VDD = 3.0 V VDD = 2.7 V to 5.5 V Oscillation frequency (1) C1 C2 VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V Stabilization time External Clock Xin Xout (2) 0.4 0.4 - 0.4 - - - - 4.2 3.0 10 6.0 ms MHz VDD = 3.0 V VDD = 2.7 V to 5.5 V XIN input frequency (1) VDD = 2.0 V to 5.5 V VDD = 1.8 V to 5.5 V XIN input high and low level width (tXH, tXL) RC Oscillator Xin R Xout 0.4 0.4 83.3 - - - - 4 4.2 3.0 1250 - ns MHz - VDD = 5 V R = 8.2 K Oscillation frequency limitation NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 14-5 ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 CPU CLOCK 1.5 MHz Main Oscillator Frequency (Divided by 4) 6 MHz 1.05 MHz 0.75 MHz 15.6 kHz 1 2 1.8 2.7 4.2 MHz 3 MHz 3 4 5 5.5 6 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 14-1. KS57C4104/C4204 Standard Operating Voltage Range Table 14-4. KS57C4104/C4204 A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time TCL0/1 Input Frequency TCL0/1 Input High, Low Width SCK Cycle Time Symbol tCY f TI tTIH, tTIL tKCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source Min 0.67 1.33 0 Typ - Max 64 Units s MHz MHz s ns - 1.5 0.75 0.48 1.8 800 670 3200 3800 - - - - 14-6 KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA Table 14-4. KS57C4104/C4204 A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter SCK High, Low Symbol tKH, tKL Conditions VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source Min 335 tKCY/2 - 50 1600 tKCY/2 - 150 100 150 150 500 400 400 600 500 - Typ - Max - Units ns Width SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source - - ns SI Hold Time to SCK High tKSI VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source - - ns Output Delay for SCK to SO tKSO (1) VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source - 300 250 1000 1000 ns Interrupt Input High, Low Width tINTH, tINTL tRSL INT0 INT1, INT2, INT4, KS0-KS3 (2) - - s 10 10 - - s RESET Input Low Input Width NOTES: 1. R(1K) and C (100pF) are the load resistance and load capacitance of the SO output line. 2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting. 14-7 ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 Table 14-5. KS57C4304 Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL One pin All output pins Output Current Low One pin peak value rms value All pins Operating Temperature Storage Temperature TA Tstg peak value rms value - - Duty . (note) (note) Conditions - All I/O ports - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 35 + 30 + 15 + 100 + 60 - 40 to + 85 - 65 to + 150 Units V V V mA mA C C NOTE: The values for Output Current Low (IOL) are calculated as Peak Value x 14-8 KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA Table 14-6. KS57C4304 D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.5 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage Output Low Voltage VOH Conditions All input pins except those specified below for VIH2-VIH3 Ports 0, 1, 3, 6 and RESET XIN, XOUT All input pins except those specified below for VIL2-VIL3 Ports 0, 1, 3, 6 and RESET XIN, XOUT VDD = 4.5 V to 5.5 V VDD - 1.0 IOH = - 1 mA Ports 0, 2-8 VDD = 3.5 V - IOL = 15 mA Ports 4 and 5 only IOL = 4 mA All output ports except ports 4 and 5 VI = VDD - All input pins except those specified below for ILIH2 VI = VDD XIN and XOUT only VI = 0 V All input pins except XIN and XOUT, RESET Min 0.7 VDD 0.8 VDD VDD - 0.1 - Typ - Max VDD VDD VDD Units V - 0.3 VDD 0.2 VDD 0.1 V - - V VOL 0.4 2 V 0.2 - 3 A Input High Leakage Current ILIH1 ILIH2 Input Low Leakage Current ILIL1 20 - - -3 A ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH ILOL RL1 RL2 VI = 0 V XIN and XOUT only VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 5 V except RESET VI = 0 V; VDD = 3 V except RESET VI = 0 V; VDD = 5 V; RESET VI = 0 V; VDD = 3 V; RESET - - 25 50 100 200 - - 50 100 250 500 - 20 3 -3 100 200 400 800 k A A k Pull-Up Resistor 14-9 ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 Table 14-6. KS57C4304 D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.5 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 Conditions Run mode; VDD = 5.0 V 10% Crystal oscillator; C1 = C2 = 22pF VDD = 3 V 10% 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz Min - Typ 3.1 2.4 1.5 1.2 Max 8.0 5.5 4.0 3.0 2.5 1.8 1.5 1.0 200 150 Units mA IDD2 Idle mode; VDD = 5.0 V 10% Crystal oscillator; C1 = C2 = 22pF VDD = 3 V 10% - 1.2 1.1 0.6 0.5 mA IDD3 Stop mode; VDD = 5.0 V 10% Stop mode; VDD = 3.0 V 10% - 120 100 A NOTES: 1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers, 2. output port drive currents and ADC. The supply current assumes a CPU clock of fx/4. Table 14-7. KS57C4304 Power-On Reset Circuit Characteristics (TA = - 40 C to + 85 C, VDD = 2.5 V to 5.5 V) Parameter Power-On Reset Voltage High Power-On Reset Voltage Low Power Supply Voltage Rise Time Power Supply Voltage Off Time Power-On Reset Circuit Cunsumption Current (2) Symbol VDDH VDDL tr toff IDDPR VDD = 5 V 10% VDD = 3 V 10% Conditions Min 2.5 0 10 0.5 120 100 200 150 2.0 Typ Max 5.5 2.2 (1) Units V V us s uA uA NOTES: 1. 217/fx (= 31.3 ms at fx = 4.19 MHz) 2. Current consumed when power-on reset circuit is provided internally. 14-10 KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA Table 14-8. KS57C4304 System Clock Oscillator Characteristics (TA = - 40 C to + 85 C, VDD = 2.5 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration Xin Xout Parameter Oscillation frequency (1) Test Condition VDD = 2.7 V to 5.5 V Min 0.4 Typ - Max 6.0 Units MHz C1 C2 VDD = 2.5 V to 5.5 V Stabilization time (2) Crystal Oscillator Xin Xout 0.4 - 0.4 - - - 4.2 4 6.0 ms MHz VDD = 3.0 V (1) Oscillation frequency VDD = 2.7 V to 5.5 V C1 C2 VDD = 2.5 V to 5.5 V Stabilization time External Clock Xin Xout (2) 0.4 - 0.4 - - - 4.2 10 6.0 ms MHz VDD = 3.0 V VDD = 2.7 V to 5.5 V XIN input frequency (1) VDD = 2.5 V to 5.5 V XIN input high and low level width (tXH, tXL) RC Oscillator Xin R Xout 0.4 83.3 - - - 4 4.2 1250 - ns MHz - VDD = 5 V R = 8.2 K Oscillation frequency limitation NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 14-11 ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 CPU CLOCK 1.5 MHz Main Oscillator Frequency (Divided by 4) 6 MHz 1.05 MHz 0.75 MHz 15.6 kHz 1 2 1.8 2.7 2.5 4.2 MHz 3 MHz 3 4 5 5.5 6 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 14-2. KS57C4304 Standard Operating Voltage Range 14-12 KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA Table 14-9. KS57C4304 A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.5 V to 5.5 V) Parameter Instruction Cycle Time TCL0/1 Input Frequency TCL0/1 Input High, Low Width SCK Cycle Time Symbol tCY f TI0 tTIH0, tTIL0 tKCY Conditions VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.7 V to 5.5 V External SCK source Internal SCK source INT0 INT1, INT2, INT4, KS0-KS3 Input Min 0.67 0 0.48 800 670 325 tKCY/2 - 50 100 150 400 400 - Typ - - - - Max 64 1.5 - - Units s MHz s ns SCK High, Low tKH, tKL - - ns Width SI Setup Time to SCK High tSIK - - ns SI Hold Time to SCK High tKSI - - ns Output Delay for SCK to SO tKSO - 300 250 ns Interrupt Input High, Low Width RESET Input tINTH, tINTL tRSL (NOTE) - - s 10 10 - - s Low Width NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting. 14-13 ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 Table 14-10. A/D Converter Electrical Characteristics (TA = - 10 C to + 70 C, VDD = 3.5 V to 5.5 V, VSS = AVSS = 0 V) Parameter Resolution Absolute accuracy (1) Conversion time (2) Analog input voltage Analog input impedance Symbol - - tCON VIAN RAN Condition - 2.5 V < AVREF < VDD - - - Min 8 - - AVSS - Typ 8 - 96/fx - 1000 (3) Max 8 1.5 - AVREF - Units bit LSB s V M NOTES: 1. Absolute accuracy does not include the quantization error ( 1/2 LSB). 2. Conversion time is the time required from the moment a conversion operation starts until it ends (EOC = 0). 3. 'fx' is the abbreviation for system clock. Table 14-11. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF Table 14-12. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillation stabilization time (1) Symbol VDDDR IDDDR tSREL tWAIT RESET Conditions - - - When released by When released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217/fx (2) Max 5.5 10 - - - Unit V A ms ms ms NOTES: 1. During oscillation stabilization time, CPU operation must be stopped to avoid unstable operation upon oscillation start. 2. The basic timer causes a delay of 217/fx after a reset. 14-14 KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA TIMING WAVEFORMS INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE VDD IDLE MODE OPERATING MODE ~ ~ V DDDR RESET EXECUTION OF STOP INSTRUCTION tWAIT t SREL Figure 14-3. Stop Mode Release Timing When Initiated By RESET IDLE MODE STOP MODE DATA RETENTION VDD NORMAL OPERATING MODE ~ ~ VDDDR EXECUTION OF STOP INSTRUCTION tSREL POWER-DOWN MODE TERMINATING (INTERRUPT REQUEST) t WAIT Figure 14-4. Stop Mode Release Timing When Initiated By Interrupt Request 14-15 ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 0.8 V DD 0.2 V DD MEASUREMENT POINTS 0.8 VDD 0.2 VDD Figure 14-5. A.C. Timing Measurement Points (Except for XIN) 1/f x tXL t XH XIN VDD - 0.5 V 0.4 V Figure 14-6. Clock Timing Measurement at XIN 1 / f TI0 t TIL0 t TIH0 TCL0 0.8 V DD 0.2 V DD Figure 14-7. TCL0/1 Timing 14-16 KS57C4104/P4104/C4204/P4204/C4304/P4304 ELECTRICAL DATA tRSL RESET 0.2 V DD Figure 14-8. Input Timing for RESET Signal tINTL t INTH INT0, 1, 2, 4 KS0 to KS3 0.8 VDD 0.2 V DD Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts 14-17 ELECTRICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 toff tr VDD VDDH VDDL Figure 14-10. KS57C4304 Power-On RESET Timing t KCY t KL SCK t KH 0.8 V DD 0.2 V DD t SIK t KSI 0.8 VDD 0.2 V DD SI INPUT DATA t KSO SO OUTPUT DATA Figure 14-11. Serial Data Transfer Timing 14-18 KS57C4104/P4104/C4204/P4204/C4304/P4304 PRODUCT OVERVIEW Table 1-1. Comparision Table Feature Core ROM RAM I/O POR (1) SIO Timer0 Timer1(PWM) Watchdog timer ADC AVSS Interrupt KS57C4104 SAM47 4 K bytes 256 nibbles 35 (4 input only) None 8-bit SIO x 1 8-bit timer/counter 8-bit timer/counter (8-bit PWM x 1) Watch-dog 4 selectable interval 8-bit x 6 None (2) External x 3 Internal x 5 Quasi x 2 (KS0-KS3) Stop/Idle Crystal, Ceramic, RC 0.4-6 MHz 1.8-5.5 V OTP 42SDIP/44QFP Same Same 21 (3 input only) None Same Same Same Same 8-bit x 4 Same External x 2 Internal x 5 Quasi x 1 ( - ) Same Same Same 1.8-5.5 V Same 30SDIP/28SOP KS57C4204 SAM47 Same Same 35 (4 input only) Built in/ Typ: 2.0 V Same Same Same Same 8-bit x 6 Same External x 3 Internal x 5 Quasi x 2 (KS0-KS3) Same Same Same 2.5-5.5 V Same 42SDIP/44QFP KS57C4304 SAM47 Power down Oscillator Operating frequency Operating voltage OTP/MTP Package NOTES 1. POR (power on reset)/Typ 2.0 V low voltage detector. 2. Internal A/D converter ground (bonded to VSS internally) 1-3 PRODUCT OVERVIEW KS57C4104/P4104/C4204/P4204/C4304/P4304 BLOCK DIAGRAM INT0, INT1, INT2,INT4 8-BIT TIMER/ COUNTER 0 RESET BASIC TIMER XIN XOUT WATCH TIMER 8-BIT TIMER/ COUNTER 1 INTERRUPT CONTROL BLOCK CLOCK INSTRUCTION REGISTER 2 I/O PORT 0 P0.0/ SCK P0.1/SO P0.2/SI P0.3/BUZ P4.0-4.3 P5.0-5.3 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 P7.0-7.3 P8.0/TCL0 P8.1/TCLO0 P8.2 I/O PORT 4 I/O PORT 5 INTERNAL INTERRUPTS INSTRUCTION DECODER ARITHMETIC AND LOGIC UNIT PROGRAM COUNTER SERIAL I/O P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0-P2.3/ AD0-AD3 PROGRAM STATUS WORD INPUT PORT 1 I/O PORT 2 STACK POINTER A/D CONVERTER I/O PORT 6 I/O PORT 7 AVREF P3.0/AD4 P3.1/AD5 P3.2/CLO/TCL1 P3.3/PWM / TCLO1 I/O PORT 8 256 x 4-BIT DATA MEMORY 4 K BYTE PROGRAM MEMORY I/O PORT 3 Figure 1-1. KS57C4104/C4204/C4304 Simplified Block Diagram 1-4 KS57C4104/P4104/C4204/P4204/C4304/P4304 PRODUCT OVERVIEW PIN ASSIGNMENTS P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P3.0/AD4 P3.1/AD5 AVREF P3.2/CLO/TCL1 P3.3/PWM/TCLO1 P4.0 VDD VSS XOUT XIN TEST P4.1 P4.2 RESET P4.3 P5.0 P5.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P8.2 P8.1/TCLO0 P8.0/TCL0 P7.3 P7.2 P7.1 P7.0 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ P0.2/SI P0.1/SO P0.0/SCK P5.3 P5.2 Figure 1-2. KS57C4104 Pin Assignment (42-SDIP) KS57C4104 42 SDIP 1-5 PRODUCT OVERVIEW KS57C4104/P4104/C4204/P4204/C4304/P4304 AVREF P3.2/CLO/TCL1 P3.3/PWM/TCLO1 P4.0 VDD VSS XOUT XIN TEST P4.1 P4.2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC P3.1/AD5 P3.0/AD4 P2.3/AD3 P2.2/AD2 P2.1/AD1 P2.0/AD0 P8.2 P8.1/TCLO0 P8.0/TCL0 P7.3 KS57C4104 44 QFP P7.2 P7.1 P7.0 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 Figure 1-3. KS57C4104 Pin Assignment (44-QFP) 1-6 P4.3 P5.0 P5.1 P5.2 P5.3 P0.0/ SCK P0.1/SO P0.2/SI P0.3/BUZ NC RESET 12 13 14 15 16 17 18 19 20 21 22 KS57C4104/P4104/C4204/P4204/C4304/P4304 PRODUCT OVERVIEW VSS XOUT XIN TEST P4.1 P4.2 RESET NC P4.3 P5.0 P5.1 P5.2 P5.3 P0.0/SCK P0.1/SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P4.0 P3.3/PWM/TCLO1 P3.2/CLO/TCL1 AVREF NC P2.3/AD3 P2.2/AD2 P2.1/AD1 P2.0/AD0 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ P0.2/SI Figure 1-4. KS57C4204 Pin Assignment (30-SDIP) KS57C4204 30 SDIP 1-7 PRODUCT OVERVIEW KS57C4104/P4104/C4204/P4204/C4304/P4304 VSS XOUT XIN TEST P4.1 P4.2 RESET P4.3 P5.0 P5.1 P5.2 P5.3 P0.0/ SCK P0.1/SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P4.0 P3.3/PWM/TCLO1 P3.2/CLO/TCL1 AVREF P2.3/AD3 P2.2/AD2 P2.1/AD1 P2.0/AD0 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ P0.2/SI Figure 1-5. KS57C4204 Pin Assignment (28-SOP) KS57C4204 28 SOP 1-8 KS57C4104/P4104/C4204/P4204/C4304/P4304 PRODUCT OVERVIEW P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P3.0/AD4 P3.1/AD5 AVREF P3.2/CLO/TCL1 P3.3/PWM/TCLO1 P4.0 VDD VSS XOUT XIN TEST P4.1 P4.2 RESET P4.3 P5.0 P5.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P8.2 P8.1/TCLO0 P8.0/TCL0 P7.3 P7.2 P7.1 P7.0 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ P0.2/SI P0.1/SO P0.0/ SCK P5.3 P5.2 Figure 1-6. KS57C4304 Pin Assignment (42-SDIP) KS57C4304 42 SDIP 1-9 PRODUCT OVERVIEW KS57C4104/P4104/C4204/P4204/C4304/P4304 AVREF P3.2/CLO/TCL1 P3.3/PWM/TCLO1 P4.0 VDD VSS XOUT XIN TEST P4.1 P4.2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC P3.1/AD5 P3.0/AD4 P2.3/AD3 P2.2/AD2 P2.1/AD1 P2.0/AD0 P8.2 P8.1/TCLO0 P8.0/TCL0 P7.3 KS57C4304 44 QFP P7.2 P7.1 P7.0 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 Figure 1-7. KS57C4304 Pin Assignment (44-QFP) 1-10 P4.3 P5.0 P5.1 P5.2 P5.3 P0.0/ SCK P0.1/SO P0.2/SI P0.3/BUZ NC RESET 12 13 14 15 16 17 18 19 20 21 22 KS57C4104/P4104/C4204/P4204/C4304/P4304 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-2. KS57C4104/C4304 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-bit input port. 1-bit and 4-bit read and test is possible. 3-bit pull-up resistors are individually assignable by software to pins P1.0, P1.1, and P1.2. 4-bit I/O port. N-channel open-drain output. 1-bit or 4-bit write and test is possible. Individual pins are software configurable as AD input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as Port 0 (P0.0-P0.3) Number 24 (18) 25 (19) 26 (20) 27 (21) Share Pin SCK SO SI BUZ P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 I 28 (23) 29 (24) 30 (25) 31 (26) 1 (38) 2 (39) 3 (40) 4 (41) INT0 INT1 INT2 INT4 AD0 AD1 AD2 AD3 I/O P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 P5.0-P5.3 I/O 5 (42) 6 (43) 8 (2) 9 (3) 10 (4) 16 (10) 17 (11) 19 (13) 20-23 (14-17) AD4 AD5 CLO/TCL1 PWM/TCLO1 - I/O 4-bit I/O ports. Ports 4 and 5 can be configured individually as nchannel open-drain or as CMOS push-pull output by software. 1-bit and 4-bit read/write and test is possible. Ports 4 and 5 can be paired to enable 8-bit data transfer. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as Port 0 except port 8 is a 3-bit I/O port P6.0-P6.3 P7.0-P7.3 P8.0 P8.1 P8.2 I/O 32-35 (27-30) 36-39 (31-34) 40 (35) 41 (36) 42 (37) KS0-KS3 - TCL0 TCLO0 - 1-11 PRODUCT OVERVIEW KS57C4104/P4104/C4204/P4204/C4304/P4304 Table 1-2. KS57C4104/C4304 Pin Descriptions (Continued) Pin Name SCK Pin Type I/O I/O I/O I/O I Serial data output Serial data input Description Serial I/O interface clock signal Number 24 (18) 25 (19) 26 (20) 27 (21) 28-29 (23-24) 30 (25) 31 (26) 1-4 (38-41) 5-6 (42-43) 40 (35) 41 (36) 8 (2) 8 (2) 9 (3) 9 (3) 32-35 (27-30) 11 (5) 12 (6) 18 (12) 14, 13 (8, 7) 7 (1) 15 (9) (22, 44) Share Pin P0.0 P0.1 P0.2 P0.3 P1.0, P1.1 SO SI BUZ INT0, INT1 2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the watch timer clock frequency of 32.768 kHz External interrupts. The triggering edge for INT0 and INT1 is selectable. Only INT0 is synchronized with the system clock. Quasi-interrupt input with rising edge detection External interrupts with detection of rising and falling edges A/D converter analog inputs INT2 INT4 AD0-AD3 AD4-AD5 TCL0 TCLO0 CLO TCL1 PWM TCLO1 KS0-KS3 VDD VSS RESET I I I/O P1.2 P1.3 P2.0-P2.3 P3.0-P3.1 P8.0 P8.1 P3.2 P3.2 P3.3 P3.3 P6.0-P6.3 - - - - - - - I/O I/O I/O I/O I/O I/O I/O - - I - - I - External clock input for timer/counter0 Timer/counter clock output Clock output External clock input for timer/counter1 PWM output Timer/counter clock output1 Quasi-interrupt input with falling edge detection Main power supply Ground Reset signal Crystal, ceramic, or RC oscillator signal for system clock. A/D converter analog reference voltage Test signal input (must be connected to VSS) No connection (no bonding pin) XIN, Xout AVREF TEST NC NOTE: Parentheses indicate 44-QFP pin number. 1-12 KS57C4104/P4104/C4204/P4204/C4304/P4304 PRODUCT OVERVIEW Table 1-3. KS57C4204 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-bit input port. 1-bit and 4-bit read and test is possible. 3-bit pull-up resistors are individually assignable by software to pins P1.0, P1.1, and P1.2. 4-bit I/O port. N-channel open-drain output. 1-bit or 4-bit write and test is possible. Individual pins are software configurable as AD input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as Port 0 (P0.0-P0.3) 4-bit I/O ports. Ports 4 and 5 can be configured individually as nchannel open-drain or as CMOS push-pull output by software. 1-bit and 4-bit read/write and test is possible. Ports 4 and 5 can be paired to enable 8-bit data transfer. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Number 14 (13) 15 (14) 16 (15) 17 (16) Share Pin SCK SO SI BUZ P1.0 P1.1 P1.2 P2.0 P2.1 P2.2 P2.3 I 18 (17) 19 (18) 20 (19) 21 (20) 22 (21) 23 (22) 24 (23) INT0 INT1 INT2 AD0 AD1 AD2 AD3 I/O P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 P5.0-P5.3 I/O I/O 27 (25) 28 (26) 29 (27) 5 (5) 6 (6) 9 (8) 10-13 (9-12) CLO/TCL1 PWM/TCLO1 - 1-13 PRODUCT OVERVIEW KS57C4104/P4104/C4204/P4204/C4304/P4304 Table 1-3. KS57C4204 Pin Descriptions (Continued) Pin Name SCK Pin Type I/O I/O I/O I/O I Serial data output Serial data input Description Serial I/O interface clock signal Number 14 (13) 15 (14) 16 (15) 17 (16) 18, 19 (17, 18) 20 (19) 21-24 (20-23) 27 (25) 27 (25) 28 (26) 28 (26) 30 (28) 1 (1) 7 (7) 3, 2 (3, 2) 26 (24) 4 (4) 8, 25 Share Pin P0.0 P0.1 P0.2 P0.3 P1.0, P1.1 SO SI BUZ INT0, INT1 2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the watch timer clock frequency of 32.768 kHz External interrupts. The triggering edge for INT0 and INT1 is selectable. Only INT0 is synchronized with the system clock. Quasi-interrupt input with rising edge detection A/D converter analog inputs Clock output External clock input for timer/counter1 PWM output Timer/counter clock output1 Main power supply Ground Reset signal Crystal, ceramic, or RC oscillator signal for system clock. Internal A/D converter analog reference voltage Test signal input (must be connected to VSS) No connection (no bonding pin) INT2 AD0-AD3 CLO TCL1 PWM TCLO1 VDD VSS RESET I I/O I/O I/O I/O I/O - - I - - I - P1.2 P2.0-P2.3 P3.2 P3.2 P3.3 P3.3 - - - - - - - XIN, XOUT AVREF TEST NC NOTE: Parentheses indicate 28-SOP pin number. 1-14 KS57C4104/P4104/C4204/P4204/C4304/P4304 PRODUCT OVERVIEW Table 1-4. Overview of KS57C4104/C4204/C4304 Pin Data Pin Names P0.0-P0.3 P1.0 P1.1 P1.2 P1.3 P2.0-P2.3 P3.0 P3.1 P3.2 P3.3 P4.0-P4.3 P5.0-P5.3 P6.0 P6.1 P6.2 P6.3 P7.0-P7.3 P8.0 P8.1 P8.2 VDD, VSS XIN, XOUT RESET Share Pins SCK, SO, SI, BUZ (note) I/O Type I/O I Reset Value Input Input Circuit Type Type D Type A-1 INT0 INT1 (note) INT2 (note) INT4 AD0-AD3 AD4 AD5 CLO/TCL1 TCLO1/PWM - KS0 (note) KS1 (note) KS2 (note) KS3 (note) - TCL0 TCLO0 - - - - - - - (note) I I/O I/O Input AD input Input Type A Type F-3 Type F Type F Type D Type D Type E Type D I/O I/O Input Input I/O I/O Input Input Type D Type D - - I - I - - - - - - - - - Type B-2 (note) - - AVREF TEST NC NOTE: A noise filter circuit is built-in. - 1-15 PRODUCT OVERVIEW KS57C4104/P4104/C4204/P4204 MICROCONTROLLER (Preliminary Spec) PIN CIRCUIT DIAGRAMS VDD VDD P-CHANNEL IN N-CHANNEL RESET 1M 7pF Figure 1-8. Pin Circuit Type A Figure 1-10. Pin Circuit Type B-2 VDD VDD PULL-UP RESISTOR ENABLE P-CHANNEL DATA OUT N-CHANNEL IN CIRCUIT TYPE A OUTPUT DISABLE Figure 1-9. Pin Circuit Type A-1 Figure 1-11. Pin Circuit Type C 1-16 KS57C4104/P4104/C4204/P4204/C4304/P4304 PRODUCT OVERVIEW VDD VDD PULL-UP RESISTOR ENABLE PULL-UP RESISTOR ENABLE DATA OUTPUT DISABLE CIRCUIT TYPE C I/O DATA OUTPUT DISABLE DATA CIRCUIT TYPE C IN/OUT CIRCUIT TYPE A TO ADC ADC INPUT SELECT Figure 1-12. Pin Circuit Type D Figure 1-14. Pin Circuit Type F VDD VDD PNE VDD PULL-UP RESISTOR ENABLE DATA OUTPUT DISABLE IN/OUT PULL-UP RESISTOR ENABLE IN/OUT DATA OUTPUT DISABLE DATA TO ADC INPUT ADC INPUT SELECT Figure 1-13. Pin Circuit Type E Figure 1-15. Pin Circuit Type F-3 1-17 PRODUCT OVERVIEW KS57C4104/P4104/C4204/P4204 MICROCONTROLLER (Preliminary Spec) NOTES 1-18 KS57C4104/P4104/C4204/P4204/C4304/P4304 (Preliminary Spec) MECHANICAL DATA 15 -- Pad diagram #42 14.00 0.2 MECHANICAL DATA This section contains the following information about the device package: -- Package dimensions in millimeters #22 0-15 15.24 42-SDIP-600 #1 #21 39.10 0.2 3.50 0.2 0.50 0.1 (1.77) 1.00 0.1 1.778 NOTE: Dimensions are in millimeters. Figure 15-1. 42-SDIP-600 Package Dimensions 3.30 0.3 0.51MIN 5.08MAX 39.50 MAX 0.25 +0.1 - 0.05 15-1 MECHANICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 (Preliminary Spec) 13.20 0.3 10.00 0.2 0-8 0.15 - 0.05 +0.10 13.20 0.3 10.00 0.2 44-QFP-1010 0.10 MAX #44 0.05 MIN 2.05 0.10 #1 0.80 0.35 +0.10 - 0.05 (1.00) 2.30 MAX NOTE: Dimensions are in millimeters. Figure 15-2. 44-QFP-1010 Package Dimensions 15-2 0.800.20 KS57C4104/P4104/C4204/P4204/C4304/P4304 (Preliminary Spec) MECHANICAL DATA #30 #16 0-15 8.94 0.2 10.16 30-SDIP-400 #1 27.88 MAX 27.48 0.2 #15 3.81 0.2 5.08MAX (1.30) 1.12 0.1 1.778 NOTE: Dimensions are in millimeters. Figure 15-3. 30-SDIP-400 Package Dimensions 3.30 0.3 0.51MIN 0.56 0.1 0.25 +0.1 - 0.05 15-3 MECHANICAL DATA KS57C4104/P4104/C4204/P4204/C4304/P4304 (Preliminary Spec) 0-8 #28 #15 10.45 0.3 7.70 0.2 28-SOP-375 #1 #14 0.15 - 0.05 +0.10 2.15 0.2 17.62 0.2 (0.56) 0.41 0.1 1.27 NOTE: Dimensions are in millimeters. Figure 15-4. 28-SOP-375 Package Dimensions 15-4 0.05MIN 2.55MAX 18.02 MAX 0.10 MAX 0.60 0.20 9.53 KS57C4104/P4104/C4204/P4204/C4304/P4304 KS57P4104/P4204/P4304 OTP 16 OVERVIEW KS57P4104/P4204/P4304 OTP The KS57P4104/P4204/P4304 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS57C4104/C4204/C4304 microcontroller. It has an on-chip OTP ROM instead of masked ROM. Samsungs own serial protocol used for OTP program pin information regarding OTP program can be referred OTP pin description. The KS57P4104/P4204/P4304 is fully compatible with the KS57C4104/C4204/C4304, in function, in D.C. electrical characteristics and in pin configuration. Because of its simple programming requirements, the KS57P4104/P4204/P4304 is ideal for use as an evaluation chip for the KS57C4104/C4204/C4304. 16-1 KS57P4104/P4204/P4304 OTP KS57C4104/P4104/C4204/P4204/C4304/P4304 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P3.0/AD4 P3.1/AD5 AVREF P3.2/CLO/TCL1 SDAT/P3.3/PWM/TCLO1 SCLK /P4.0 VDD/VDD V SS/VSS XOUT XIN VPP/TEST P4.1 P4.2 RESET /RESET P4.3 P5.0 P5.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P8.2 P8.1/TCLO0 P8.0/TCL0 P7.3 P7.2 P7.1 P7.0 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ P0.2/SI P0.1/SO P0.0/SCKB P5.3 P5.2 NOTE: The bolds indicate an OTP pin name. Figure 16-1. KS57P4104 Pin Assignments (42-SDIP) KS57P4104 42 SDIP 16-2 KS57C4104/P4104/C4204/P4204/C4304/P4304 KS57P4104/P4204/P4304 OTP 44 43 42 41 40 39 38 37 36 35 34 AVREF P3.2/CLO/TCL1 SDAT/P3.3/PWM/TCLO1 SCLK /P4.0 VDD/VDD VSS/VSS XOUT XIN VPP/TEST P4.1 P4.2 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 NC P3.1/AD5 P3.0/AD4 P2.3/AD3 P2.2/AD2 P2.1/AD1 P2.0/AD0 P8.2 P8.1/TCLO0 P8.0/TCL0 P7.3 KS57P4104 44 QFP P7.2 P7.1 P7.0 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 NOTE: The bolds indicate an OTP pin name. Figure 16-2. KS57P4104 Pin Assignments (44-QFP) RESET P4.3 P5.0 P5.1 P5.2 P5.3 P0.0/SCK P0.1/SO P0.2/SI P0.3/BUZ NC /RESET 12 13 14 15 16 17 18 19 20 21 22 16-3 KS57P4104/P4204/P4304 OTP KS57C4104/P4104/C4204/P4204/C4304/P4304 VSS/VSS XOUT XIN VPP/TEST P4.1 P4.2 RESET /RESET NC P4.3 P5.0 P5.1 P5.2 P5.3 P0.0/ SCK P0.1/SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD/ VDD P4.0/ SCLK P3.3/PWM/TCLO1/ SDAT P3.2/CLO/TCL1 AVREF NC P2.3/AD3 P2.2/AD2 P2.1/AD1 P2.0/AD0 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ P0.2/SI NOTE: The bolds indicate an OTP pin name. Figure 16-3. KS57P4204 Pin Assignments (30-SDIP) KS57P4204 30 SDIP 16-4 KS57C4104/P4104/C4204/P4204/C4304/P4304 KS57P4104/P4204/P4304 OTP VSS/V SS XOUT XIN VPP/TEST P4.1 P4.2 RESET /RESET P4.3 P5.0 P5.1 P5.2 P5.3 P0.0/SCK P0.1/SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD/VDD P4.0/SCLK P3.3/PWM/TCLO1/SDAT P3.2/CLO/TCL1 AVREF P2.3/AD3 P2.2/AD2 P2.1/AD1 P2.0/AD0 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ P0.2/SI NOTE: The bolds indicate an OTP pin name. Figure 16-4. KS57P4204 Pin Assignments (28-SOP) KS57P4204 28 SOP 16-5 KS57P4104/P4204/P4304 OTP KS57C4104/P4104/C4204/P4204/C4304/P4304 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P3.0/AD4 P3.1/AD5 AVREF P3.2/CLO/TCL1 SDAT/P3.3/PWM/TCLO1 SCLK /P4.0 VDD/VDD V SS/VSS XOUT XIN VPP/TEST P4.1 P4.2 RESET /RESET P4.3 P5.0 P5.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P8.2 P8.1/TCLO0 P8.0/TCL0 P7.3 P7.2 P7.1 P7.0 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ P0.2/SI P0.1/SO P0.0/SCKB P5.3 P5.2 NOTE: The bolds indicate an OTP pin name. Figure 16-5. KS57P4304 Pin Assignments (42-SDIP) KS57P4304 42 SDIP 16-6 KS57C4104/P4104/C4204/P4204/C4304/P4304 KS57P4104/P4204/P4304 OTP AVREF P3.2/CLO/TCL1 SDAT/P3.3/PWM/TCLO1 SCLK /P4.0 VDD/VDD VSS/VSS XOUT XIN VPP/TEST P4.1 P4.2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC P3.1/AD5 P3.0/AD4 P2.3/AD3 P2.2/AD2 P2.1/AD1 P2.0/AD0 P8.2 P8.1/TCLO0 P8.0/TCL0 P7.3 KS57P4304 44 QFP P7.2 P7.1 P7.0 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P4.3 P5.0 P5.1 P5.2 P5.3 NOTE: The bolds indicate an OTP pin name. Figure 16-6. KS57P4304 Pin Assignments (44-QFP) RESET P0.0/ SCK P0.1/SO P0.2/SI P0.3/BUZ NC /RESET 12 13 14 15 16 17 18 19 20 21 22 16-7 KS57P4104/P4204/P4304 OTP KS57C4104/P4104/C4204/P4204/C4304/P4304 Table 16-1. Pin Descriptions of KS57P4104/P4304 Used to Read/Write the EPROM Main Chip Pin Name P3.3 Pin Name SDAT Pin No. 9 (3) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. P4.0 TEST SCLK VPP (TEST) 10 (4) 15 (9) I/O I RESET RESET 18 (12) 11/12 (5/6) I I VDD/VSS VDD/VSS NOTE: Parentheses indicate 44-QFP pin number. Table 16-2. Pin Descriptions of KS57P4204 Used to Read/Write the EPROM Main Chip Pin Name P3.3 Pin Name SDAT Pin No. 28 (26) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. P4.0 TEST SCLK VPP (TEST) 29 (27) 4 (4) I/O I RESET RESET 7 (7) 30/1 (28/1) I I VDD/VSS VDD/VSS NOTE: Parentheses indicate 28-SOP pin number. 16-8 KS57C4104/P4104/C4204/P4204/C4304/P4304 KS57P4104/P4204/P4304 OTP Table 16-3. Comparison of KS57P4104/P4204 and KS57C4104/C4204 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability KS57P4104/P4204 4 K byte EPROM 1.8 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 42 SDIP, 44 QFP, 30 SDIP, 28 SOP User Program 1 time 42 SDIP, 44 QFP, 30 SDIP, 28 SOP Programmed at the factory KS57C4104/C4204 4 K byte mask ROM 1.8 V to 5.5 V Table 16-4. Comparison of KS57P4304 and KS57C4304 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability KS57P4304 4 K byte EPROM 2.5 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 42 SDIP, 44 QFP User Program 1 time 42 SDIP, 44 QFP Programmed at the factory KS57C4304 4 K byte mask ROM 2.5 V to 5.5 V OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the KS57P4104/P4204/P4304, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-4 below. Table 16-5. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode NOTE: "0" means Low level; "1" means High level. 16-9 KS57P4104/P4204/P4304 OTP KS57C4104/P4104/C4204/P4204/C4304/P4304 START Address= First Location VDD =5V, V PP=12.5V x=0 Program One 1ms Pulse Increment X YES x = 10 NO FAIL Verify Byte Verify 1 Byte FAIL Last Address NO Increment Address VDD = VPP= 5 V FAIL Compare All Byte PASS Device Failed Device Passed Figure 16-7. OTP Programming Algorithm 16-10 KS57C4104/P4104/C4204/P4204/C4304/P4304 KS57P4104/P4204/P4304 OTP Table 16-6. KS57P4104/P4204 D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 Conditions Run mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz Min - Typ 3.0 2.3 1.4 1.1 Max 8.0 5.5 4.0 3.0 2.5 1.8 1.5 1.0 5.0 3.0 Units mA IDD2 Idle mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% - 1.1 1.0 0.5 0.4 mA IDD3 Stop mode; VDD = 5.0 V 10% Stop mode; VDD = 3.0 V 10% - 0.1 0.1 A NOTES: 1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers, 2. output port drive currents and ADC. The supply current assumes a CPU clock of fx/4. CPU CLOCK 1.5 MHz Main Oscillator Frequency (Divided by 4) 6 MHz 1.05 MHz 0.75 MHz 15.6 kHz 1 2 1.8 2.7 4.2 MHz 3 MHz 3 4 5 5.5 6 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 16-8. KS57P4104/P4204 Standard Operating Voltage Range 16-11 KS57P4104/P4204/P4304 OTP KS57C4104/P4104/C4204/P4204/C4304/P4304 Table 16-7. KS57P4304 D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.5 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 Conditions Run mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz Min - Typ 3.1 2.4 1.5 1.2 Max 8.0 5.5 4.0 3.0 2.5 1.8 1.5 1.0 200 150 Units mA IDD2 Idle mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% - 1.2 1.1 0.6 0.5 mA IDD3 Stop mode; VDD = 5.0 V 10% Stop mode; VDD = 3.0 V 10% - 120 100 A NOTES: 1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers, 2. output port drive currents and ADC. The supply current assumes a CPU clock of fx/4. CPU CLOCK 1.5 MHz Main Oscillator Frequency (Divided by 4) 6 MHz 1.05 MHz 4.2 MHz 15.6 kHz 1 2 2.5 3 4 5 5.5 6 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 16-9. KS57P4304 Standard Operating Voltage Range 16-12 |
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