View M66242FP_149104.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
M66242P/FP M66242P/FP
4-CH 12-BIT PWM GENERATOR 4-CH 12-BIT PWM GENERATOR
DESCRIPTION M66242 Integrated Circuit has four 12-bit PWM (pulse width modulation) circuits which are built by using the CMOS (complementary metal oxide semiconductor) process. This IC controls PWM waveform by adjusting the "H" width according to serial data sent from MCU (micro controller unit) or other device. Each channel can be independently controlled. High-resolution digital-analog converter can be formed easily by connecting a low-pass filter circuit to the output pins of this circuit. FEATURES * Built-in four 12-bit high-resolution pulse width modulation circuits * Easy digital-analog conversion - Quick output waveform smoothing Control by 1.22mV possible per step (VCC =5V) * Serial data input * "H" level width setting type * 4 independently controlled channels * All 4 channels reset by reset input (R) High-impedance status after reset * All 4 channels controlled by output control input (OC) * Settings take effect after ongoing cycle is completed * Input: TTL level * Output: CMOS 3-state output Output current IO = 4mA * VCC =5V 10% BLOCK DIAGRAM (EACH CHANNEL)
PIN CONFIGURATION (TOP VIEW)
CHIP SELECT CS R RESET WRITE CONTROL WR SERIAL DATA INPUT SIN WRITE CLOCK SCLK OUTPUT CONTROL OC GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC PWM1 PWM2 OUTPUT PWM3 PWM4 XOUT CLOCK OUTPUT XIN CLOCK INPUT
Outline 14P4 14P2N-A
APPLICATION * Analog signal control in televisions and audio systems * Control of lamps, heaters and motors * For software servo in home appliances and industrial machinery
M66242P/FP
14 VCC Upper byte register SIN 4 SCLK 5 Input register
8-BIT PWM circuit PWM register 12-bit PWM circuit 4-bit-rate multiplier 13 PWM1
CS 1 WR 3 R2 OC 6 Control circuit
Lower byte register
12 PWM2 11 PWM3 10 PWM4
1/2 divider To other channels
Oscillation circuit
8 XIN 9 XOUT 7 GND
1
MITSUBISHI DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
FUNCTION The PWM output waveform of each channel is controlled by taking in PWM data from MCU or other device via serial data input SIN. Twelve-bit PWM data is input being divided between upper 8 bits (upper byte) and lower 4 bits. The lower 4-bit data is combined with command data such as channel designation and input as 8-bit data (lower byte). The lower byte should be written first, and then the upper byte. Even if only the upper byte is to be changed, rewrite from the lower byte. The PWM waveform changes according to the new setting from the next cycle. One cycle of PWM waveform (4096 divisions; 12-bit resolution) are divided into 16 (24) subsections t. Each subsection consists of 256 (28; 8-bit resolution) minimum bits (=2/ fXIN**). One subsection t consists of a 8-bit PWM waveform (basic waveform). The "H" width of this waveform is determined according to the upper 8 bits of PWM data. One cycle has 16
subsections t, each of which has this basic waveform. Among them, those which are designated by the 4-bit-rate multiplier are conditioned to have a "H" width that is longer by . The lower 4 bits of PWM data are used to specify those subsections (tm). The waveform of other subsections remains unchanged. A PWM waveform (12-bit resolution) is a combination of two types of waveforms which are different in "H" width, as described above. When output control input OC is "H", the output of every channel turns high-impedance from the next cycle. When reset input R is "L", the output of every channel turns high-impedance as soon as the ongoing cycle is completed, and PWM data of all channels is reset. If R input is changed from "L" to "H", the next cycle starts, however, the output of the channels remains high-impedance. To enable output, rewrite input data for each channel. **)fXIN: Clock XIN repeat frequency
PIN DESCRIPTIONS
Pin R CS WR SIN SCLK OC PWM1~PWM4 XIN XOUT Name Reset input Chip select input Write control input Serial data input Write clock input Output control input PWM outputs 1 thru 4 Clock input Clock output Input/Output Input Input Input Input Input Input Output Input Output Functions "L": All 4 channels put in high impedance state. "L": Communication with MCU becomes possible. WR, SIN and SCLK put in enable state. "L": Serial data written. "L"-to-"H" edge: Written data stored in upper or lower byte. Inputs 8-bit serial data from MCU synchronously with clock pulses. Inputs sync clock pulses for 8-bit serial data writing. "H": All 4 channels put in high-impedance state. Outputs PWM waveform. (CMOS 3-state output) Inputs/outputs signals generated by clock signal generation circuit. Oscillation frequency is determined by connecting ceramic or quartz resonator between XIN and XOUT. The frequency of internal clock (PWM timing clock) signals is the 1/2 divider of the frequency input from clock input XIN. When external clock signals are used, connect clock generator to XIN pin and leave XOUT open.
2
MITSUBISHI DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
(1) Upper byte resister
b7
b6
b5
b4
b3
b2
b1
b0
(2) Lower byte resister
PWM output "H" width setting bits (Upper 8 bits: b11 thru b4)
b7
b6
b5
b4
b3
b2
b1
b0
Write data designation bit 0: Lower byte only 1: Both lower and upper bytes PWM output select bit 00: PWM 1 01: PWM 2 10: PWM 3 11: PWM 4 Output control select bit 0: Output disable (Bits b7~b4 and b0 are ignored.) 1: Output enable
PWM output "H" width setting bits (Lower 4 bits: b3 to b0)
Fig. 1 Upper and Lower Byte Resister Makeup
Table 1 Mode Selection
Mode Lower 4-bit data setting PWM data setting (output enable) 12-bit data setting Output disable Input serial data Lower byte data b7 b6 b5 b4 1 b2 b7 b6 b5 b4 1 b2 XX X X 0 b2 Upper byte data b1 0 ---- b1 1 b7 b6 b5 b4 b3 b2 b1 b1 b1 X ----
Table 2 Patterns of Lower 4 Bits and Subsections Whose "H" Width Is Increased
PWM register b3-b0 0000 0001 0010 0100 1000 1111 Subsections tm whose H width is increased by (m =0 thru 15) Nothing m=8 m=4, 12 m=2, 6, 10, 14 m=1, 3, 5, 7, 9, 11, 13, 15 m=1~15 (m0) Number of Subsections 0 1 2 4 8 15
3
MITSUBISHI DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
Upper byte register b7 0 1 0 0 1 0 1 b0 0
Lower byte register b7 0 1 1 0 ? ? ? b0 ?
PWM register b11 4A616 0 1 0 0 1 0 1
b4 0
b3 0 1 1
b0 0
Determines "H" width of basic waveform (In this case, "H" width is 4A16 = 74)
Determines subsections tm whose "H" width is increased by the minimum bit width of (Refer to Table 2.) (In this case, m = 2, 4, 6, 10, 12 and 14.) x 74 2 fXIN (e.g. When fXIN is 4 MHz, = 0.5s) =
Basic waveform
x 74
Output waveform x 74
One subsection t = x 256 (8-bit resolution) x 74
Designated subsection tm (In this case, m = 2, 4, 6, 10, 12 and 14.) x 75
t0
t4 Subsection
t5
t6
t7
t8
t9
t10
t11
t12
t13
t15
One cycle
Fig. 2 PWM Waveform Output Example (Input data: 4A6 16)
OPERATION Serial Data Input When chip select CS is "L" and write control input WR is "L", data input to SIN at the edge where write clock input SCLK status shifts from "L" to "H" is written. (See Fig. 3.) At the edge where WR rises from "L" to "H", the latest 8-bit data writing is completed, and input data is stored in lower (or upper) byte register. When writing on the lower byte or writing on both upper and lower bytes is completed, data on the lower byte register or, in the latter case, data on both lower and upper byte registers is written on the PWM register of the channel designated by lower bytes b2 and b1. All setting process ends with this writing, and PWM waveform changes according to the setting from the next cycle.
PWM Waveform Output (1) 12-bit PWM output One PWM waveform cycle is divided into 16(24 ) subsections t, and each subsection is further divided into 256 (28) minimum resolution bits (= 2/fXIN) The "H" width of subsection t basic waveform is determined by the upper 8 bits of PWM data. (In Fig. 2 above, "H" width is 4A16 = 74 x ) Among these 16 subsections t, subsections tm designated by the lower 4 bits of PWM data have "H" width that is longer by . [In Fig. 2 above, the "H" width of designated 6 subsections (m =2, 4, 6, 10, 12 and 14) is 4B16 = 75 x .]
4
MITSUBISHI DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
The "H" width of undesignated subsections remains unchanged. As explained above, one cycle of waveform is a combination of two waveforms different in the "H" width. (In Fig. 2 above, one cycle consists of 10 subsections whose H width is 74 x and 6 subsections whose "H" width is 75 x .) Note: It is impossible to set one whole cycle to "H" level. (2) 8-bit PWM output As can be seen from the 12-bit PWM waveform output process as described above, 8-bit resolution PWM waveform can be output by fixing the lower 4 bits of PWM data to 00002. All subsections from t10 to t15 have the "H" width as determined by the upper 8 bits of PWM data. Note: It is impossible to set one whole cycle to "H" level. Output Control (1) Serial data input By using data on lower byte register b3 (output control selection bit), output of each channel can be controlled independently. The state of the selected PWM output changes after the completion of the ongoing cycle. When b3 is set 0, lower byte register b0 (write data designation bit) is reset. Do not write on upper byte in this case. (2) Output control input The status of all 4 channel outputs during a cycle is determined depending on the status of output control input OC at the start of the cycle. (See Fig. 6.)
Even when output is in a high-impedance state, data on each PWM register is retained, and data can be rewritten. (3) Reset When reset input R turns "L", all operation is reset as soon as the ongoing cycle is completed: The outputs of all 4 channels turns high-impedance. The PWM register of each channel is reset. When R is shifted from "L" to "H", a next cycle starts, and data writing becomes possible. However, outputs stay in the high-impedance state. (See Fig. 6.) To resume output, write input data for each channel. Initial State After power-on, outputs and PWM register data are unstable. (1) Reset Reset input R is kept on "L" level for more than one cycle (2.048ms when fXIN is 4 MHz) or more, this integrated circuit is put in a reset state. If stabilization needs more time, e. g. when a quartz resonator is used, keep R on "L" level for an adequate period of time. (2) Serial data input When starting using this integrated circuit without resetting, input false lower byte data (b0 =0) to stabilize lower byte register b0 data, and then input normal data.
WR
SIN
b0
b1
b2
b3
b4
b5
b6
b7
SCLK
PWM output Ongoing cycle Next cycle
Fig. 3 Serial Data Write Timing
5
MITSUBISHI DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
PWM Setting Data
000 16 001 16 002 16 003 16 00E 16 00F 16 010 16 011 16 012 16 013 16 x 150 963 16 x 255 FFD 16 FFE 16 FFF 16 t0 t4 t5 t6 t7 t8 t9 1 cycle 12 T= 2 x 2 fXIN t10 t11 t12 t13 t15 x 150
Fig. 4 12-bit PWM Waveform Output Example PWM Setting Data
000 16 010 16 x2 020 16 x 254 FE0 16 x 255 FF0 16 t0 t1 t2 t3 1 cycle t13 t14 t15 x 255 x 255 x 255 x 255 x 255 x 255 x 254 x 254 x 254 x 254 x 254 x 254 x2 x2 x2 x2 x2 x2
Fig. 5 8-bit PWM Waveform Output Example
6
MITSUBISHI DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
R
OC
CS
WR
SIN
DATA
Internal signal "" (cycle start signal)
PWM output High-impedance 1cycle High-impedance
Fig. 6 Output Control Timing Chart
Start
Reset
R = "L"
Set lower byte
WR = "L"
Set upper byte
1
b0 = ? 0 A
WR = "L"
NO
Setting complete? YES Output enable OC = "L", or lower byte b3 = 1
PWM output
Change settings? NO Stop
YES
Repeat series of operation A
Fig. 7 PWM Setting Flow Chart
7
MITSUBISHI DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
ABSOLUTE MAXIMUM RATINGS (Ta = -20C ~ 75C unless otherwise noted)
Symbol VCC VI VO IIK IOK IO ICC Pd Tstg Supply voltage Input voltage Output voltage Input protection diode current Output parasite diode current Output current Supply/GND current Power dissipation Storage temperature When output is "H" or under high-impedance condition VI<0V VI>VCC VO<0V VO>VCC VCC, GND Parameter Conditions Ratings -0.5 ~ +7.0 -0.5 ~ VCC + 0.5 -0.5 ~ VCC + 0.5 -10 10 -10 10 15 40 150 -65 ~ 150 Unit V V V mA mA mA mA mW C
RECOMMENDED OPERATIONAL CONDITIONS
Symbol VCC VIH VIL IOH IOL Topr Supply voltage "H" Input voltage "L" Input voltage "H" Output current "L" Output current Ambient temperature XIN Other input XIN Other input PWM1~4 VOHVCC-0.8 PWM1~4 VOL0.5 Parameter Min. 4.5 0.8VCC 2.0 0 0 0 0 -20 Limits Typ. 5 Max. 5.5 VCC VCC 0.2VCC 0.8 -4 4 75 Unit V V V V V mA mA C
ELECTRICAL CHARACTERISTICS (Ta = -20C ~ 75C, VCC = 5V10% unless otherwise noted)
Symbol VOH VOL IIH IIL IOZH IOZL ICC ICC Parameter PWM1~4 "H" Output voltage PWM1~4 "L" Output voltage "H" Input current "L" Input current "H" output current under off condition "L" output current under off condition Power dissipation Maximum quiescent power dissipation Test conditions IOH=-4mA IOL=4mA VI=VCC VI=GND VO=VCC VO=GND VI=VCC, GND, IO=0A VI=2.4, 0.4V (Note 1) Min. VCC-0.8 Limits Typ. 4.7 0.2 Max. 0.5 1.0 -1.0 5.0 -5.0 40 2.9 Unit V V A A A A A mA
0.4
Note 1: Only one input (excluding XIN) should be set to this voltage. Other inputs should be connected to VCC or GND.
8
MITSUBISHI DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
SWITCHING CHARACTERISTICS (Ta = -20C ~ 75C, VCC = 5V10% unless otherwise noted)
Symbol fmax tPLH tPHL Parameter XIN XIN PWM1~4 Test conditions CL=50pF (Note 2) Min. 16 Limits Typ.* 25 25 25 Max. 100 100 Unit MHz ns ns
Output "L"-"H", "H"-"L"
5: Standard values are measured under conditions of VCC = 5V and Ta = 25C.
TIMING CHARACTERISTICS (Ta = -20C ~ 75C, VCC = 5V10% unless otherwise noted)
Symbol tC(X) tW(XH) tW(XL) tW(S) tWRH tsu(CS) tsu(WR) tsu(S) th(CS) th(WR) th(S) th(SCLK) tr tf Parameter XIN cycle time XIN "H" pulse width XIN "L" pulse width SCLK pulse width WR "H" hold time CS "L" setup time after WR WR "L" setup time after SCLK SIN setup time after SCLK CS "L" hold time after WR WR "L" hold time after SCLK SIN hold time after SCLK SCLK hold time after WR Input rise time Input fall time Test conditions Min. 62.5 32.5 30 30 6tc (X) 30 30 50 30 10 10 30 Limits Typ.* 40 20 10 5 10 5 5 10 5 5 5 25 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5: Standard values are measured under conditions of VCC = 5V and Ta = 25C.
NOTE 2: TEST CIRCUIT
Input
VCC
Output
P.G. 50
Tested element CL GND
(1) Pulse generator (PG) characteristics: tr=tf=6ns (2) Capacitance CL includes connection floating capacitance and probe input capacitance.
9
MITSUBISHI DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
TIMING CHARTS
tsu(CS) th(CS) 3V CS 1.3V 0V tWRH 3V WR 1.3V 1.3V 1.3V 0V tsu(WR) tw(S) tw(S) th(WR) th(SCLK) 3V SCLK 1.3V 1.3V 1.3V 0V tsu(S) th(S) 3V SIN 1.3V tc(X) tw(XH) tw(XL) VCC XIN 50% 50% 0V (Internal clock) 1.3V 0V
tPLH
tPHL VOH
PWM1~4
50%
50% VOL
Note 3: (1) Shaded portions indicate that switching is possible during those periods. (2) PWM outputs 1 to 4 change synchronously with internal clock signals . The frequency of these signals is the 1/2 divider of the frequency input from XIN.
APPLICATION EXAMPLE (Combination with electronic control M5283P for amplifier system)
Electronic control M5283P Power amplifier CD FM DAT AV Graphic equalizer Speaker
Control microcomputer MCU M66242P/FP
Buffer/Low-pass filter PWM
10

▲Up To Search▲

Price & Availability of M66242FP

	To Download M66242FP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .