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MT91610
Analog Ringing SLIC Preliminary Information
Features
* * * * * * * * * * * * * * * Transformerless 2W to 4W conversion Controls battery feed to line Programmable line impedance Programmable network balance impedance Off-hook and dial pulse detection Protects against GND short circuit Programmable gain Programmable constant current mode with constant voltage fold over Transformerless balanced ringing with automatic ring trip circuit. No mechanical relay Supports low voltage ringing Line polarity reversal On-hook transmission Power down and wake up capability Meter pulse injection Ground Key detection
DS5181 ISSUE 2 February 2000
Package Information MT91610AQ 36 Pin QSOP Package
-40C to +85C
Description
The Mitel MT91610, with an external bipolar driver (Figure 4), provides an interface between a switching system and a subscriber loop. The functions provided by the MT91610 include battery feed, programmable constant current with constant voltage fold over for long loop, 2W to 4W conversion, offhook and dial pulse detection, direct balance ringing with built in ring tripping, unbalance detection, user definable line and network balance impedance's and gain, and power down and wake up. The device is fabricated as a CMOS circuit in a 36 pin QSOP package.
Applications
Line interface for: * PABX * Intercoms * Key Telephone Systems * Control Systems
RV
PD
GTX1 ESE
ESI
GTX0
VX
TD RD
Tip/Ring Drive Controller
Audio Gain & Network Balance Circuit VR
TIP RING RF1, RF2
Line Sense 2 W to 4 W Conversion & Line Impedance Over-Current Protection Circuit
Z3 Z2
CP5 Line Reverse Driver LR
RC CP4 CP6 CP7
Ring Drive Controller
Loop Supervision
CP2
CP3
VDD
VREF
GND
VEE
Figure 1 - Functional Block Diagram
VBAT
DCRI
SHK UD
CP1
1
MT91610
VDD TD TF1 NC TIP VREF LR RING RF1 NC RD CP1 CP2 CP3 CP4 ESE PD DCRI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VEE RV CP7 SHK VBAT UD RC CP6 VR GTX1 ESI VX GTX0 Z3 Z2 CP5 Z1 AGND
Preliminary Information
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name VDD TD TF1 NC Tip VREF LR Ring RF1 NC RD CP1 CP2 CP3 CP4 ESE PD DCRI AGND Positive supply rail, +5V. Tip Drive (Output). Controls the Tip transistor. Connects 150nF cap to GND. Tip Feed 1 (Output). Connects to the Tip transistor and to TIP via the Tip feed resistor. No Connection Left open Tip. Connects to the TIP lead of the telephone line. Reference Voltage (Input). Used to set the subscribers loop constant current. A 0.1uF cap should be connected between this pin and GND for noise decoupling. Line Reverse (Input). This pin should be set to 0V for NORMAL polarity. Setting the pin to +5V reverses the polarity of Tip and Ring Ring. Connects to the RING lead of the telephone line Ring Feed 1 (Output). Connects to the RING lead via the Ring feed resistor No Connection Left open Ring Drive (Output). Controls the Ring transistor. Connects 150nF cap to GND. CP1. A 220nF capacitor should be connected between this pin and pin 13 CP2. A 330nF capacitor for loop stability is connected between this pin and pin 14 CP3. A 330nF capacitor for loop stability is connected between this pin and pin 13 CP4. A 100nF cap should be connected between this pin and GND External Signal Enable (Input). A logic '1' enable the MPI (Meter Pulse Input) to Tip / Ring. This pin should be set to logic '0' when not used. Power Down (Input). A logic '1' power down the device. This pin should be set to logic '0' for normal operation. DC voltage for Ringing Input (Input) The positive voltage supply for balance ringing. The input DC voltage range is from 0V to +72V. Analog Ground. 4 Wire Ground, normally connected to system ground. Description
2
Preliminary Information
Pin Description (continued)
Pin # 20 21 22 23 24 25 26 27 28 29 30 Name Z1 CP5 Z2 Z3 GTX0 VX ESI GTX1 VR CP6 RC Description
MT91610
Line Impedance Node 1. A resistor of scaled value "k" is connected between Z1 and Z2. This connection can not be left open circuit. Line Impedance AC couple. A 0.1uF cap must be connected between this pin and Z1 (pin 16) Line Impedance Node 2. This is the common connection node between Z1 and Z3. Line Impedance Node 3. A network either resistive or complex of scaled value "k" is connected between Z3 and Z2. This connection can not be left open circuit. Gain Node 0. This is the common node between Z3 and VX where resistors are connected to set the 2W to 4W gain. Transmit Audio. 4W analog signal from the SLIC. External Signal Input. 12 / 16 KHz signal input Gain Node 1. The common node between VR and the audio input from the CODEC or switching network where resistors are fitted to sets the 4W to 2W gain Receive Audio. 4W analog signal to the SLIC. Ringing Cap. A 0.47uF cap should be connected between this pin and GND for ringing voltage filtering. Ringing Control. An active high (+5V) on this pin will set up the DC feed and gain of the SLIC to apply 20 Hz ringing. When low (0V) set the SLIC in normal constant current mode of operation. UnBalance Detect. To indicate an offset current between Tip and Ring VBAT. The negative battery supply, typically at -48V Switch Hook. This pin indicates the line state of the subscribers telephone. The output can also be used for dial pulse monitoring. This pin is active high Deglitching Cap. A 33nF should be connected between this pin and GND Ringing Voltage. 20 Hz sinusoidal or square wave AC in for balance ringing Negative supply rail, -5V. 4 wire signal, which is the output from the SLIC to the analog switch or voice CODEC. components
31 32 33 34 35 36
UD VBAT SHK CP7 RV VEE
Functional Description
Refer to Figure designation. 4 for MT91610
Gain Control
It is possible to set the Transmit and Receive gains by the selection of the appropriate external components. The gains can be calculated by the following formulae: 2W to 4W gain Gain 2 - 4 = 20 Log [ R8 / R7] 4W to 2W gain Gain 4 - 2 = 20 Log [0.891 * [R10 / R9)]
The MT91610, with external bipolar transistors, functions as an Analog Line SLIC for use in a 4 Wire switched system. The SLIC performs all of the BORSH functions whilst interfacing to a CODEC or switching system. 2 Wire to 4 Wire conversion The SLIC performs 2 wire to 4 wire conversion by taking the 4 wire signal from an analog switch or voice CODEC, and converting it to a 2 wire differential signal at Tip and Ring. The 2 wire signal applied to tip and ring by the phone is converted to a
3
MT91610
Impedance Programming
The MT91610 allows the designer to set the device's impedance across TIP and RING, (ZTR), and network balance impedance, (ZNB), separately with external low cost components. The impedance (ZTR) is set by R4, R5, whilst the network balance, (ZNB), is set by R6, R8, (see Figure 4.) The network balance impedance should calculated once the 2W - 4W gain has been set. be
Preliminary Information
Loop Supervision
The Loop Supervision circuit monitors the state of the phone line and when the phone goes "Off Hook" the SHK pin goes high to indicate this state. This pin reverts to a low state when the phone goes back "On Hook" or if the loop resistance is too high (>2.3K) When loop disconnect dialing is being used, SHK pulses to logic 0 indicate the digits being dialled. This output should be debounced.
Constant Current Control & Voltage Fold Over Mode
The SLIC employs a feedback circuit to supply a constant feed current to the line. This design is accomplished by sensing the sum of the voltages across the feed resistors, Ra and Rb, and comparing it to the input reference voltage, Vref, that determines the constant current feed current. By using a resistive divider network, (Figure 3), it is possible to generate the required voltage to set the ILOOP. This voltage can be calculated by the formula: I LOOP = [ G * 5] * 3 (Ra +Rb) where, G = R2 / (R1 + R2) I LOOP is in Ampere. R1= 200K Ra = Rb = 100 R2 = 72.73 K R2 = 100 K R2 = 133.33 K
Line Impedance
For optimum performance, the characteristic impedance of the line, (Zo), and the device's impedance across TIP and RING, (ZTR), should match. Therefore: Zo = ZTR The relationship between Zo and the components that set ZTR is given by the formula: Zo / ( Ra+Rb) = kZo / R4 where kZo = R5 Ra = Rb The value of k can be set by the designer to be any value between 20 and 250. R4 and R5 should be greater than 50k.
Network Balance Impedance
The network balance impedance, (ZNB), will set the transhybrid loss performance for the circuit. The transhybrid loss of the circuit depends on both the 4 2 Wire gain and the 2 - 4 Wire gain. The method of setting the values for R6 (or Z6... it can be a complex impedance) is given as below: R6 = R7 * (R9 / R10) * 2.2446689 * ( ZNB / ZNB + Zo)
From Figure 3 with For ILOOP = 20mA, For ILOOP = 25mA, For ILOOP = 30mA,
R2 **k
6 R1 200K
VREF
C2 0.1uF
MT91610
+5V
Please note that in the case of Zo not equal to ZNB (the THL compromized case) R6 is a complex impedance. In the general case of Zo matches to ZNB (the THL optimized case) R6 is just a single resistor.
** See Figure 6
Figure 3 - Loop Setting For convenience, a graph which plots the value of R2 (K) versus the expected loop current is shown in Figure 6.
4
Preliminary Information
As +5V is used as the reference voltage to generate the loop current, any noise on the +5V rail will deteriorate the PSR (Power Supply Rejection) parameter of the SLIC. It is therefore important to decouple +5V to GND. A 0.1uF cap at Vref pin (pin6) is recommended. The MT91610 operating current mode is recommended to be between 20mA and 30mA. The device will automatically switch to voltage hold over mode should an unexpected long loop situation occur for a given programmed loop current. The lowest operational current should be 16mA with VBAT set at -48V. A typical Operating Current versus Loop Resistance with VBAT at -48V is shown in Figure 7.
MT91610
Balanced Ringing & Automatic Ring Tripping
Balanced Ringing is applied to the line by setting the RC to +5V (pin 25) and connecting ringing signal (20Hz) to RV (pin 35) as shown in Figure 4. A 1.2Vrms input will give approximately about 60Vrms output across Tip and Ring, sufficient for short loop SLIC application. The SLIC is capable of detecting an Off Hook condition during ringing by filtering out the large A.C. component. A 0.47uF cap should be connected to pin CP6 (pin 29) to form such filter. This filter allows a true Off Hook condition to be monitored at pin SHK (pin 33). When an Off Hook condition is detected by the SLIC, it will remove the 20Hz AC ringing voltage and revert to constant current mode. The local controller will, however, still need to deselect RC (set it to 0V). The MT91610 supports short burst of ringing cadence. A deglitching input (CP7) is provided to ensure that the SHK pin is glitch free during the assertion and de-assertion of RC. A 33nF cap should be connected at this pin to GND. A positive voltage source is required to be connected to the pin DCRI (Figure 5) for normal Ringing generation. The SLIC can perform ringing even with the DCRI input connected to 0V. However, it does require the VBAT to be lower than -48V (ie at -53V or lower) and the 20Hz AC input should be a square wave at 2Vrms.
UD & Line Drivers Overcurrent Protection
The Line Drivers control the external Battery Feed circuit which provide power to the line and allows bidirectional audio transmission. The loop supervision circuitry provides bias to the line drivers to feed a constant current. Overcurrent protection is done by the following steps: (A) External bipolar transistors to limit the current of the NPN drivers to 50mA (Figure 5). (B) The local controller should monitor the Unbalance Detection output (UD) for any extended period of assertion (>5 seconds). In such case the controller should power down the device by asserting the PD pin, and polls the device every 5 seconds. The UD output can be used to support GND START LOOP in a PaBX operation. Please note that this UD output should be disregarded and masked out if RC pin is active (ie set to +5V).
Line Reversal
The MT91610 can deliver Line Reversal, which is required in operation such as ANI, by simply setting LR (pin 7) to +5V. The device transmission parameters will cease during the reversal. The LR (pin 7) should be set to 0V for all normal loop operations.
Power Down And Wake Up
The MT91610 should normally be powered down to conserve energy by setting the PD pin to +5V. The SHK pin will be asserted if the equipment side (2 wire) goes off hook. The local controller should then restore power to the SLIC for normal operations by setting the PD pin to 0V. Please note that there will be a short break (about 80ms) in the assertion time of SHK due to the time required for the loop to power up and loop current to flow. The local controller should be able to mask out this time fairly easily.
5
Powering Up / Down Sequence
AGND is always connected Powering Up: +5V, -5V, VBAT PD to +5V for 100ms; PD to 0V Powering Down: VBAT, -5V, +5V
MT91610
Meter Pulse Injection
The MT91610 provides a gain path input (ESI) for meter pulse injection and an independent control logic input (ESE) for turning the meter pulse signal on and off. Additional circuit can be used to ensure good cancellation of meter pulse signal (Figure 4) should it becomes audible at the 4 wire side. Usually, the optional circuit is not required. Gain (meter pulse) = 20 Log [0.891 * (R10 / R11)]
Preliminary Information
Step 2: Impedance Matching (R4, R5) Zo / ( Ra+Rb) = kZo / R4 where kZo = R5 R5 / R4 = 3 choose R4 = 100k => R5 = 300k Step 3: Network Balance Impedance (R6) Optimized Case Zo = ZNB R6 = R7 * (R9 / R10) * 2.2446689 * ( ZNB / ZNB + Zo) R6 = 300k * (1) * 1.1223344 = 336.7k Step 4: The Loop Current (R2) In order to remain in constant current mode during normal operation, it is necessary that the following equation holds: {| I * Zt |} V < { | VBAT | - 6*VREF - 2} V where, I = Desirable Loop Current Zt = Ra + Rb + maximum loop impedance VBAT = Battery voltage VREF= DC voltage at VREF pin Given the parameters as follows: Ra = Rb = 100 Expected maximum loop impedance = 1.6k (including Ra and Rb) Desirable Loop Current = 20mA 6*Vref=8V Then | VBAT | (min) = 1600 * 0.020 +10 = 42V Assume that the VBAT of 42V is available, then read the value of R2 from Figure 6, which is 50k. Step 5: Calculation Of Non-Clipping Sinusoidal Ringing Voltage At Tip Ring (VTR) Assume the Ringing Current is less than 40mA, the ringing voltage (20Hz) at Tip and Ring is given as: VTR (rms) = 0.707 * {| VBAT | + VDCRI - (15.6 * VREF)} VDCRI= Positive DC voltage at DCRI pin VBAT = Negative Battery voltage VREF= Positive DC voltage at VREF pin AC voltage at the RV input pin is therefore RV (rms)~= VTR (rms) / 50
Components Selection
Feed Resistors The selection of feed resistors, Ra and Rb, can significantly affect the performance of the MT91610. The value of 100 is used for both Ra and Rb. The resistors should have a tolerance of 1% (0.1% matched) and a power rating of 0.5 Watt. Calculating Components Value There are five parameters a designer should know before starting the component calculations. These five parameters are: 1) 2) 3) 4) 5) characteristic impedance of the line Zo network balance impedance ZNB value of the feed resistors (Ra and Rb) 2W to 4W transmit gain 4W to 2W receive gain
The following example will outline a step by step procedure for calculating component values. Given: Zo = 600, ZNB= 600, Ra=Rb= 100 Gain 2 - 4 = -6dB, Gain 4 - 2 = -1 dB Step 1: Gain Setting (R7, R8, R9, R10) Gain 2 - 4 = 20 Log [ R8 / R7] -6 dB = 20 Log [R8 / R7] choose R7 = 300k, R8 = 150k. Gain 4 - 2 = 20 Log [0.891 * [R10 / R9)] -1 dB = 20 Log [0.891 * [R10/ R9)] choose R9 = 200k, R10 = 200k.
6
Preliminary Information
MT91610
+5V
C5
C4
-5V
1 Vdd
36 Vee C6 RV 35 20 C10 RING VOLTAGE R16
2 C14 3 4 5 PR1 RING 8
TD
TF1 NC TIP
Z1
NO CONNECT TIP
CP5 21
R4 R5
RING
Z2
22
TR_DRIVER_610B PD 1 -5V 2 3 4 RC 13 12 11 10 9 +5V
9 RF1 NO CONNECT 10 C2 R2 R1 6 VREF2
Z3 GTX0
23 R7 24 R8 25 26 R11 C8 ESI R9 VR_IN R10 R6
NC
VX ESI
VX_OUT
5 VBAT 6 8 +5V 7 14 8 15 RF_BR TF_BR D1**
12 C13 13 C1 14
CP1 CP2
GTX1
27
VR 28 UD 31
CP3 C9 C7 SHK R13 DCRI_IN C12 15 CP4
UNBALANCE DETECTION
VBAT 32
VBAT
VBAT_IN SHK C3
18
DCRI
SHK 33 CP6
SWITCH HOOK
34 C11
CP7 ESE
29 16
ESE
ESE
11 C15
RD
PD LR
17 7
PD
POWER DOWN LINE REVERSE
RC 30 AGND 19
RC
RING CONTROL
= Ground (Earth)
* See Functional Description Meter Pulse Injection ** Optional
Figure 4 - Typical Application with a Resistive 600 ohm Line Impedance
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MT91610
Component List R11 R2 R1,9,10 R4 R5,7,16 R6 R8 R13 = = = = = = = = 100k See Figure 6 200k 100k 300k 336k7 150k 51k
Preliminary Information
C1,10 = 330nF, 5% C2,4,5,7,8 = 100nF, 5% C3 = 470nF, 5% C6 = 4.7uF, 5% C9 = 10nF, 5% C11 = 33nF, 5% C12 = 100nF, 5% C13 = 220nF, 5% C14,15 = 150nF, 5% D1 = 1N5819 Schottky Diode (Optional)
All resistors are 1/4W, 1% unless otherwise indicated. This device must always be fitted to ensure damages does not occur from inductive loads. For simple applications PR1 can be replaced by a single TVS, such as 1.5KE220C, across tip and ring. For applications requiring lightning and mains cross protection further circuitry will be required and the following protection devices are suggested: P2353AA, P2353AB (Teccor), THBT20011, THBT20012, THBT200S (SGS-Thomson), TISP2290, TSSP8290L (T.I.) TF_BR,RF_BR= Circuit Breaker PR1 =
8
Preliminary Information
MT91610
R3
R8 D9 PIN 14 RF_BR BR RF C1 Ra R31 D10 RING PIN 11 Q5 PIN 10
Q6 R1 Q7 D3 R4 RCI PIN 3 0V PIN 7 VDD R21 PIN 1 PD R22 R23 R26 Vee R2 Q3 R6 Q14 Vbat PIN 13 R7 0v D4 R5
Q8 Vbat R9
R25 Q13 R27
DCRI PIN 4 R28
R24 PIN 2 Vee VEE Q4
D13
Q1 R29 Q3 RC PIN 5 R30 R18 0v Q10
R13
R11 D11 Q9 D3 TCI PIN 12 R17 D4 R31 R12 R16 Q15 Vee Vbat R32 R15 D12 Q12 Q11 R19 Vbat VBAT_IN PIN 6 TIP PIN 9 R14 C2 PIN 15 TF_BR BR PIN 8 TF Rb
Figure 5 - Line Driver Stage
9
MT91610
Component List R1,3,6,11,13,16 = 2.5k R2,12 = 3.6k R4,5,14,15 = 470 R7,17,31,32 = 360 R8,9,18,19 = 12 Ra, Rb = 100 1%, 0.15% matched 1W R21,26,27,30 = 30k R22,25,28,29 = 3k R23,24 = 20k R21,26,27,30 = 3 k R31 = 5.1 k C1,2 = 10nF, 5%
Preliminary Information
D1-8,13 = 1N4148 or equivalent D9,10,11,12 = 1N4005 or equivalent Q1,3 = Q2,4,14,15= Q3 = Q5,7,9,11 = Q6,8,10,12,13 2N2907 2N2222 BCP56 MPSA42 = MPSA92
BR
=Circuit Breaker
All resistors are 1/4W, 1% unless otherwise indicated.
10
Preliminary Information
MT91610
R2 (Kohm) vs Loop Current (mA)
145
140
135
130
125
120
115
110
105
R2 (Kohm)
100
95
90
85
80
75
70
65
60
55 50 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Loop Current (mA)
Figure 6 - Approximated R2 (Kohm) Versus Programmed Loop Current (mA)
11
MT91610
Preliminary Information
Loop Current (mA) versus Loop Resistance (Ohm)
31
30 29 28 27 26
25 24 23
22
21
20 19 18
17 16 15
14
13 12
11 10
9
8 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000
Loop Resistance (Ohm)
Figure 7 - Loop Current (mA) Versus Loop Resistance (ohm)
12
Preliminary Information
Absolute Maximum Ratings*
Parameter 1 DC Supply Voltages Sym VDD VEE VBAT VRING Min -0.3 +0.3 +0.3 Max +6.5 -6.5 -72 70 Units V V V VRMS
MT91610
.
Comments
2
Ringing Voltages
Differentially across Tip & Ring for a 1.5Vrms input at RV (Figure 4) Note 1 MAX 1ms (with power on)
3 4 5 6 7 8 9
Voltage setting for Loop Current Overvoltage Tip/GND Ring/GND, Tip/Ring Ringing Current Tip / Ring Ground over-current Storage Temp Package Power Dissipation ESD maximum rating
VREF EE IRING TSTG PDISS
0
5 200 35 50
V V mA mA C W V
Note 2
-65
+150 0.10 500
+85C max, VBAT = -48V
*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Note 1: Refer to Figure 3 & 6 for appropriate biasing values Note 2: Tip and Ring drivers to be limited to about 50mA externally (Figure 5). If the UD pin is asserted for longer than 5 seconds, then PD should be asserted to power down the device. The device should then be checked (by de-asserting PD) every 5 seconds.
Recommended Operating Conditions
Parameter 1 Operating Supply Voltages Sym VDD VEE VBAT DCRI VRING VREF Min 4.75 -5.25 -72 5 0 Typ 5.00 -5.00 -48 60 1.67 Max 5.25 -4.75 -22 72 Units V V V V VRMS V Test Conditions
50mA current capability Note 3 ILOOP = 25mA, VBAT = -48V Note 4
2 3
Ringing Voltage Voltage setting for Loop Current
4
Operating Temperature
TO
-40
+25
+85
C
Typical Figures are at 25C with nominal supply voltages and are for design aid only Note 3: For a 1.2Vrms 20Hz input at RV terminal (Figure 4) and with RC pin set to +5V. Note 4: Refer to Figure 3 & 6 for biasing values
13
MT91610
DC Electrical Characteristics
Characteristics 1 Supply Current Sym IDD IEE IBAT IDD IEE IBAT ILOOP RLOOP Min Typ 8 6 28 300 300 1.8 25 1600 700 Max Units mA mA mA uA uA mA mA
Preliminary Information
Test Conditions
PD= 0V
VBAT= -48V lBAT ~ lLOOP + 3 mA PD = 5V VBAT = -48V VREF=1.67V ILOOP = 20mA VBAT = -48V ILOOP = 20mA VBAT = -22V
2
Supply Current
3 4
Constant Current Line Feed Operating Loop Constant Current Mode (including the DC resistance of the Telephone Set) Off Hook Detection Threshold RC, LR Input Low Voltage Input High Voltage PD, ESE Input Low Voltage Input High Voltage SHK Output Low Voltage Output High Voltage UnBalance Detection Threshold UD Output Low Voltage Output High Voltage Dial Pulse Distortion
5 6
SHK
14
mA
VIL VIH VIL VIH VOL VOH
IUD
0.5 4.5 0.5 4.5 0.4 2.7 12
V V V V V V mA
LIL = -1A LIH = 1A LIL= -1A LIH = 1A LOL = 8mA LOH = -1mA
7
8
9 10
VOL VOH
0.4 2.7 1 ms
LOL = 0.3mA LOH = -0.3mA
11
Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical Figures are at 25C with nominal 5V and are for design aid only.
14
Preliminary Information
AC Electrical Characteristics
Characteristics 1 2 3 4 5 6 7 8 9 10 11 Ring Trip Detect Time Impedance (2W) Return Loss (2W) Transhybrid Loss Output Impedance at VX Gain 4 to 2 Wire @ 1kHz Gain Relative to 1kHz Gain 2W to VX @ 1kHz Gain Relative to 1kHz Longitudinal to Metallic Balance at 2W Total Harmonic Distortion @2W @VX 12 13 Common Mode Rejection 2 Wire to Vx Idle Channel Noise @2W @VX 14 Power Supply Rejection Ratio at 2W and VX Vdd Vee 15 Line Reversal Recovery Timing TLRR PSR 23 23 30 50 dB dB ms CMR NC 12 12 dBrnC dBrnC 45 LCL THD 0.3 0.3 50 1.0 1.0 % % dB -0.5 -1.5 Sym Tt ZO RL THL 20 20 Min Typ 90 600 30 25 10 -1 0.15 0 0.15 55 0.5 -0.5 Max 200 Units mS
MT91610
Test Conditions
dB
dB dB dB dB dB dB
300Hz to 3k4Hz Note 5 AC small signal Note 5 300 - 3400Hz Note 5 300Hz to 3.4KHz 300Hz to 3.4KHz
1Vrms, 1kHz @ 2W 1Vrms, 1KHz @ VR Input 0.5Vrms, 1KHz
Cmessage Filter Fig. 4 Cmessage Filter Fig. 4
0.1Vp-p @ 1kHz Note 6
Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical Figures are at 25C with nominal 5V and are for design aid only. Note 5: Refer to Figure 4 & 5 for set up and components value. Note 6: TLRR is measured from the time when the LR pin is set to 0V (de-selected), to the time when the loop current is within 10% of its programmed steady state value.
15
MT91610
D e ZD
Preliminary Information
R E H
A A1
Pin #1 7
B
0.20
0.51 x 45 (.020) .008 (.014) 0.335 7
0.63
0.10
(.025)
.004
GAGE PLANE
C L Notes: 1. Lead Coplanitary should be 0 to 0.10mm (.004") max 2. Package surface finishing (2.1) Top Matte: (Charmilles #18-30) (2.2) All Sides: (Charmilles #18-30) (2.3) Bottom Matte: (Charmilles #18-30) 3. All dimensions excluding mold flashes 4. Max. deviation of center of package and center of leadrame to be 0.10mm (.004") 5. Max. misalignment between top and bottom center of package to 0.10mm (.004") 6. End flash from the package body shall not exceed 0.152 (.006") per side (D) 7. Dimension B shall not include dambar protrusion/intrusion and solder coverage. 8. Not to scale 9. Dimension in inches 10.Dimensions in (millimeters) a Q
QSOP - Quad Shrink Outline Package 36-Pin
Dim Dim
36-Pin Min
e H L Q R ZD
Min
A A1 B C D E .096 (2.44) .004 (0.10) .011 (0.26) .0091 (0.23) .598 (15.20) .291 (7.40)
Max
.104 (2.64) .012 (0.30) .020 (0.51) .0125 (0.32) .606 (15.40) .299 (7.60)
Max
.0315 inches (ref) 0.80mm .398 (10.11) 0.16 (0.40) 0 .025 (0.63) .414 (10.51) .050 (1.27) 8 .035 (0.89)
.0335 inches (ref) 0.85
16
Preliminary Information
Notes:
MT91610
17
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