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Integrated Circuit Systems, Inc.
ICS2595 Not recommended for new designs
User-Programmable Dual High-Performance Clock Generator
Description
The ICS2595 is a dual-PLL (phase-locked loop) clock generator specifically designed for high-resolution, highrefresh rate, video applications. The video PLL generates any of 16 pre-programmed frequencies through selection of the address lines FS0-FS3. Similarly, the auxiliary PLL can generate any one of four pre-programmed frequencies via the MS0 & MS1 lines. A unique feature of the ICS2595 is the ability to redefine frequency selections in both the VCLK and MCLK synthesizers after power-up. This permits complete set-up of the frequency table upon system initialization.
Features
* * * * * * Advanced ICS monolithic phase-locked loop technology for extremely low jitter Supports high-resolution graphics - VCLK output to 145 MHz Completely integrated - requires only external crystal (or reference frequency and decoupling) Power-down modes support portable computing Sixteen selectable VCLK frequencies (all user re-programmable) Four selectable MCLK frequencies (all user re-programmable)
Applications
* * PC Graphics VGA/Supper VGA/XGA Applications
Block Diagram
Pin Configuration
20-Pin DIP or SOIC
ICS2595 RevB 3/2/00
ICS2595
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10,14,16 11 12 13,20 15 17 18 19 PIN NAME X1 X2 EXTFREQ FS0 FS1 STROBE FS2 FS3 MS0 GND MS1 MCLK VDD VAA RESERVED REFCLK VCLK TYPE IN OUT IN IN IN IN IN IN IN PWR IN OUT PWR PWR N/C OUT OUT DESCRIPTION Quartz crystal connection 1/Reference Frequency Input Quartz crystal connection2 External Frequency Input VCLK PLL Frequency Select LSB VCLK PLL Frequency Select Bit Control for Latch of VCLK Select its (FS0-FS3) VCLK PLL Frequency Select Bit VCLK PLL Frequency Select MSB MCLK PLL Frequency Select LSB Device Ground. All pins must be connected MCLK PLL Frequency Select MSB MCLK Frequency Output Output Stage VDD. All pins must be connected Synthesizer VDD Must be connected to GND Buffered Referenced Clock Output VCLK Frequency Output
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ICS2595
Digital Inputs
The FS0-FS3 pins and the STROBE pin are used to select the desired operating frequency of the VCLK output from the 16 pre-programmed/user-programmed selections in the ICS2595. These pins are also used to load new frequency data into the registers. The standard interface for the ICS2595 matches the interface of the industry standard ICS2494. That is, the FS0-FS3 inputs access the device internals transparently when the STROBE pin is high. The digital interface for the ICS2595 (i.e. the FS0-FS3 inputs) may be optionally configured for edge-triggered or level-activated operation of the STROBE pin. Example timing requirements for each of the four options are shown in Figure 1. The programming sequence has been designed in such a way that STROBE pin need not be used (as in situations where the device is connected to the frequency select port of some VGA chips). Because the same pins are used for both VCLK frequency selection and re-programming the device frequency table, a specific procedure must be observed for selection between these modes. Device programming is accomplished by
Table 1: Programming Sequence
Nibble 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 FS0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X FS1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X FS2 0 1 START bit (must be "0") " R/W* control bit (must be "0") " LO (location LSB) " L1 " L2 " L3 " L4 (location MSB) " N 0 (feedback LSB " N1 " N2 " N3 " N4 " N5 " N6 " N 7(feedback MSB) " EXTFREQ (select if "1") " D0 (post- divder MSB) " D1 (post- divder MSB) " STO P1 bit (must be "1") " STO P2 bit (must be '1") " FS3 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VCLK Output Frequency Selection
To change the VCLK output frequency, simply write the appropriate data to the ICS2595 FS inputs. The synthesizer will output the new frequency programmed into that location after a brief delay (see time-out specifications). Upon device power-up, the selected frequency will be the frequency pre-programmed into address 0 until a device write is performed.
MCLK Output Frequency Selection
The MS0-MS1 pins are used to directly select the desired operating frequency of the MCLK output from the four pre-programmed/user-programmed selections in the ICS2595. These inputs are not latched, nor are they involved with memory programming operations.
Programming Mode Selection
In order to ensure that reliable programming under all circumstances, we require that two "nibble" writes be added to the beginning of the programming sequence that was previously specified. The new sequence is shown in Table 1. Note that the FS3 data is "0" for these first two writes. 3
executing a "programming sequence". The latched FS2 input functions as a data input, and the latched FS3 input functions as a data clock when this mode is activated. As the latched FS3 data transitions from 0 to 1, the latched FS2 data is shifted into the register. Note that it is the
ICS2595
LATCHED FS inputs, not the FS inputs themselves, that are interpreted by the internal logic. Interface logic resides between the FS input pins and the programming/frequency select logic. The appropriate "data write" procedure must be observed. See the section "Digital Interface" in this supplement for more information. These rules must be followed: * Calculate Tmax and Tmin in seconds (where R is the modulus of the reference divider and Fref is the reference frequency in Hz) by the following formulas:
Data Description
Location Bits (l0-L4)
The first five bits after the start bit control the frequency location to be re-programmed according to this table. The rightmost bit (the LSB) of the five shown in each selection of the table is the first one sent.
Table 3 - Location Bit Programming
L(4.0) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 LOCATION VCLK Address 0 VCLK Address 1 VCLK Address 2 VCLK Address 3 VCLK Address 4 VCLK Address 5 VCLK Address 6 VCLK Address 7 VCLK Address 8 VCLK Address 9 VCLK Address 10 VCLK Address 11 VCLK Address 12 VCLK Address 13 VCLK Address 14 VCLK Address 15 MCLK Address 0 MCLK Address 1 MCLK Address 2 MCLK Address 4
Tmin = Tmax =
*
6* R
Fref
4096* R
Fref
A programming sequence consists of 42 successive data writes to the device as shown in table 1: no delay greater than Tmax or less than Tmin may occur between any two successive writes. A readback sequence consists of 64 successive data writes to the device as shown in table 2: no delay greater than Tmax or less than Tmin may occur between any two successive writes. Programming or readback sequences must be preceded by a "quiet" period of at least 2* Tmax with no data writes to the device unless it was immediately preceded by another legal programming (or readback) sequence (nothing else in between) To change the active VCLK frequency selection, simply write that data to the device; the last data written to the part will always become VCLK frequency select after a delay of approximately 2* Tmax. The internal shift register is cleared at this time also.
*
*
*
Feedback Set Bits (N0-N7) These bits control the feedback divider setting for the location specified. The modulus of the feedback divider will be equal to the value of these bits + 257. The least significant bit (N0) is sent first. Post-Divider Set Bits (D0-D1) These bits control the post-divider setting for the location specified according to this table. The least significant bit (D0) is sent first.
The FS0 & FS1 inputs are not used for programming, so it is possible to use a two-pin interface for programming and frequency selection (any bank of four VCLK addresses). The reference frequency source must be operational for proper execution of the programming sequence. If the onchip crystal oscillator is, allow at least 4* Tmax after the device has valid power before attempting to program it. 4
Table 4 - Post-Divider Programming
D(1-0) 00 01 10 11 POST-DIVIDER 8 4 2 1
ICS2595
Read/Write* Control Bit
When set to a "0," the ICS2595 shift register will transfer its contents to the selected memory register at the completion of the programming sequence. When this bit is a "1," the selected memory location will be transferred to the shift register to permit a subsequent readback of data. No modification of device memory will be performed. "Readback" of a location in the frequency table may be performed by execution the 64 step readback sequence. The readback sequence is shown in Table 2. Note that the readback sequence is essentially the programming sequence (with the R/W* bit set high) followed by the actual data readback. The bi-directional FS0 pin will convert to output mode after the 42nd nibble write and the logic level output will be that of the first data bit (N0). Subsequent "clocking" by latching FS3 to "0" and then to "1" will shift out the remaining data bits. The last two writes will return the FS0 pin to input mode.
Frequency Synthesizer Description
Refer to the block diagram of the ICS2595. The ICS2595 generates its output frequencies using phase-locked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency pro-vided to the PLL. The phase-frequency detector shown in the block diagram drives the VCO to a frequency that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. This occurs when:
FVCO = FXTAL1*
N
R
EXTFREQ Input
The EXTFREQ input allows an externally generated frequency to be routed to the VCLK or MCLK output pins under device programming control. If the EXTFREQ bit is set (logic "1") at the selected address location, the frequency applied to the EXTFREQ input will be routed to the output instead of the frequency generated by the VCLK (or MCLK) PLL. When setting the EXTFREQ bit to a "1," be sure that the D0 and D1 bits are not both set to "1" also, unless it is intended that the phase-locked loop be shutdown as well.
where N is the effective modulus of the feedback divider chain and R is the modulus of the reference divider chain. The feedback divider on the ICS2595 may be set to any integer value from 257 to 512. This is done by the setting of the N0-N7 bits. The standard reference divider on the ICS2595 is fixed to a value of 43 (this may be set to a different value via ROM programming; contact factory). The ICS2595 is equipped with a post-divider and multiplexer that allows the output frequency range to be scaled down from that of the VCO by a factor of 2, 4, or 8, therefore, the VCO frequency range will be from 5.976 to 11.906 (257/43 to 512/43) of the reference frequency. The output frequency range will be from 0.747 to 11.906 times the reference frequency. Worst case accuracy for any desired fre-quency within that range will be 0.2%. If a 14.31818 MHz reference is used, the output frequency range would be from 10.697 MHz to 170.486 MHz (but the upper end is first limited to 145 MHz by the ICS2595 output driver).
Programming Example
Suppose that we want differential CLK output to be 45.723 MHz. We will assume the reference frequency to be 14.31818 MHz. The VCO frequency range will be 85.565 MHz to 170.486 MHz (5.976 * 14.31818 to 11.906 * 14.31818). We will need to set the post-divider to two to get an output of 45.723 MHz. The VCO will then need to be programmed to two times 45.723 MHz, or 91.446 MHz. To calculate the required feed-
Power Conservation
The ICS2595 supports power conservation by permitting either or both of the phase-locked loops to be disabled. This can be done by programming a particular address to have EXTFREQ, D0, & D1 bits set to a logic "1." Any frequency applied to the EXTFREQ pin will still be passed through the output multiplexer and appear at the respective output.The crystal oscillator is not affected by this power-down function and will continue to operate normally.
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ICS2595
back divider modulus we divide the VCO frequency by the reference frequency and multiply by the reference divider: 91.446 *43=274.62 14.31818 which we round off to 275. The exact output frequency will be: 275 *14.31818* 1 =45.784 MHz 2 43 The value of the N programming bits may be calculated by subtracting 257 from the desired feedback divider modulus. Thus, the N value will be set to 18 (275-257) or 000100102. The D bit programming is set to 10 (from Table 4).
Power Supply
The ICS2595 has three GND pins to reduce the effects of package inductance. All pins are connected to the same potential on the die (the ground bus). All of these pins should connect to the ground plane of the video board as close to the package as is possible. The ICS2595 has two VDD pins which supply of +5 volt power to the output stages. These pins should be connected to the power plane (or bus) using standard high-frequency decoupling practice. That is, use low-capacitors should have low series inductance and be mounted close to the ICS2595. The VAA pin is the power supply for the synthesizer circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for this pin. This will allow the PLL to track through power supply fluctuations without visible effects.
Reference Oscillator & Crystal Selection
The ICS2595 has on-board circuitry to implement a Pierce oscillator with the addition of only one external component, a quartz crystal. Pierce oscillators operate the crystal in parallel-resonant (also called anti-resonant mode). See the AC Characteristics for the effective capacitive loading to specify when ordering crystals. Crystals characterized for their series-resonant frequency may also be used with the ICS2595. Be aware that the oscillation frequency in circuit will be slightly higher than the frequency that is stamped on the can (typically 0.0250.05%). As the entire operation of the phaselocked loop depends on having a stable reference frequency, we recommend that the crystal be mounted as closely as possible to the package. Avoid routing digital signals or the ICS2595 outputs underneath or near these traces. It is also desirable to ground the crystal can to the ground plane, if possible.
External Reference Sources
An external frequency source may be used as the reference for the VCLK and MCLK PLLs. To implement this, simply connect the reference frequency source to the X1 pin of the ICS2595. For best results, insure that the clock edges are as clean and fast as possible and that the input voltage thresholds are not violated.
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ICS2595
Absolute Maximum Ratings
Supply Voltage ............................................................................................... -5V to +7 V Logic inputs ........................................................................................... 5V to VDD +.5V Ambient operating temp ................................................................................. 0 to 70C Storage temperature ............................................................................. -85C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Characteristics
PARAMETER TTL-Compatible Inputs (VS0-3, MS0-1, STROBE): Input High Voltage Input Low Voltage Input High Current Input Low Current Input capacitance XTAL1: Input High Voltage Input Low Voltage VCLK, MCLK Outputs: Output High Voltage @Ioh=0.4mA Output Low Voltage @Iol=8.0mA Vol Voh Vxh Vx1 Vih Vil Iih Iil Cin SYMBOL DC Characteristics TEST CONDITIONS MIN 2.0 VSS-0.5 VDD*0.75 VSS-0.5 2.4 TYP MAX VDD=0.5 0.8 10 200 8 VDD+0.5 VDD*0.25 0.4 UNITS V V A A pF V V V V -
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ICS2595
AC Characteristics
PARAMETER Phase-Locked Loop: VCLK, MCLK VCO Frequency PLL Acquire Time Crystal Oscillator Crystal Frequency Range Parallel Loading Capacitance XTAL1 Minimum High Time XTAL1 Minimum Low Time Power Supplies: VDD Supply Current VAA Supply Current Digital Outpluts: VCLK, MCLK, XTALOUT Rise Time @Cload=20pF VCLK, MCLK, STALOUT Fall Time @Cload=20pF SYMBOL Fvco Tlock Fxtal AC Characteristics TEST CONDITIONS MIN 60 5 Txhi Txlo idd Iaa Tr Tf 8 8 TYP 500 20 MAX 185 25 35 10 2 2 UNITS MHz Sec MHz pF ns ns mA mA ns ns
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ICS2595
Table 2: Readback Sequence
Nibble 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 FS0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X FS1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X FS2 0 1 START bit (must be "0") " R/W* control bit (must be "0") " LO (location LSB) " L1 " L2 " L3 " L4 (location MSB) " X X X X X X X X X X X X X X X X X X X X X X STOP1 bit (must be "1") " STOP2 bit (must be '1") " FS0 becomes output after write #42 X FS3 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Nibble 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
FS0 " N1 " N2 " N3 " N4 " N5 " N6 " N7 " EXTFRE " D0 " D1 " X
FS1 X X X X X X X X X X X X X X X X X X X X X X
FS2 X X X X X X X X X X X X X X X X X X X X X FS0 returns to input mode after write #64
FS3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
"X" = don't care
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ICS2595
All times shown are minimums. Figure 1. ICS2595 Digital Interface Timing
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ICS2595
Frequency Table
PATTERN Reference Divider VCLK ADDR 0 1 2 3 4 5 6 7 8 9 A B C D E F MCLK ADDR 0 1 2 3 ICS2595-02 46 VCLK 100.27 125.90 93.06 36.27 50.76 57.03 External Frequency 45.28 135.99 32.20 110.51 80.21 40.11 45.28 75.51 65.49 MCLK 40.42 45.59 N/A N/A ICS2595-04 43 VCLK 50.28 56.60 64.93 71.92 80.08 89.90 62.93 74.92 25.14 28.30 31.46 35.96 40.04 44.95 49.94 64.93 MCLK 40.20 41.54 44.54 49.61
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ICS2595
20 PIN DIP Package
20 PIN SOIC Package Ordering Information
ICS2595
Example:
ICS XXXX N-SXX
S=Strobe Option/XX=Default Freq2uencies Package T ype
N=DIP (Plastic) M=SOIC
Device Type (consists of 3 or 4 digit numbers) Prefix
ICS, AV=Standard Device; GSP=Genlock Device
Where: "S" denotes strobe option: "XX"denotes default frequencies:
D - Negative edge triggered
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