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DA7838.002 20 September, 2000
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The MAS7838 is a single chip duplex synchronous to asynchronous converter. It converts asynchronous start stop characters to synchronous character format, with stop bit deletion when required as defined in the CCITT recommendation V.14 (V.22). On the receiver channel the MAS7838 converts the incoming synchronous data to asynchronous start stop character format with stop bit insertion when required as defined in the CCITT recommendation V.14 (V.22).The MAS7838 implements the data modes for the synchronous interface as specified in the V.14 (V.22). The device can be configured to operate at any frequency to maximum device speed within the above mentioned modes.
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* Implements CCITT recommendations V.14 and V.22 chapters 4.1, 4.2 and 4.3 * Operates in modes as defined in the CCITT recommendations V.22 (i), ii), iii), iv) and v) * Transmission rate up to 64 kbit/s * CMOS compatible interface * Low power consumption (typically 25 mW) * No additional circuitry required to perform the conversion * CMOS device * Single =5V supply
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* * * Adapts asynchronous terminals to synchronous modems Full or half card PC modems using UART as a data source Simplifying data multiplexing in a MUX/DEMUX system
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CL1
CONTROL
VDD
CL2 XESR TMG OSC TSL TXC TDO RXC RDI XASY
> _1 SYNC TO ASYNC ASYNC TO SYNC O S C
TDI
RDO
XHST VSS
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DA7838.002 20 September, 2000
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PDIP 16 SO16
MAS7838N
TSL 1 TMG 2 OSC 3 TXC 4 CL1 5 CL2 6 XESR 7 VSS 8
A A A X Y Y Y Y Y X Y A A A A A A A & ' " '
16 VDD 15 RXC 14 RDI 13 RDO 12 XHST 11 XASY 10 TDO 9 TDI TSL TMG OSC TXC CL1 CL2 XESR VSS 1 2 3 4 5 6 7 8
MAS7838S
16 15 14 13 12 11 10 9 VDD RXC RDI RDO XHST XASY TDO TDI
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3LQ QDPH TSL TMG OSC TXC 3LQ QR 1 2 3 4 ,2 I I O I Timing select. 0 selects asynchronous sampling timing 16 x TXC from pin 2, TMG. 1 selects asynchronous sampling timing 256...8192 x TXC from pin 2, TMG. Timing. Square wave timing signal 16 x TXC (TSL=0) or 256...8192 x TXC (TSL=1). Max f=10 MHz. Oscillator. Output for crystal. If used, the crystal is connected between pins 2 and 3. Transmitter timing. Synchronous square wave timing for transmitter. The transmitted data output, TDO is synchronized to the rising edge of TXC. The duty cycle of TXC has to be 50% +/- 5%. Character length. The total character length including one start bit, one stop bit and possible parity bit is selected with the CL1 and CL2 signals. Extended signalling rate. The tolerance of the synchronous bit rate can be: XESR = 1 (basic signalling rate) TXC -2.5%...+1.0% XESR = 0 (extended signalling rate) TXC -2.5%...2.3% Ground Transmitter data input. 1 = mark or stop bit, 0 = space, start or break signal Transmitter data output. The output data is synchronized to the synchronous timing signal TXC (pin 4). 1 = mark, 0 = space Asynchronous mode. XASY=0 Asynchronous transmission. XASY=1 Synchronous transmission. In synchronous transmission the converter is totally bypassed in both directions: TDI=TDO, RDI=RDO Higher speed signalling timing. XHST = 1 normal synchronous to asynchronous conversion (Bell 212; CCITT V.22). XHST = 0 asynchronous to synchronous conversion with higher speed synchronous timing (TXC, RXC). TXC and RXC timing must be 1-2% higher than the normal bit rate in order to allow some overspeed in the asynchronous data. On the receiver side the RX buffer is deleted and the synchronous data RDI is directly connected to the asynchronous output RDO. Receiver data output. RDO is the received data converted back to asynchronous mode. 1 = mark or stop bit, 0 = space, start or break signal Receiver data input. 1 = mark, 0 = space. The received data must be synchronized to the receiver timing RXC from the synchronous channel (pin 15). Receiver timing. Receiver square wave timing from the synchronous channel. The received data RDI must be synchronized to the rising edge of RXC. Power supply
CL1 CL2 XESR
5 6 7
I I I
VSS TDI TDO XASY
8 9 10 11
G I O I
XHST
12
I
RDO
13
O
RDI RXC VDD
14 15 16
I I P
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3DUDPHWHU Supply Voltage Storage Temperature 6\PERO VDD Ts &RQGLWLRQV 0LQ -0.5 -55 0D[ 5.5 +150
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3DUDPHWHU Input high voltage Input low voltage Input leakage current Input capacitance load Internal pull-up resistor for digital inputs
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Timings between synchronous clocks and data are shown below. Note that absolute delays depend on the speed of the data transmission.
TTXC TXC
TDO
T1
delay
TRXC RXC
T2 T3
RDI
If pin TSL = 1 (Automatic synchronous sampling timing)
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u $V\QFKURQRXV WR V\QFKURQRXV FRQYHUWHU The synchronous start-stop character, TDI (transmitter data input), is read into the Tx buffer. When the character is available the data bits are transferred as TDO (transmitter data output) with the synchronous timing signal TXC (transmitter clock). The bit rate of TDI must be the same as the TDO rate within -2.5%...+1% or -2.5%...+2.3% tolerance depending on XESR (extended signalling rate) signal. The transmitter adds extra stop bits to the synchronous data stream, if TDI is slower than TDO. The over speed is handled by u 6\QFKURQRXV WR DV\QFKURQRXV FRQYHUWHU The synchronous RDI (receiver data input) is buffered to recognise the stop and start bits. If a missing stop bit is detected, it is added to the RDO (receiver data output). In this case the stop bits are shortened 12.5% uA&RQYHUWLQJ ZLWK KLJKHU VSHHG WLPLQJ An alternative method to handle the over speed in asynchronous data is to boost synchronous timing TXC and RXC by 1-2%. In this mode XHST (higher speed timing) = 0. In this case there is no need to delete any stop bits in the transmitter buffer. The break signal goes through unchanged. On the receiver side the synchronous data, RDI, is transferred directly to the asynchronous output RDO with RXC. (25% if XESR = 0) during each character. When the receiver gets at least 2M + 3 bits of start polarity, it does not add stop bits to RDO. This enables the break signal to go through the buffer. deleting one stop bit in every 8th character at maximum in the synchronous output data TDO. When extended signal rate (XESR = 0) is used 4th stop bit may be deleted. When the transmitter detects a break signal( at least M bits of start polarity, where M is length of character), it sends 2M + 3 bits of start - polarity to TDO. If the break is longer than 2M + 3 bits, then all bits are transferred to TDO. After a break signal, at least 2M bits of stop polarity must be transmitted before sending further data.
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DA7838.002 20 September, 2000
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u 7LPLQJ VHOHFWLRQ The MAS7838 requires clock signals in order to function properly. The synchronous data transfer always requires the TXC clock. The clock is used internally for: -shifting data out from the TX buffer (to pin TDO) -shifting data into the RX buffer (via pin RDI) -detection of the bit rate in order to adjust the internal baud rate generator (only if TSL = 1) The asynchronous data transfer (pins TDI, TDO) is accomplished by generating an internal timing signal for the asychronous circuits. This internal timing signal (16T) is 16 times the TXC bit rate in order to sample the asynchronous data stream (TDI) at the proper speed.
Timing Circuits 16 x TXC
MAS 7838
TXC
EXTERNALLY GENERATED 16T CLOCK
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u 6\QFKURQRXV PRGHP ZLWK DV\QFKURQRXV LQWHUIDFH The MAS7838 is intended for applications where an asynchronous and synchronous data source must be linked together. A typical case appears in a data modem where the terminal interface of the modem has been specified to be asynchronous but the modem data pump operates in a synchronous fashion.
RS232C
MAS9138 MODEM CIRCUITS
INTERFACE
TXD
TDI
TDO TXC RDI
RXD
RDO
RXC
PHONE LINE
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DA7838.002 20 September, 2000
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RS232C
MAS7838 MODEM CIRCUITS
uP INTERFACE
TDI
TDO TXC RDI Sync Modem Data Pump
PHONE LINE
RDO
RXC
u 6\QFKURQRXV VHULDO LQWHUIDFH ZLWK X3 LQWHUIDFH Another application is a synchronous serial interface for uP which uses UART as a data source. The concept is illustrated below. u 'DWD PXOWLSOH[HU A third application is a data multiplexing/demultiplexing system. The system accepts data from several sources. These data lines are sampled and the samples are sent through a multiplexer to a demultiplexer. To accomplish this, either a very high sample rate is needed or first convert the data to synchronous mode, where synchronous multiplexing can be used and only one sample per data bit is needed.
M AS7838 TDI CH 1 RDO 1 TDO RDI RDI TDO
M AS7838 RDO 1 TDI
M AS7838 FORWARD CH 2 2
M AS7838
MUX/ DEMUX
BACKWARD
MUX/ DEMUX
2
TIMING CH N N N
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DA7838.002 20 September, 2000
$33/,&$7,21 ,1)250$7,21
+5v RS232C TXD TTL/V28 78189A
470pF
Synchronous Modem TDO TXC RDI RXC TTL-Level TTL-Level TTL-Level TTL-Level *) 16 x TXC RXC TXC
TDI 9
16
10 4
+12v TTL/V28 RDO 13 75189A +5v +5v -12v TSL XHST 1 12 7 5 6 8
14 15
RXD
470pF
MAS7838
2
22pF
3x 4.75k
Ext. Signal Rate Char. Length Char. Length
CR 1
9.8304MHz
3
22pF
ASY/SYN Select 11
Modem Timing Circuit
mode selection jumpers
+5v
*) Optional timing from the synchronous modem. In this case CR 1 can be eliminated. MAS7838 simplified application: V.28 interface for synchronous modem
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DA7838.002 20 September, 2000
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16 LEAD PDIP OUTLINE (300 MIL BODY)
6.10 7.11 1.52
18.93 21.33
2.93 4.95
5.33 MAX
7.62 BSC
0 .2 5 4
5.5
5-7
SEATING PLANE
0.36 0.56
1.15 1.77
2.54 BSC
0.63 TYPICAL
1 PIN
ALL MEASUREMENTS IN mm
All dimensions are in accordance with JEDEC standard MS-001.
16 LEAD SO OUTLINE (300 MIL BODY)
0.33 x 45 5 TYP. 5TYP 0.25 RAD. MIN. 0.94 1.12 1.27 5 TYP. TYP. 0.36 0.48 0-0.13 RAD.
2.36 2.64 10.10 10.50 10.00 10.65 PIN 1 ALL MEASUREMENTS IN mm 7.40 7.60 0.10 0.30
SEATING PLANE
5 TYP. 5 TYP.
. 0.86 TYP
All dimensions are in accordance with JEDEC standard MS-013.
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DA7838.002 20 September, 2000
25'(5,1* ,1)250$7,21
3URGXFW &RGH MAS7838N MAS7838S-T MAS7838S 3URGXFW 3DFNDJH PDIP16 SO16 SO16 &RPPHQWV 25 pcs/tube 1000 pcs/reel 47 pcs/tube MSB0091A Bake recommendation for surface mounted devices
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Micro Analog Systems Oy Kamreerintie 2, P.O.Box 51 FIN-02771 Espoo, FINLAND http:\\www.mas-oy.com Tel. (09) 80 521 Tel. Int. +358 9 80 521 Telefax +358 9 805 3213 E-mail: info@mas-oy.com
NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
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