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(R) STD16NE10L N - CHANNEL 100V - 0.07 - 16A DPAK STripFETTM POWER MOSFET PRELIMINARY DATA TYPE STD16NE10L s s s s s s s V DSS 100 V R DS(o n) < 0.10 ID 16 A TYPICAL RDS(on) = 0.07 AVALANCHE RUGGED TECHNOLOGY LOW GATE CHARGE HIGH CURRENT CAPABILITY 175 oC OPERATING TEMPERATURE LOW THRESHOLD DRIVE ADD SUFFIX "T4" FOR ORDERING IN TAPE & REEL 3 1 DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SOLENOID AND RELAY DRIVERS s DC-DC & DC-AC CONVERTERS s AUTOMOTIVE ENVIRONMENT DPAK TO-252 (Suffix "T4") INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symb ol V DS V DGR VGS ID ID I DM (*) P tot Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (R GS = 20 k) G ate-source Voltage Drain Current (continuous) at Tc = 25 oC Drain Current (continuous) at Tc = 100 o C Drain Current (pulsed) T otal Dissipation at Tc = 25 C Derating Factor dv/ dt (1) Peak Diode Recovery voltage slope T st g Tj Storage Temperature Max. Operating Junction Temperature o Value 100 100 20 16 11 64 55 0.36 7 -65 to 175 175 ( 1) ISD 16A, di/dt 300 A/s, VDD V(BR)DSS, Tj TJMAX Unit V V V A A A W W /o C V/ns o o C C (*) Pulse width limited by safe operating area May 2000 1/6 STD16NE10L THERMAL DATA R th j-pc b R thj -amb R t hj-s ink Tl Thermal Resistance Junction-PC Board Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink T yp Maximum Lead Temperature F or Soldering Purpose 2.73 100 1.5 275 o o C/W C/W o C/W o C AVALANCHE CHARACTERISTICS Symbo l IAR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 30 V) Max Value 16 75 Unit A mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 A V GS = 0 Min. 100 1 10 100 Typ. Max. Unit V A A nA V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) V GS = 20 V T c = 125 oC ON () Symbo l V GS(th) R DS(on) I D(o n) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance On State Drain Current V GS = 10 V V GS = 5 V Test Con ditions ID = 250 A ID = 8 A ID = 8 A 16 Min. 1 Typ. 1.7 0.07 0.085 Max. 2.5 0.085 0.1 Unit V A V DS > ID(o n) x R DS(on )ma x V GS = 10 V DYNAMIC Symbo l g f s () C iss C os s C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Con ditions V DS > ID(o n) x R DS(on )ma x V DS = 25 V f = 1 MHz ID = 8 A V GS = 0 V Min. 5 Typ. 9 1750 165 45 Max. Unit S pF pF pF 2/6 STD16NE10L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l t d(on) tr Qg Q gs Q gd Parameter Turn-on Delay T ime Rise Time Total G ate Charge Gate-Source Charge Gate-Drain Charge Test Con ditions V DD = 50 V ID = 8 A R G = 4.7 V GS = 4.5 V (Resistive Load, see fig. 3) V DD = 80 V ID = 16 A V GS = 5 V Min. Typ. 40 80 24 5.5 11 32 Max. Unit ns ns nC nC nC SWITCHING OFF Symbo l t d(of f) tf tr (Voff) tf tc Parameter Turn-off Delay T ime Fall T ime Off-voltage Rise T ime Fall T ime Cross-over Time Test Con ditions V DD = 50 V ID = 8 A V GS = 4.5 V R G = 4.7 (Resistive Load, see fig. 3) V DD = 80 V I D = 16 A V GS = 4.5 V R G = 4.7 (Induct ive Load, see fig. 5) Min. Typ. 45 12 12 17 35 Max. Unit ns ns ns ns ns SOURCE DRAIN DIODE Symbo l ISD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 16 A V GS = 0 100 300 6 I SD = 16 A di/dt = 100 A/s T j = 150 o C V DD = 40 V (see test circuit, fig. 5) Test Con ditions Min. Typ. Max. 16 64 1.5 Unit A A V ns nC A () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area 3/6 STD16NE10L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STD16NE10L TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397 DIM. H A C2 C DETAIL "A" A1 L2 D DETAIL "A" B = = 3 B2 = = G E 2 L4 1 = = A2 0068772-B 5/6 STD16NE10L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6 |
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