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LR38603
LR38603
DESCRIPTION
The LR38603 is a CMOS digital signal processor for color CCD video camera systems of 270 k/320 k/ 410 k/470 k-pixel CCDs with complementary color filters. The video camera system consists of CDS/PGA/ADC IC (IR3Y48A1), DSP IC (LR38603) and V driver IC (LR36685) with CCD.
Digital Signal Processor for Color CCD Cameras
FEATURES
* Designed for 1/4-type 270 k/320 k/410 k/470 kpixel color CCDs with Mg, G, CY, and Ye complementary color filters * Switchable between NTSC and PAL modes * Built-in signal generation circuit for driving CCD and various pulses for TV signals * Parameters for camera signal processing can be set * Built-in auto exposure control * Built-in auto white balance control * Built-in auto carrier balance control * Built-in drive circuit for 2 K-bit EEPROM * Built-in 9-bit D/A converter * Built-in mirror image output * Built-in circuit to reduce line crawl noise * Built-in auto white detect correction * YUV digital output (8 bits x 2) * UYVY digital output (8 bits x 1) * Analog video output * External clock input (8 fsc) * Built-in vertical reset * Built-in horizontal reset * Single +3.3 V power supply * Package : 80-pin LQFP (P-LQFP080-1212) 0.5 mm pin-pitch
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1
LR38603
PIN CONNECTIONS
80-PIN LQFP
FCDS FS RS GND VDD FH2 FH1 FR GND VDD OFDX VH3X VH1X GND VDD V4X V3X V2X V1X VD
TOP VIEW
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ACL CKI CKO VDD GND ADCK SCK SDATA ADI9 ADI8 ADI7 ADI6 ADI5 ADI4 VDD GND ADI3 ADI2 ADI1 ADI0
61
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
HD Y7 Y6 Y5 Y4 VDD GND Y3 Y2 Y1 Y0 EXCKI DCK2 DCK1 VDD GND EEMD3 EEMD2 EEMD1 EEMDS
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OBCP ADCLP BLKX EEPDA GND VDD EEPCK EEPFL EEPSL WB1 WB2 MIR BLC GNDDA VDDDA VB IREF VREF GNDDA VIDEO
(P-LQFP080-1212)
2
40
LR38603
BLOCK DIAGRAM
ADI9-ADI0
OB CLAMPING
4 LINES DELAY
LUMINANCE SIGNAL PROCESS
VIDEO 9-BIT DA Y7-Y0
BLKX, CSYNC HD, VD, ADCLP OBCP
SSG
COLOR SIGNAL PROCESS
DCK1, DCK2
EXCKI
CKI CKO FR, FH1, FH2 V1X-V4X VH1X, VH3X FCDS, FS, RS ADCK TG EEPSL, EEPFL EEPCK, EEPDA
AUTOMATIC CONTROL
EEPROM CONTROL
EEMD2, EEMD3 EEMDS, EEMD1 WB1, WB2, MIR, BLC
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LR38603
PIN DESCRIPTION
PIN NO. SYMBOL IO SYMBOL POLARITY 1 ACL ICSU All reset 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CKI CKO VDD GND ADCK SCK SDATA ADI9 ADI8 ADI7 ADI6 ADI5 ADI4 VDD GND ADI3 ADI2 ADI1 ADI0 OBCP ADCLP BLKX OSCI OSCO - - OBF4M OBF4M OBF4M IC IC IC IC IC IC - - IC IC IC IC OBF4M OBF4M OBF4M DESCRIPTION
Input for reference clock oscillator Connect to CKO (pin 3) with R. NTSC : 28.63636 MHz PAL : 28.375 MHz Output for reference clock oscillator. The output is the inverse of CKI (pin 2). Power supply input (+3.3 V) Ground Clock output for A/D converter Connect to ADCK of IR3Y48A1. Clock output for setting parameter of IR3Y48A1 Serial data output for setting parameter of IR3Y48A1 Digital signal input (MSB) Digital signal input Digital signal input Digital signal input Digital signal input Digital signal input Power supply input (+3.3 V) Ground Digital signal input Digital signal input Digital signal input Digital signal input (LSB) Clamp pulse output for optical black Clamp pulse output Blanking pulse output Data input from EEPROM Connect to a data output pin of EEPROM. When setting internal register from an external device, use EEPCK, EEPFL and EEPSL together with EEPDA. This pin is for serial data input. Ground Power supply input (+3.3 V) Clock output for EEPROM Connect to clock input of EEPROM. When setting internal register from external device, this pin is used as serial clock. Control for setting internal register from an external device Usually used at H level. Control for setting internal register from external device Usually used at L level. When setting register, set EEPSL at H level.
24
EEPDA
IO4MU
25 26
GND VDD
- -
27
EEPCK
IO4MSU
28
EEPFL
ICU
29
EEPSL
ICD
4
LR38603
PIN NO. SYMBOL IO SYMBOL POLARITY 30 WB1 IO4MD
DESCRIPTION WB setting. Use together with WB1 and WB2 00 (WB2, WB1) : Auto white balance 11 : WB3 mode 01 : WB1 mode 10 : WB2 mode
31
WB2
IO4MD
These pins are 0 bit (WB1) and 1st-bit (WB2) of UV output in output digital YUV mode. Setting for mirroring video output mode L : Normal H : Mirroring This pin is 2nd-bit of UV output in output digital YUV mode. Switching internal register for exposure-standard This pin is 3rd-bit of UV output in digital output mode. Ground for internal D/A converter Power supply for internal D/A converter Connect to DC 3.3 V power supply (+3.3 V). DC output of internal D/A converter. Connect to ground pin via capacitor. DC output of internal D/A converter. Connect to ground pin via register. DC reference input for internal D/A converter Connect to DC power supply (+1.0 V). Ground for internal D/A converter. Analog video output Switching electronic shutter control Use together with EEMDS, EEMD1, EEMD2 and EEMD3. Refer to "Electronic Shutter Speed Setting" in AUTOMATIC CAMERA FUNCTION CONTROL. These pins are 4th to 7th-bit of UV output in digital output mode. When in line lock mode, EEMD2 : H reset EEMD3 : V reset Ground Power supply input (+3.3 V). Clock output synchronized with digital output Switchable among CSYNC, CBLK or L level. ID pulse output of UV signal for digital output When in analog output, output is KEI or L level.
32
MIR
IO4MD
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
BLC GNDDA VDDDA VB IREF VREF GNDDA VIDEO EEMDS EEMD1 EEMD2 EEMD3 GND VDD DCK1
IO4MD - - DAO DAO DAI - DAO IO4MU IO4MU IO4MU IO4MU - - OBF4M
48
DCK2
OBF4M
KEI pulse : At power-on, begin with L level. When shutter speed is 1/60 s (PAL 1/50 s) and PGA gain is more than the value in address 92h, it goes to H level and becomes stable. Input for external clock Digital video signal output Use together with Y7 (MSB) to Y0 (LSB). UYVY signal or illumination signal output (according to the register). Ground
49 50 51 52 53 54
EXCKI Y0 Y1 Y2 Y3 GND
ICSU OBF4M OBF4M OBF4M OBF4M -
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LR38603
PIN NO. SYMBOL IO SYMBOL POLARITY 55 VDD - Power supply input (+3.3 V) 56 57 58 59 Y4 Y5 Y6 Y7 OBF4M OBF4M OBF4M OBF4M Digital video signal output
DESCRIPTION
Use together with Y7 (MSB) to Y0 (LSB). UYVY signal or illumination signal output (according to the register) Horizontal drive pulse output It is able to select horizontal drive pulse for drive timing and video output timing from BELL pulse, HREF pulse and L level. BELL pulse : The signal that goes to H level 1 time per 1 field. Vertical drive pulse output
60
HD
OBF4M
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
VD V1X V2X V3X V4X VDD GND VH1X VH3X OFDX VDD GND FR FH1 FH2 VDD GND RS FS FCDS
OBF4M OBF4M OBF4M OBF4M OBF4M - - OBF4M OBF4M OBF4M - - OBF12M OBF12M OBF12M - - OBF4M OBF4M OBF4M
It is able to select from VD, CSYNC and VS outputs for drive timing and video output timing. CCD vertical drive pulse output Connect each pin to CCD via V driver IC. Power supply input (+3.3 V) Ground Pulse output for reading charges Connect each pin to CCD via V driver IC. OFD pulse output. Connect each pin to CCD via V driver IC. Power supply input (+3.3 V) Ground Reset pulse output. Connect each pin to CCD via capacitor. Horizontal transmit pulse output Connect to CCD. Power supply input (+3.3 V) Ground Pulse output for sample hold When using IR3Y48A1, connect to CSN pin for parameter setting. Pulse output for sample hold Pulse output for sample hold
DAO OSCO IO4MU IO4MD IO4MSU : : : : : Output pin for D/A converter Output pin for oscillation Input/output pin with pull-up resistor Input/output pin with pull-down resistor Input/output pin with pull-down resistor (schmidt input)
IC ICU ICD ICSU DAI OSCI OBF4M OBF12M
: Input pin : Input pin with pull-up resistor : Input pin with pull-down resistor : Schmidt input pin with pull-up resistor : Input pin for D/A converter : Input pin for oscillation : Output pin : Output pin
6
LR38603
DSP REGISTER TABLE
ADDRESS NAME BIT CONTENTS 00h STOP_EEPROM [7 : 0] Stop reading from EEPROM only when EEPROM data is FF. 01h LPF_TH [7] H : Luminance signal processing without LPF (when using B/W CCD) CCD_SEL [6 : 5] 00 : 270 k pixel CCD (NTSC) 01 : 410 k pixel CCD (NTSC) 10 : 320 k pixel CCD (PAL) 11 : 470 k pixel CCD (PAL) ADTI [4 : 3] Input data timing adjustment 00 : Reference 01 : 1 clock delay 10 : 1 clock forward 11 : 2 clocks forward [2] 1 : Latch with inverted clock SEL_CDS [1 : 0] Fixed to 1X (IR3Y48A1) 02h NI [6] 0 : Interlace 1 : Non-interlace MODE_OUT_SIG Select output mode. [5 : 3] 000 : Analog video output EXCKI : Vertical reset pulse input 001 : Analog video output EXCKI : 8 fsc clock input EEMD3 : Vertical reset pulse input EEMD2 : Horizontal reset pulse input 010 : Analog video output EEMD2 : Horizontal reset pulse input EEMD3 : Vertical reset pulse input 100 : YUV digital video output : Clock rate of video data pixel-CK 101 : YUV digital video output : Clock rate of video data EXCKI 110 : UYVY digital video output : Clock rate of video data EXCKI 011, 111 are prohibited. START_EE [2] Shutter speed at power-on 0 : minimum 1 : maximum AGC_FIX [1] PGA control 0 : Auto 1 : Fixed OB_SEL [0] Carrier balance control 0 : Auto 1 : Fixed 03h HD_SEL [6 : 5] Select output signal from HD pin 00 : HD output (CCD drive timing) 01 : HD output (video output timing) 10 : BELL pulse (in analog video output), HREF (in digital video output) 11 : Fixed to L level VD_SEL [4 : 3] Select output signal from VD pin 00 : VD output (CCD drive timing) 01 : VD output (video output timing) 10 : Fixed to L level (in analog video output), VS (in digital video output) 11 : Fixed to L level (in analog video output), CSYNC (in digital video output) DCK1_SEL [2 : 1] Select output signal from DCK1 pin (in analog video output) 00 : CSYNC 01 : CBLNK 1X : Fixed to L level DCK2_SEL [0] Select output signal from DCK2 pin (in analog video output) 0 : Fluorescent signal 1 : Fixed to L level 04h SW_CTRL [7 : 0] Electronic shutter control (EEMDS, EEMD1, EEME2, EEMD3), mirror video output (MIR [MSB]), internal register for exposure-standard (BLC) and white balance (WB2, WB1 [LSB]) are set when selecting digital output mode with MODE_OUT_SIG (address 02h). Shutter control of EEMD2 and EEMD3 is set by the register of SW_CTRL and that of EEMDS and EEMD1 is set by pin 41 and pin 42 when setting "001" and "010" with MODE_OUT_SIG (address 02h).
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LR38603
ADDRESS NAME 05h MIN_SH_SEL MAX_SH 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h REF_IRIS1 CTLD_AGC CTLD_0 REF_IRIS2 CLIP_IRIS UW_E1 UW_E2 UW_E3 UW_E4 UW_E5 UW_E6 UW_E7 UW_E8 CW_E CWP_E CWA_E EE_DIV_STP LPFE_O LPFE_I 17h 18h 19h P_HEE P_LEE MOD8 IRIS_DLY
BIT [7]
CONTENTS Select minimum shutter speed 0 : 1/60 s (1/50 s) 1 : 1/100 s (1/120 s)
[6 : 0] Restriction in maximum shutter speed (When EEMDS, EEMD1, EEMD2, EEMD3 = 4' b1110) [7 : 0] Reference of exposure [7 : 0] Outside range of error of exposure reference (Hysteresis range of IRIS and PGA tweaking range) [7 : 0] Inside range of error of exposure reference (Exposure control is stopped in REF_IRISCTLD_0) [7 : 0] Exposure reference in condition against light (When BLC = H) [7 : 0] Ceiling clip in accumulate exposure data [7 : 0] Downward weight factor 1 in calculation of exposure. (upper of screen) [7 : 0] Downward weight factor 2 in calculation of exposure. [7 : 0] Downward weight factor 3 in calculation of exposure. [7 : 0] Downward weight factor 4 in calculation of exposure. [7 : 0] Downward weight factor 5 in calculation of exposure. [7 : 0] Downward weight factor 6 in calculation of exposure. [7 : 0] Downward weight factor 7 in calculation of exposure. [7 : 0] Downward weight factor 8 in calculation of exposure. (lower of screen) Sum of UW_E1 to UW_E8 must be 256d. [6 : 0] Ratio of downward IRIS against center [5 : 0] Center point, position of left-upper area. [5 : 0] Center point, size of area. [6 : 4] Select dividing value of shutter speed control. [3 : 2] Select LPF of IRIS data in PGA normal adjustment. [1 : 0] Select LPF of IRIS data in PGA tweak. [7 : 0] Ratio of luminance H peak of IRIS data [7 : 0] Ratio of luminance L peak of IRIS data [4] Select peak accumulation. 0 : Avg. of 8 pixels 1 : Avg. of 4 pixels [3 : 2] Reduction of IRIS control in normal operation. 00 : Operating always 01 : Operating each 2VD timing 10 : Operating each 4VD timing 11 : Operating each 8VD timing [1 : 0] Reduction of IRIS control in PGA tweak. 00 : Operating always 01 : Operating each 2VD timing 10 : Operating each 4 VD timing 11 : Operating each 8VD timing
IRIS_DLY
1Ah 1Bh 1Ch 1Dh 1Eh
AG_DIV_STP AG_GAIN MAX_AGC REF_AGC S_38M_GA S_38M_GA_U S_38M_MX
[7 : 5] Select dividing value of PGA control. [4 : 0] Number of steps in PGA gain [7 : 0] Upper limitation of PGA control. [7 : 0] Lower limitation of PGA control (initial value of PGA at power-on). [7 : 0] Fixed PGA gain [7 : 0 (LSB) ] [3] [2 : 0] Fixed PGA gain when using IR3Y48A1 [8 (MSB)] IR3Y48A1 minimum gain [1 : 0] 00 : 0 01 : +6 dB 10 : +12 dB 11 : -2 dB
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LR38603
ADDRESS 1Fh
NAME S_38M_OFS
BIT [7]
CONTENTS Offset auto adjustment. 0 : Auto 1 : Fixed (when using IR3Y48A1)
[6 : 0] Factor in fixed offset mode Fixed to 40h when using IR3Y48A1. 20h 21h 22h 23h 24h CSEPR CSEPB CB_R CB_B C_GAM YL_SEL C1_RB_SEL [7 : 0] R side factor of color separation (positive value) [7 : 0] B side factor of color separation (positive value) [7 : 0] R side factor of carrier balance (complement of 2) [7 : 0] B side factor of carrier balance (complement of 2) [5 : 3] Select characteristics of color gamma. [2 : 1] Manner of YL signal production ([2 : 1]) 00 : Avg. of 3 lines 01 : Each R, B line 1X : Fixed ratio [0] Manner of RG signal production 0 : Use color separation factor (address 20h, 21h) 1 : Use fixed color separation factor. Matrix factor 0 : Unsigned 1 : Signed 1 : Operation against line crawl in color processing. 1 : Set YL to 0 in chrominance generation. Switch order of UV digital output Swap R and B after color separation. Swap R - Y and B - Y in output Switch attributes of SP1 and SP2. Switch attribute of color separation HG.
25h
MODE_MAT LC_ON_RB YL_SUB UV_CTRL1 SEL_RB SEL_RB2 SPCTRL IDCO
[7] [6] [5] [4] [3] [2] [1] [0]
26h 27h 28h 29h 2Ah
MAX_WBR MIN_WBR MAX_WBB MIN_WBB JMP_OFF AWB_HIGH MAX_IQAREA IQ_LPF
[7 : 0] Upper limit of R side range of AWB gain (9 bits data which includes 1 at LSB) [7 : 0] Lower limit of R side range of AWB gain (9 bits data which includes 1 at LSB) [7 : 0] Upper limit of B side range of AWB gain (9 bits data which includes 1 at LSB) [7 : 0] Lower limit of B side range of AWB gain (9 bits data which includes 1 at LSB) [4] 0 : Normal 1 : Suppress AWB skipping [3] [2] 0 : Normal 1 : Force fast processing in small frame 0 : Address 36h to 3Dh 1 : Fix WB frame to maximum.
[1 : 0] Select LPF of AWB I, Q. 00 : Avg. of 4 V 01 : Avg. of 2 V 1X : Non [7 : 0] R side multiplier of capture speed in AWB fast processing. [7 : 0] B side multiplier of capture speed in AWB fast processing. [7 : 0] Number of operations of white balance (each CMP_CT x VD timing) [7 : 0] Initial value of AWBHCL [7 : 0] Initial value of AWBLCL [7 : 0] Reference data in calculation of intercept level of AWB accumulated luminance [7 : 0] H peak ratio in calculation of intercept level of AWB accumulated luminance [7 : 0] Multiplier in calculation of intercept level of AWB accumulated luminance [7] AWB detected data 0 : I, Q 1 : R - Y, B - Y
2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h
K_WBR_H K_WBB_H CMP_CT AWB_HCL AWB_LCL REF_WBPK K_CL K_WBCL INT_I_R_Y CW_IQ
[6 : 0] Ratio of AWB weighted center and downward.
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LR38603
ADDRESS NAME 34h CWPA_IQ 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h CTLD_AW0 AWB_IP_L AWB_IM_L AWB_QP_L AWB_QM_L AWB_IP_S AWB_IM_S AWB_QP_S AWB_QM_S AWB_IW_L AWB_QW_L AWB_IW_S AWB_QW_S AWB_C_I AWB_C_Q WBR1 WBB1 WBR2 WBB2 WBR3 WBB3 REF_GA_R1M REF_GA_B1M REF_GA_R1P REF_GA_B1P REF_GA_R2M REF_GA_B2M REF_GA_R2P REF_GA_B2P REF_GA_R3M REF_GA_B3M
BIT CONTENTS [7 : 0] Position and area of AWB center. [7 : 0] Reset range of WB frame (compared with IRIS) [7 : 0] Outside, I-axis positive of AWB detect area (in fast processing) [7 : 0] Outside, I-axis negative of AWB detect area (in fast processing) [7 : 0] Outside, Q-axis positive of AWB detect area (in fast processing) [7 : 0] Outside, Q-axis negative of AWB detect area (in fast processing) [7 : 0] Inside, I-axis positive of AWB detect area (in normal processing) [7 : 0] Inside, I-axis negative of AWB detect area (in normal processing) [7 : 0] Inside, Q-axis positive of AWB detect area (in normal processing) [7 : 0] Inside, Q-axis negative of AWB detect area (in normal processing) [6 : 0] White area, I-axis, outside (for hysteresis). [6 : 0] White area, Q-axis, outside (for hysteresis). [7 : 4] White area, I-axis, inside (for targeted white area). [3 : 0] White area, Q-axis, inside (for targeted white area). [7 : 4] WB convergence orientation, I-axis coordinate (complement of 2) [3 : 0] WB convergence orientation, Q-axis coordinate (complement of 2) [7 : 0] WB1 R side constant (9 bits data which includes 0 at MSB) [7 : 0] WB1 B side constant (9 bits data which includes 0 at MSB) [7 : 0] WB2 R side constant (9 bits data which includes 0 at MSB) [7 : 0] WB2 B side constant (9 bits data which includes 0 at MSB) [7 : 0] WB3 R side constant (9 bits data which includes 0 at MSB) [7 : 0] WB3 B side constant (9 bits data which includes 0 at MSB) [7 : 0] Chrominance gain of R - Y negative direction when WB1 is fixed or autocontrolled (present WBR factor WBR1). [7 : 0] Chrominance gain of B - Y negative direction when WB1 is fixed or autocontrolled (present WBR factor WBR1). [7 : 0] Chrominance gain of R - Y positive direction when WB1 is fixed or autocontrolled (present WBR factor WBR1). [7 : 0] Chrominance gain of B - Y positive direction when WB1 is fixed or autocontrolled (present WBR factor WBR1). [7 : 0] Chrominance gain of R - Y negative direction when WB2 is fixed or autocontrolled (present WBR factor WBR2). [7 : 0] Chrominance gain of B - Y negative direction when WB2 is fixed or autocontrolled (present WBR factor WBR2). [7 : 0] Chrominance gain of R - Y positive direction when WB2 is fixed or autocontrolled (present WBR factor WBR2). [7 : 0] Chrominance gain of B - Y positive direction when WB2 is fixed or autocontrolled (present WBR factor WBR2). [7 : 0] Chrominance gain of R - Y negative direction when WB3 is fixed or autocontrolled (present WBR factor WBR3). [7 : 0] Chrominance gain of B - Y negative direction when WB3 is fixed or autocontrolled (present WBR factor WBR3).
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LR38603
ADDRESS NAME 52h REF_GA_R3P 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h REF_GA_B3P K_GA_R1M K_GA_B1M K_GA_R1P K_GA_B1P K_GA_R2M K_GA_B2M K_GA_R2P K_GA_B2P
BIT CONTENTS [7 : 0] Chrominance gain of R - Y positive direction when WB3 is fixed or autocontrolled (present WBR factor WBR3). [7 : 0] Chrominance gain of B - Y positive direction when WB3 is fixed or autocontrolled (present WBR factor WBR3). [6 : 0] Chrominance gain slope of R - Y negative direction in WB auto control (WBR1 < present WBR < WBR2) [6 : 0] Chrominance gain slope of B - Y negative direction in WB auto control (WBR1 < present WBR < WBR2) [6 : 0] Chrominance gain slope of R - Y positive direction in WB auto control (WBR1 < present WBR < WBR2) [6 : 0] Chrominance gain slope of B - Y positive direction in WB auto control (WBR1 < present WBR < WBR2) [6 : 0] Chrominance gain slope of R - Y negative direction in WB auto control (WBR2 < present WBR < WBR3) [6 : 0] Chrominance gain slope of B - Y negative direction in WB auto control (WBR2 < present WBR < WBR3) [6 : 0] Chrominance gain slope of R - Y positive direction in WB auto control (WBR2 < present WBR < WBR3) [6 : 0] Chrominance gain slope of B - Y positive direction in WB auto control (WBR2 < present WBR < WBR3)
REF_MAT_R1M [5 : 0] Matrix correction factor of R - Y negative direction when WB1 is fixed or autocontrolled (present WBR factor WBR1). REF_MAT_B1M [5 : 0] Matrix correction factor of B - Y negative direction when WB1 is fixed or autocontrolled (present WBR factor WBR1). REF_MAT_R1P [5 : 0] Matrix correction factor of R - Y positive direction when WB1 is fixed or REF_MAT_B1P autocontrolled (present WBR factor WBR1). [5 : 0] Matrix correction factor of B - Y positive direction when WB1 is fixed or
autocontrolled (present WBR factor WBR1). REF_MAT_R2M [5 : 0] Matrix correction factor of R - Y negative direction when WB2 is fixed or autocontrolled (present WBR factor = WBR2). REF_MAT_B2M [5 : 0] Matrix correction factor of B - Y negative direction when WB2 is fixed or autocontrolled (present WBR factor = WBR2). REF_MAT_R2P [5 : 0] Matrix correction factor of R - Y positive direction when WB2 is fixed or autocontrolled (present WBR factor = WBR2). REF_MAT_B2P [5 : 0] Matrix correction factor of B - Y positive direction when WB2 is fixed or autocontrolled (present WBR factor = WBR2). REF_MAT_R3M [5 : 0] Matrix correction factor of R - Y negative direction when WB3 is fixed or autocontrolled (present WBR factor = WBR3). REF_MAT_B3M [5 : 0] Matrix correction factor of B - Y negative direction when WB3 is fixed or autocontrolled (present WBR factor = WBR3). REF_MAT_R3P [5 : 0] Matrix correction factor of R - Y positive direction when WB3 is fixed or autocontrolled (present WBR factor = WBR3).
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LR38603
ADDRESS NAME 67h REF_MAT_B3P 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh K_MAT_R1M K_MAT_B1M K_MAT_R1P K_MAT_B1P K_MAT_R2M K_MAT_B2M K_MAT_R2P K_MAT_B2P CKIL_OFF COL_Y COL_S COL_H CKI_HCL CKI_LCL CKI_HLGA CKI_HLTI CKI_HECL CKI_EVCL CKI_EGA NSUP_R NSUP_B LC_ON_YL Y_GAM SEL_LPF_Y Y_SEL VAPT_OFF HAPT_OFF HAPT_SEL APT_HTIM APT_HGA
7Ch
BIT CONTENTS [5 : 0] Matrix correction factor of B - Y positive direction when WB3 is fixed or autocontrolled (present WBR factor = WBR3). [7 : 0] Matrix correction slope factor of R - Y negative direction in WB auto control (WBR1 < present WBR < WBR2) [7 : 0] Matrix correction slope factor of B - Y negative direction in WB auto control (WBR1 < present WBR < WBR2) [7 : 0] Matrix correction slope factor of R - Y positive direction in WB auto control (WBR1 < present WBR < WBR2) [7 : 0] Matrix correction slope factor of B - Y positive direction in WB auto control (WBR1 < present WBR < WBR2) [7 : 0] Matrix correction slope factor of R - Y negative direction in WB auto control (WBR2 < present WBR < WBR3) [7 : 0] Matrix correction slope factor of B - Y negative direction in WB auto control (WBR2 < present WBR < WBR3) [7 : 0] Matrix correction slope factor of R - Y positive direction in WB auto control (WBR2 < present WBR < WBR3) [7 : 0] Matrix correction slope factor of B - Y positive direction in WB auto control (WBR2 < present WBR < WBR3) [6] 1 : Color killer OFF [5 : 0] Start point of luminance color suppression in maximum PGA gain. [7 : 0] Start point of low luminance color suppression (PGA gain). [5 : 0] Low luminance color suppression gain. [7 : 0] Start level of high luminance color suppression. [7 : 0] Start level of low luminance color suppression. [7 : 4] High luminance color suppression gain. [3 : 0] Low luminance color suppression gain. [5 : 3] Timing adjustment of high luminance color suppression : -2 to +2 [2 : 0] Timing adjustment of low luminance color suppression : -2 to +2 [7 : 0] Start point of horizontal edge color suppression. [7 : 0] Start point of vertical edge color suppression. [7 : 4] Gain of horizontal edge color suppression. [3 : 0] Gain of vertical edge color suppression. [7 : 4] R - Y signal low level suppression [3 : 0] B - Y signal low level suppression [7] 1 : Execute measure against line crawl in processing luminance signal. [6 : 4] Select characteristics of luminance gamma. [3] Select characteristics of luminance LPF. [2] Switch luminance signal processing 0 : Use only 1H 1 : 3-line process [1] 1 : Vertical aperture is OFF [0] 1 : Horizontal aperture is OFF [7] Switch characteristics of horizontal aperture. 0 : (-1 + Z1) (1 - Z2) 1 : (-1 + Z1) (1 - Z1) [6 : 5] Timing of horizontal aperture : -1 to +1 [4 : 0] Initial value of APT_HGA (gain of horizontal edge signal)
12
LR38603
ADDRESS NAME 7Dh APT_HCL 7Eh 7Fh 80h 81h 82h 83h 84h APT_VGA APT_VCL APT_S APT_H APT_Y CKI_HCL2 CKI_ETI
BIT CONTENTS [6 : 0] Suppression level of horizontal edge signal. [4 : 0] Initial value of APT_VGA (gain of vertical edge signal) [6 : 0] Suppression level of vertical edge signal. [7 : 0] Start point of edge signal suppression (PGA gain). [5 : 0] Gain of edge signal suppression. [5 : 0] Start point of edge signal suppression in maximum PGA gained luminance. [7 : 0] Luminance suppression point of high luminance aperture. [6] Select level of edge signal, used in internal calculation. 1 : 1/4 times [5 : 3] Delete timing of horizontal edge : -2 to +2 [2 : 0] Delete timing of vertical edge : -2 to +2
85h 86h 87h 88h 89h 8Ah 8Bh
LC_K1 LC_K2 LC_MAX SETUP BAS_R BAS_B OUTGA
[7 : 0] Difference of 0H, 2H signal allowed level, for judgment of line crawl. [7 : 0] Difference of R, B signal allowed level, for judgment of line crawl. [7 : 0] Judgment of luminance level, for judgment of line crawl. [6] Switch CBLK level. [5 : 0] Adjustment of setup level (complement of 2). [7] Sign of burst level R - Y 1 : - direction 0 : + direction [6 : 0] Burst level R - Y. [7] Sign of burst level B - Y 1 : - direction 0 : + direction [6 : 0] Burst level B - Y (sign + absolute value). [6] 1 : Mute in encoder. [5] 1 : Stop adding SYNC to analog output. [4 : 0] Gain of analog output (1 time at 10h).
8Ch 8Dh 8Eh
SYNCLEV MUTE_OUT SEL_FH SEL_FR SEL_ADCK
[7 : 0] Adjustment of SYNC level. [7] 1 : Disable output mute at power-on. [6 : 0] Period of mute (MUTE_OUT x 2 vertical period) [7] [6] Switch attribute of FH Switch attribute of FR 1 : Inverted 1 : Inverted
[5 : 3] ADCK phase adjustment When using 270 k, 320 k-pixel CCDs 000 : standard to 101 : 300 (delayed from "000" to "101" every 60.) When using 410 k, 470 k-pixel CCDs 000 : standard to 101 : 270 (delayed from "000" to "101" every 45.)
SEL_FS 8Fh SEL_FH2 SEL_FCDS SEL_RS 90h STANDBY
[2 : 0] FS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from "000" to "111" every 2 ns.) [7 : 6] FH2 phase adjustment 00 : standard 01 : 1 ns delay 10 : 2 ns delay 11 : 3 ns delay [5 : 3] FCDS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from "000" to "111" every 2 ns.) [2 : 0] RS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from "000" to "111" every 2 ns.) [6] 1 : Standby [5 : 0] Period of return from standby (STANDBY x vertical period)
13
LR38603
ADDRESS NAME 91h KNEE INV_DCK2 INV_DCK1 BUSY_SEL EI_ON_SEL HRI_SEL VRI_SEL IN_VRES
BIT [7] [6] [5] [4] [3] [2] [1] [0]
CONTENTS 1 : Invert OBCP clock 1 : Invert DCK2 1 : Invert DCK1 1 : Reset auto control factor, when EEPSL is at H. 1 : Enable KEI pulse function. 1 : Invert HRES (minus attribute) 1 : Invert VRES (minus attribute) Select vertical reset timing. 0 : Reset at CSYNC pulse timing. 1 : Reset at VD pulse timing.
92h 93h
KEI_KEISU ENCIN_PH VARI_ENC
[7 : 0] Gain of PGA which produces KEI pulse. [3] Latch encoder clock inverted. [2] 1 : Enable DFF. [1 : 0] Delay adjustment of addition of luminance and color modulation. (Delay of color signal) 00 : 0 clock delay to 11 : 3 clocks delay (delayed from "00" to "11" every 1 clock .) 1 clock : Original clock
94h
ANA_VARI
[6 : 4] Delay adjustment of addition of luminance and color modulation. (Delay of luminance signal) 101 : -3 clocks delay to 011 : 3 clocks delay (delayed from "101" to "011" every 1 clock .) 1 clock : Pixel CK (complement of 2)
VARI_Y
[3 : 0] Timing adjustment of luminance processing. 1001 : -7 clocks delay to 0111 : 7 clocks delay (delayed from "1001" to "0111" every 1 clock.) 1 clock : Pixel CK (complement of 2)
95h
BUNSYU8_SEL TEST STDBY CHG_CKIL CHG_WB CHG_MTX CHG_CCD4 HG_YL_SEL
[7] [6] [5] [4] [3] [2] [1] [0]
Output 1/8 of original clock from DCK1. Test mode. Set 0 in normal operation. (The LR38603 does not read EEPROM and registers are set by serial data.) Make D/A converter standby. Swap R and B of color killer. Swap R and B of white balance. Swap R and B of matrix input. Swap U and V of digital output. Swap YL line selection for each R and B.
96h 97h 98h 99h 9Ah 9Bh 9Ch
REF_AW REF_BW REF_CW REF_DW REF_AB REF_BB REF_CB
[7 : 0] Factor for white detect correction [7 : 0] Factor for white detect correction [7 : 0] Factor for white detect correction [7 : 0] Factor for white detect correction [7 : 0] Factor for black detect correction [7 : 0] Factor for black detect correction [7 : 0] Factor for black detect correction
14
LR38603
ADDRESS NAME 9Dh REF_DB 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h C0h C1h C2h C3h C4h C5h AWNC_SEL APT_O_LIM WN00H WN00V WN00HV WN01H WN01V WN01HV WN02H WN02V WN02HV WN03H WN03V WN03HV WN04H WN04V WN04HV WN05H WN05V WN05HV WN06H WN06V WN06HV WN07H WN07V WN07HV TST_SEL31 TST_SEL32 TST_SEL33 TST_SEL1A TST_SEL1B TST_SEL1C
BIT CONTENTS [7 : 0] Factor for black detect correction [5 : 0] ON/OFF control signal for each condition. [7 : 0] Limiter of aperture output. [7 : 0] Lower bits of horizontal coordinate 1 of white defect. [7 : 0] Lower bits of vertical coordinate 1 of white defect. [3 : 0] [3 : 2] Upper bits of vertical coordinate 1 of white defect. [1 : 0] Upper bits of horizontal coordinate 1 of white defect. [7 : 0] Lower bits of horizontal coordinate 2 of white defect. [7 : 0] Lower bits of vertical coordinate 2 of white defect. [3 : 0] [3 : 2] Upper bits of vertical coordinate 2 of white defect. [1 : 0] Upper bits of horizontal coordinate 2 of white defect. [7 : 0] Lower bits of horizontal coordinate 3 of white defect. [7 : 0] Lower bits of vertical coordinate 3 of white defect. [3 : 0] [3 : 2] Upper bits of vertical coordinate 3 of white defect. [1 : 0] Upper bits of horizontal coordinate 3 of white defect. [7 : 0] Lower bits of horizontal coordinate 4 of white defect. [7 : 0] Lower bits of vertical coordinate 4 of white defect. [3 : 0] [3 : 2] Upper bits of vertical coordinate 4 of white defect. [1 : 0] Upper bits of horizontal coordinate 4 of white defect. [7 : 0] Lower bits of horizontal coordinate 5 of white defect. [7 : 0] Lower bits of vertical coordinate 5 of white defect. [3 : 0] [3 : 2] Upper bits of vertical coordinate 5 of white defect. [1 : 0] Upper bits of horizontal coordinate 5 of white defect. [7 : 0] Lower bits of horizontal coordinate 6 of white defect. [7 : 0] Lower bits of vertical coordinate 6 of white defect. [3 : 0] [3 : 2] Upper bits of vertical coordinate 6 of white defect. [1 : 0] Upper bits of horizontal coordinate 6 of white defect. [7 : 0] Lower bits of horizontal coordinate 7 of white defect. [7 : 0] Lower bits of vertical coordinate 7 of white defect. [3 : 0] [3 : 2] Upper bits of vertical coordinate 7 of white defect. [1 : 0] Upper bits of horizontal coordinate 7 of white defect. [7 : 0] Lower bits of horizontal coordinate 8 of white defect. [7 : 0] Lower bits of vertical coordinate 8 of white defect. [3 : 0] [3 : 2] Upper bits of vertical coordinate 8 of white defect. [1 : 0] Upper bits of horizontal coordinate 8 of white defect. [7 : 0] [7 : 0] [0] [7 : 0] [7 : 0] [7 : 0] Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h)
15
LR38603
ADDRESS NAME C6h TST_SEL1D C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h F0h F1h F2h F3h TST_SEL1V1 TST_SEL1V2 TST_SEL1V3 TST_SEL1V4 TST_C2_OB3 TST_C2_OB4 TST_C2_DL1 TST_C2_DL2
BIT [1 : 0] [7 : 0] [7 : 0] [7 : 0] [7 : 0] [6 : 0] [6 : 0] [7 : 0] [7 : 0]
CONTENTS Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h)
TST_C2_YL [5 : 0] TST_C2_GAMMA1 [7 : 0] TST_SSG_SEL [2] TST_C2_GAMMA2 [1 : 0] TST_C6_00 TST_C6_01 TST_C6_02 TST_C4_IO0 TST_C4_IO1 TST_C4_IO2 TST_C4_S0 TST_C4_S1 TST_C4_S2 TST_C5_T0 TST_C5_T1 TST_C5_T2 TST_SEL71 TST_SEL72 TEST_C8_00 TEST_C8_01 TEST_C8_02 TEST_C8_03 TEST_C8_04 TEST_C8_05 TEST_C8_06 TEST_C8_07 TEST_C8_08 TEST_C8_09 TST_REG1 TST_REG2 TST_REG3 TST_REG4 [7 : 0] [7 : 0] [6 : 0] [7 : 0] [4 : 0] [7 : 0] [7 : 0] [7 : 0] [0] [7 : 0] [7 : 0] [5 : 0] [7 : 0] [1 : 0] [7 : 0] [7 : 0] [7 : 0] [7 : 0] [7 : 0] [7 : 0] [7 : 0] [7 : 0] [7 : 0] [6 : 0] [7 : 0] [7 : 0] [7 : 0] [7 : 0]
16
LR38603
ADDRESS NAME F4h TST_REG5 F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh TST_REG6 TST_REG7 TST_REG8 TST_REG9 TST_REGA TST_REGB TST_SEL_REG WT_DAT30 WT_DAT31 TST_C5_WT3
BIT [7 : 0] [7 : 0] [5 : 0] [7 : 0] [7 : 0] [7 : 0] [7 : 0] [5 : 0] [7 : 0] [6 : 0] [5 : 0]
CONTENTS Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h) Test address (Set 00h)
17
LR38603
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage Input voltage Output voltage Storage temperature SYMBOL VDD VI VO TSTG RATING -0.3 to +4.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150 UNIT V V V C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Input voltage Output voltage Input clock SYMBOL VDD TOPR FCK MIN. 3.0 -20 TYP. 3.3 +25 28.6 MAX. 3.6 +70 UNIT V C MHz
ELECTRICAL CHARACTERISTICS 1
PARAMETER Input "High" voltage Input "Low" voltage Input "High" voltage Input "Low" voltage Hysteresis voltage Input "High" current Input "Low" current Input "High" current Input "Low" current Input "High" current Input "Low" current Input "High" current Input "Low" current Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage SYMBOL VIH VIL VIH VIL VHIS |IIH1| |IIL1| |IIH2| |IIL2| |IIH3| |IIL3| |IIH4| |IIL4| VOH1 VOL1 VOH3 VOL3 VOH4 VOL4 VIN = VDD VIN = 0 V VIN = VDD VIN = 0 V VIN = VDD VIN = 0 V VIN = VDD VIN = 0 V IOH = +4 mA IOL = -4 mA IOH = +12 mA IOL = -12 mA IOH = +2 mA IOL = -3 mA CONDITIONS
(VDD = 3.3 V10%, TA = -20 to +70C)
MIN. TYP. 0.8VDD 0.8VDD 0.2VDD 0.2 1.0 1.0 10 40 10 0.8VDD 0.2VDD 0.8VDD 0.2VDD 0.8VDD 0.2VDD 33 100 33 2.0 70 2.0 300 70 2.0 UNIT V 0.2VDD V V V V A A A A A A A A V V V V V V 3 4 5 6 7 8 9 MAX. NOTE 1
2
NOTES :
1. Applied to inputs/outputs (IO4MU, IO4MD) and inputs (IC, ICU, ICD, OSCI). 2. Applied to input (ICSU), input/output (IO4MSU). 3. Applied to input (IC, OSCI). 4. Applied to inputs (ICU, ICSU), input/output (IO4MSU). 5. Applied to input/output (IO4MU). 6. Applied to input (ICD), input/output (IO4MD). 7. Applied to inputs/outputs (IO4MU, IO4MD), output (OBF4M). 8. Applied to output (OBF12M). 9. Applied to output (OSCO).
18
LR38603
ELECTRICAL CHARACTERISTICS 2
PARAMETER Resolution Error of linearity Error of differential linearity Full scaled current Output impedance Reference voltage Reference resistance SYMBOL RES EL ED IFS ROUT VREF RREF CONDITIONS VREF = 1.0 V RREF = 4.8 k$ ROUT = 75 $
(VDD = 3.310%, TA = -20 to +70C)
MIN. TYP. 9 MAX. 5.0 1.0 13 75 1.0 4.8 UNIT Bit LSB LSB mA $ V k$ 2 3 NOTE
1
NOTES :
1. Applied to pin (VIDEO). 2. Applied to pin (VREF). 3. Applied to pin (IREF).
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LR38603
AUTOMATIC CAMERA FUNCTION CONTROL Automatic Electronic Exposure Control
Electronic shutter speed is controlled so that the exposure control data approach the data of REF_IRIS1 (address 06h). Under BLC mode, the data of REF_IRIS2 (address 09h) are available instead of REF_IRIS1. If the exposure control data are less than the data of CTLD_AGC (address 07h), an electronic shutter
speed is held. And then PGA gain is controlled so that the exposure control data will be less than the data of CTLD_0 (Address 08h). If the exposure control data are greater than the data of CTLD_AGC (address 07h), exposure control starts again.
Electronic Shutter Speed Setting
Electronic shutter speeds below can be selected by either hardware or coefficient data.
EEMDS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
EEMD1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
EEMD2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
EEMD3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1/60 s 1/100 s 1/250 s 1/500 s 1/1 000 s 1/2 000 s 1/5 000 s 1/10 000 s 1/20 000 s 1/50 000 s 1/100 000 s 1/30 s 1/15 s 1/7.5 s AUTO
ELECTRONIC SHUTTER SPEED NTSC PAL 1/50 s 1/120 s 1/250 s 1/500 s 1/1 000 s 1/2 000 s 1/5 000 s 1/10 000 s 1/20 000 s 1/50 000 s 1/100 000 s 1/25 s 1/12.5 s 1/6.25 s AUTO
1/60 s to MAX_SH (address 05h) 1/50 s to MAX_SH (address 05h) AUTO AUTO 1/60 s to 1/100 000 s 1/50 s to 1/100 000 s
A slower shutter speed of less than 1/60 s (1/50 s of PAL) can make images whose interval is every two fields, every four fields, etc. VD pulse is also converted to the same frequency as the output image rate.
Electronic exposure control data come from the following equation using averaged luminance levels of 64 areas in one image, made by DSP.
20
LR38603
Electronic exposure control data = [{Weighted data 1 q x (64 - CW_E (address 13h)) + Weighted data 2 w x CW_E}/64 x (256 - P_HEE (address 17h) - P_LEE (address 18h)) + Top level e x P_HEE + Bottom level r x P_LEE]/256
Y11 Y21 Y31 Y41 Y51 Y61 Y71 Y81 Y12 Y22 Y32 Y42 Y52 Y62 Y72 Y82 Y13 Y23 Y33 Y43 Y53 Y63 Y73 Y83 Y14 Y24 Y34 Y44 Y54 Y64 Y74 Y84 Y15 Y25 Y35 Y45 Y55 Y65 Y75 Y85 Y16 Y26 Y36 Y46 Y56 Y66 Y76 Y86 Y17 Y27 Y37 Y47 Y57 Y67 Y77 Y87 Y18 Y28 Y38 Y48 Y58 Y68 Y78 Y88
e Top level : The highest luminance data in one image by averaging either 4 pixels or 8 pixels in horizontal. r Bottom level : The lowest luminance data in one image by averaging either 4 pixels or 8 pixels in horizontal.
Auto White Balance Control
If white balance control data are less than the data of AWB_IW_S and AWB_QW_S (address 40h), then AWB stops. If white balance control data are less than the data of AWB_IW_L (address 3Eh) and AWB_QW_L (address 3Fh) AWB is made active so that white balance control data are less than the data of AWB_IW_S and AWB_QW_S. When the data are greater than AWB_IW_L and AWB_QW_L, AWB will be active again. White balance data come from the following equation using averaged I and Q data of 16 areas in one image.
I11 I21 I31 I41 Q11 Q21 Q31 Q41 I12 I22 I32 I42 Q12 Q22 Q32 Q42 I13 I23 I33 I43 Q13 Q23 Q33 Q43 I14 I24 I34 I44 Q14 Q24 Q34 Q44
q Weighted data 1 This comes from the following equation weighting in horizontal. Weighting factors are the data from UW_E1 (address 0Bh) to UW_E8 (address 12h). Weighted data 1 = {(Y11 + Y12 + + Y18)/8 x UW_E1 (address 0Bh) + (Y21 + Y22 + + Y28)/8 x UW_E2 (address 0Ch) : + (Y81 + Y82 + + Y88)/8 x UW_E8 (address 12h)}/256 The sum from UW_E1 to UW_E8 shall be 256. w Weighted data 2 Weighting area can be set by the data of CWP_E (address 14h), CWA_E (address 15h). Weighting position can be set by the data of CWP_E. Weighting area size can be set by the data of CWA_E. Weighted data come from averaged data in chosen area.
White balance data = {Weighted data 3 q x (64 - CW_IQ (address 33h)) + weighted data 4 w x CW_IQ}/64
21
LR38603
q Weighted data 3 I (or Q) data come from the following equation. Weighted data 3 = {(I11 + I12 + I13 + I14)/4 + (I21 + I22 + I23 + I24)/4 + + (I31 + I32 + I33 + I34)/4 + (I41 + I42 + I43 + I44)/4}/4 w Weighted data 4 Weighting area can be chosen by CWPA_IQ (address 34h). Weighted data come from averaged data in chosen area. e White balance area setting The sum of I and Q can be regulated by the luminance level and the color level. Setting available luminance level range : High level : AWB_HCL (address 2Eh) + [{K_CL (address 31h) x H peak level + (256 - K_CL) x Exposure control data}/256 - REF_WBPK (address 30h)] x K_WBCL (address 32h) Low level : AWB_LCL (address 2Fh) + [{K_CL (address 31h) x H peak level + (256 - K_CL) x Exposure control data}/256 - REF_WBPK (address 30h)] x K_WBCL (address 32h) Setting target zone : AWB_IP_L (address 36h), AWB_IM_L (address 37h) AWB_QP_L (address 38h), AWB_QM_L (address 39h) If white balance data are less than the data of AWB_IW_S and AWB_QW_S (address 40h) the target zone of auto white balance changes to the zone by the data below. Setting target zone : AWB_IP_S (address 3Ah), AWB_IM_S (address 3Bh) AWB_QP_S (address 3Ch), AWB_QM_S (address 3Dh)
Auto Color Matrix and Level Compensation
Color matrix compensation can be done by R - Y = R - Y(Data1 x B - Y) B - Y = B - Y(Data2 x R - Y) Color level compensation can be done by R - Y = R - Y x Data3 B - Y = B - Y x Data4 The above data come from the following equation along the variation of color temperature. MODE1 MODE2 MODE3 MODE4 MODE1 Data1 = Data2 = Data3 = Data4 = : : : : Present WBR factor < WBR1 WBR1 present WBR factor < WBR2 WBR2 present WBR factor < WBR3 WBR3 present WBR factor
and MODE_MAT (address 25h) = 0 REF_MAT_R1M (address 5Ch) REF_MAT_B1M (address 5Dh) REF_GA_R1M (address 48h) REF_GA_B1M (address 49h)
MODE1 and MODE_MAT = 1 Data1 = REF_MAT_R1M (address 5Ch) : B - Y < 0 REF_MAT_R1P (address 5Eh) : B - Y 0 Data2 = REF_MAT_B1M (address 5Dh) : R - Y < 0 REF_MAT_B1P (address 5Fh) : R - Y 0 Data3 = REF_GA_R1M (address 48h) : R - Y < 0 REF_GA_R1P (address 4Ah) : R - Y 0 Data4 = REF_GA_B1M (address 49h) : B - Y < 0 REF_GA_B1P (address 4Bh) : B - Y 0
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LR38603
MODE2 and MODE_MAT = 0 Data1 = REF_MAT_R1M + K_MAT_R1M (address 68h) x (WBR - WBR1)/32 Data2 = REF_MAT_B1M + K_MAT_B1M (address 69h) x (WBR - WBR1)/32 Data3 = REF_GA_R1M + K_GA_R1M (address 54h) x (WBR - WBR1)/32 Data4 = REF_GA_B1M + K_GA_B1M (address 55h) x (WBR - WBR1)/32 MODE2 and MODE_MAT = 1 Data1 = REF_MAT_R1M + K_MAT_R1M (address 68h) x (WBR - WBR1)/32 : B - Y < 0 REF_MAT_R1P + K_MAT_R1P (address 6Ah) x (WBR - WBR1)/32 : B - Y 0 Data2 = REF_MAT_B1M + K_MAT_B1M (address 69h) x (WBR - WBR1)/32 : R - Y < 0 REF_MAT_B1P + K_MAT_B1P (address 6Bh) x (WBR - WBR1)/32 : R - Y 0 Data3 = REF_GA_R1M + K_GA_R1M (address 54h) x (WBR - WBR1)/32 : R - Y < 0 REF_GA_R1P + K_GA_R1P (address 56h) x (WBR - WBR1)/32 : R - Y 0 Data4 = REF_GA_B1M + K_GA_B1M (address 55h) x (WBR - WBR1)/32 : B - Y < 0 REF_GA_B1P + K_GA_B1P (address 57h) x (WBR - WBR1)/32 : B - Y 0 MODE3 and MODE_MAT = 0 Data1 = REF_MAT_R2M (address 60h) + K_MAT_R2M (address 6Ch) x (WBR - WBR1)/32 Data2 = REF_MAT_B2M (address 61h) + K_MAT_B2M (address 6Dh) x (WBR - WBR1)/32 Data3 = REF_GA_R2M (address 4Ch) + K_GA_R2M (address 58h) x (WBR - WBR1)/32 Data4 = REF_GA_B2M (address 4Dh) + K_GA_B2M (address 59h) x (WBR - WBR1)/32 MODE3 and MODE_MAT = 1 Data1 = REF_MAT_R2M (address 60h) + K_MAT_R2M (address 6Ch) x (WBR - WBR1)/32 : B - Y < 0 REF_MAT_R2P (address 62h) + K_MAT_R2P (address 6Eh) x (WBR - WBR1)/32 : B - Y 0 Data2 = REF_MAT_B2M (address 61h) + K_MAT_B2M (address 6Dh) x (WBR - WBR1)/32 : R - Y < 0 REF_MAT_B2P (address 63h) + K_MAT_B2P (address 6Fh) x (WBR - WBR1)/32 : R - Y 0 Data3 = REF_GA_R2M (address 4Ch) + K_GA_R2M (address 58h) x (WBR - WBR1)/32 : R - Y < 0 REF_GA_R2P (address 4Eh) + K_GA_R2P (address 5Ah) x (WBR - WBR1)/32 : R - Y 0 Data4 = REF_GA_B2M (address 4Dh) + K_GA_B2M (address 59h) x (WBR - WBR1)/32 : B - Y < 0 REF_GA_B2P (address 4Fh) + K_GA_B2P (address 5Bh) x (WBR - WBR1)/32 : B - Y 0 MODE4 Data1 = Data2 = Data3 = Data4 = and MODE_MAT = 0 REF_MAT_R3M (address 64h) REF_MAT_B3M (address 65h) REF_GA_R3M (address 50h) REF_GA_B3M (address 51h)
MODE4 and MODE_MAT = 1 Data1 = REF_MAT_R3M (address 64h) : B - Y < 0 REF_MAT_R3P (address 66h) : B - Y 0 Data2 = REF_MAT_B3M (address 65h) : R - Y < 0 REF_MAT_B3P (address 67h) : R - Y 0 Data3 = REF_GA_R3M (address 50h) : R - Y < 0 REF_GA_R3P (address 52h) : R - Y 0 Data4 = REF_GA_B3M (address 51h) : B - Y < 0 REF_GA_B3P (address 53h) : B - Y 0
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LR38603
Color Level Suppression Under Lower Illumination
Working PGA gain can control both R - Y level and B - Y level by the following equation. R - Y (B - Y) level = {32 - (working PGA gain - COL_S (address 71h)) x COL_H (address 72h)}/32 When (working PGA gain - COL_S (address 71h)) 0, ( ) = 0.
Aperture Level Suppression Under Lower Illumination
Working PGA gain can control both the horizontal aperture level and the vertical aperture level by the following equation. Horizontal aperture level = APT_HGA (address 7Ch) x {32 - (working PGA gain - APT_S (address 80h)) x APT_H (address 81h)}/32 Vertical aperture level = APT_VGA (address 7Eh) x {32 - (working PGA gain - APT_S (address 80h)) x APT_H (address 81h)}/32 When (working PGA gain - APT_S (address 80h)) 0 , ( ) = 0.
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LR38603
Gamma Characteristic Option
* Luminance signal gamma option Y_GAM (address 7Bh) can choose one output of below 8 responses.
256
224
192 Output Level
160
128 000 001 010 011 100 101 110 111
96
64
32
0
0
64
128
192
256
320
384
448
512
576
640
704
768
832
896
960 1 024
Input Level
* Color signal gamma option C_GAM (address 24h) can choose one output from 8 responses below.
256
224
192 Output Level
160
128 000 001 010 011 100 101 110 111
96
64
32
0
0
64
128
192
256
320
384
448
512
576
640
704
768
832
896
960 1 024
Input Level
25
LR38603
PACKAGE OUTLINES 80 LQFP (P-LQFP080-1212)
0.08 P-0.5TYP. 60 61 80-0.20.08 (1.0) 41 40 M 0.1250.05 See Detail A
(Unit : mm)
12.00.2
14.00.3
80 1 (1.0) 12.00.2 14.00.3 20
21 (1.0) Detail A 0.125 (1.0) 0.64 1.70MAX. 0.10.1 1.40.2 0.64 0.64 1.40.2 1.7MAX 1.00.15
Package base plane
0.10
0-10 0.10.1 0.25
Seating plane
0.550.15
26

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