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Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHX3055E
FEATURES
* 'Trench' technology * Low on-state resistance * Fast switching * Isolated mounting tab
SYMBOL
d
QUICK REFERENCE DATA VDSS = 55 V ID = 9 A
g
RDS(ON) 150 m (VGS = 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode, field-effect power transistor in a plastic envelope with an electrically isolated mounting tab. The device uses 'trench' technology to achieve low on-state resistance. Applications:* d.c. to d.c. converters * switched mode power supplies The PHX3055E is supplied in the SOT186A (isolated TO220AB) conventional leaded package.
PINNING
PIN 1 2 3 tab gate drain source isolated DESCRIPTION
SOT186A
case
123
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 150C Tj = 25 C to 150C; RGS = 20 k Ths = 25 C Ths = 100 C Ths = 25 C Ths = 25 C MIN. - 55 MAX. 55 55 20 9 5.6 36 21 150 UNIT V V V A A A W C
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 C unless otherwise specified SYMBOL Visol PARAMETER R.M.S. isolation voltage from all three terminals to external heatsink CONDITIONS f = 50-60 Hz; sinusoidal waveform; R.H. 65% ; clean and dustfree MIN. TYP. MAX. 2500 UNIT V
Cisol
Capacitance from T2 to external f = 1 MHz heatsink
-
10
-
pF
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHX3055E
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Peak non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 3.3 A; tp = 220 s; Tj prior to avalanche = 25C; VDD 25 V; RGS = 50 ; VGS = 10 V; refer to fig:15 MIN. MAX. 25 UNIT mJ
IAS
-
9
A
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-hs Rth j-a Thermal resistance junction to heatsink Thermal resistance junction to ambient CONDITIONS TYP. 55 MAX. 6 UNIT K/W K/W
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance Forward transconductance Gate source leakage current Zero gate voltage drain current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 150C Tj = -55C VGS = 10 V; ID = 5.5 A Tj = 150C VDS = 25 V; ID = 5.5 A VGS = 10 V; VDS = 0 V VDS = 55 V; VGS = 0 V; Tj = 150C ID = 10 A; VDD = 44 V; VGS = 10 V MIN. 55 50 2.0 1.1 1.5 TYP. MAX. UNIT 3.0 120 210 3.2 10 0.05 5.8 1.5 3.2 3 26 8 10 4.5 7.5 190 55 40 4.0 6 150 263 100 10 100 10 35 15 20 250 80 50 V V V V V m m S nA A A nC nC nC ns ns ns ns nH nH pF pF pF
VDD = 30 V; RD = 2.7 ; RG = 5.6 ; VGS = 10 V Resistive load Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHX3055E
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 10 A; VGS = 0 V IF = 10 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 30 V TYP. MAX. UNIT 1.1 32 50 9 36 1.5 A A V ns nC
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHX3055E
Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 Heatsink temperature, Ths (C) 125 150
10
Transient thermal impedance, Zth j-hs (K/W)
D = 0.5
0.2 1 0.1 0.05 0.02 single pulse 0.1 1E-06 T 1E-03 1E-02 1E-01 1E+00 1E+01 P D tp D = tp/T
1E-05
1E-04
Pulse width, tp (s)
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Ths)
Fig.4. Transient thermal impedance. Zth j-hs = f(t); parameter D = tp/T
Drain Current, ID (A) Tj = 25 C VGS = 10V 8V 7V 6.5 V 6V 5.5 V 5V 4.5 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2
Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 Heatsink temperature, Ths (C) 125 150
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Ths); conditions: VGS 10 V
Peak Pulsed Drain Current, IDM (A)
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS)
100
0.5 RDS(on) = VDS/ ID tp = 10 us 0.45 0.4 10 0.35 0.3 100 us 1 D.C. 100 ms 1 ms 10 ms 0.25 0.2 0.15 0.1 0.05 0.1 1 10 Drain-Source Voltage, VDS (V) 100 0
Drain-Source On Resistance, RDS(on) (Ohms) 5V 5.5V 6V Tj = 25 C
6.5 V 7V 8V VGS = 10V
0
1
2
3 4 5 6 Drain Current, ID (A)
7
8
9
10
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID)
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHX3055E
Drain current, ID (A) 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 Gate-source voltage, VGS (V) Tj = 25 C VDS > ID X RDS(ON)
4.5 4 3.5 3 2.5 2 1.5
175 C
Threshold Voltage, VGS(TO) (V) maximum typical
minimum
1 0.5 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics. ID = f(VGS)
Transconductance, gfs (S) VDS > ID X RDS(ON) 3.5 3 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 Drain current, ID (A) 7 8 9 10 175 C Tj = 25 C
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Drain current, ID (A)
4
1.0E-01
1.0E-02 minimum typical 1.0E-04 maximum 1.0E-05
1.0E-03
1.0E-06 0 0.5 1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V) 4 4.5 5
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID)
Normalised On-state Resistance 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
1000
Capacitances, Ciss, Coss, Crss (pF)
Ciss
100 Coss
Crss 10 0.1 1 10 Drain-Source Voltage, VDS (V) 100
Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHX3055E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Gate-source voltage, VGS (V) ID = 10A Tj = 25 C VDD = 11 V 10 100
Maximum Avalanche Current, IAS (A)
VDD = 44 V
25 C
1 Tj prior to avalanche = 125 C
0
1
2
3 4 5 Gate charge, QG (nC)
6
7
8
0.1 0.001
0.01
0.1 Avalanche time, tAV (ms)
1
10
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG)
Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load
Source-Drain Diode Current, IF (A) 10 9 8 7 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) Tj = 25 C 175 C VGS = 0 V
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHX3055E
MECHANICAL DATA
Dimensions in mm Net Mass: 2 g
Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 SOT186A
E P q D1 T
A A1
D
j L2 b1 L b2 L1 K Q
1
2
b e e1
3
wM c
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.6 4.0 A1 2.9 2.5 b 0.9 0.7 b1 1.1 0.9 b2 1.4 1.2 c 0.7 0.4 D 15.8 15.2 D1 6.5 6.3 E 10.3 9.7 e 2.54 e1 5.08 j 2.7 2.3 K 0.6 0.4 L L1 L2 max. 3
(1)
P 3.2 3.0
Q 2.6 2.3
q 3.0 2.6
T
(2)
w 0.4
14.4 3.30 13.5 2.79
2.5
Notes 1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned. 2. Both recesses are 2.5 x 0.8 max. depth OUTLINE VERSION SOT186A REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11
Fig.16. SOT186A; The seating plane is electrically isolated from all terminals.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8".
August 1999
7
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHX3055E
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1999
8
Rev 1.000

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