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INTEGRATED CIRCUITS
DATA SHEET
TDA8755 YUV 8-bit video low-power analog-to-digital interface
Product specification Supersedes data of June 1994 File under Integrated Circuits, IC02 1995 Mar 09
Philips Semiconductors
Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
FEATURES * 8-bit resolution * Sampling rate up to 20 MHz * TTL compatible digital inputs * 3-state TTL outputs * U, V two's complement outputs * Y binary output * Power dissipation of 550 mW (typical) * Low analog input capacitance, no buffer amplifier required * High signal-to-noise ratio over a large analog input frequency range * Track-and-hold included * Clamp functions included * UV multiplexed ADC * 4 : 1 : 1 output data encoder * Stable voltage regulator included. QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO INL DNL EB fclk(max) Ptot PARAMETER analog supply voltage digital supply voltage output stages supply voltage analog supply current digital supply current output stages supply current DC integral non-linearity DC differential non-linearity effective bits maximum clock frequency total power dissipation fclk = 2 MHz fclk = 2 MHz CONDITIONS MIN. 4.75 4.75 4.75 - - - - - - 20 - TYP. 5.0 5.0 5.0 46 55 9 0.4 0.3 7.1 - 550 GENERAL DESCRIPTION APPLICATIONS
TDA8755
* High speed analog-to-digital conversion for video signal digitizing * 100 Hz improved definition TV (IDTV).
The TDA8755 is a bipolar 8-bit video low-power analog-to-digital conversion (ADC) interface for YUV signals. The device converts the YUV analog input signal into 8-bit coded digital words in a 4 : 1 : 1 format at a sampling rate of 20 MHz. The U/V signals are converted in a multiplexed manner. All analog signal inputs are digitally clamped and a fast precharge is provided for start-up. All digital inputs and outputs are TTL compatible. Frame synchronization is supported in a multiplexed manner.
MAX. 5.25 5.25 5.25 55 66 12 1 0.5 - - 700 V V V
UNIT
mA mA mA LSB LSB bits MHz mW
ORDERING INFORMATION PACKAGE TYPE NUMBER PINS TDA8755T 32 PIN POSITION SO32L MATERIAL plastic CODE SOT287-1
1995 Mar 09
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Product specification
TDA8755
Fig.1 Block diagram.
handbook, full pagewidth
1995 Mar 09
AGND 10 18 8 1 2 4 13 DGND SDN n.c. REG1 REG2 REG3 23
BLOCK DIAGRAM
Philips Semiconductors
VCCA
VCCD
VCCO
6
32
SUPPLY AND REFERENCE VOLTAGE REGULATOR
INY CLAMP Y TRACK AND HOLD 8 24 31 8 8-BIT ADC 8-BIT PIPELINE TTL I/O
3 8 D0 D7
YUV 8-bit video low-power analog-to-digital interface
CLPY
5
Y
CLP
15 COMPARATOR 16
CLAMP LOGIC
3
TIMING GENERATOR TRACK AND HOLD ANALOG MULTIPLEXER TRACK AND HOLD 8-BIT ADC 8 U AND V DATA ENCODER TRACK AND HOLD COMPARATOR 128
16 14 17
INU
7
HREF CE CLK
CLPU
11
CLAMP U
CLPV
12
DIGITAL MULTIPLEXER
TTL I/O
19 20 21 22
2 D'0 D'1 2 D'2 D'3
V U
CLAMP V
INV
9
TDA8755
MLA734 - 1
Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
PINNING SYMBOL n.c. REG1 INY REG2 CLPY VCCA INU SDN INV AGND CLPU CLPV REG3 CE CLP HREF CLK DGND D'0 D'1 D'2 D'3 VCCO D0 D1 D2 D3 D4 D5 D6 D7 VCCD PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DESCRIPTION not connected decoupling input (internal stabilization loop decoupling) Y analog voltage input decoupling input (internal stabilization loop decoupling) Y clamp capacitor connection analog positive supply voltage (+5 V) U analog voltage input stabilizer decoupling node and analog reference voltage (+3.35 V) V analog voltage input analog ground U clamp capacitor connection V clamp capacitor connection decoupling input (internal stabilization loop decoupling) chip enable input (TTL level input active LOW) clamp control input horizontal reference signal clock input digital ground V data output; bit 0 (n-1) V data output; bit 1 (n) U data output; bit 0 (n-1) U data output; bit 1 (n) positive supply voltage for output stages (+5 V) Y data output; bit 0 (LSB) Y data output; bit 1 Y data output; bit 2 Y data output; bit 3 Y data output; bit 4 Y data output; bit 5 Y data output; bit 6 Y data output; bit 7 (MSB) digital positive supply voltage (+5 V) Fig.2 Pin configuration.
CE 14 CLP 15 HREF 16
MLA728 - 1
TDA8755
handbook, halfpage
n.c. REG1 INY REG2 CLPY VCCA INU SDN INV
1 2 3 4 5 6 7 8 TDA8755 9
32 VCCD 31 D7 30 D6 29 D5 28 D4 27 D3 26 D2 25 D1 24 D0 23 V CCO 22 D'3 21 D'2 20 D'1 19 D'0
AGND 10 CLPU 11
CLPV 12 REG3 13
18 DGND 17 CLK
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage output stages supply voltage supply voltage difference between VCCA and VCCD supply voltage difference between VCCO and VCCD supply voltage difference between VCCA and VCCO VI Vclk(p-p) IO Tstg Tamb Tj HANDLING input voltage AC input voltage for switching (peak-to-peak value) output current storage temperature operating ambient temperature junction temperature referenced to AGND referenced to DGND CONDITIONS MIN. -0.3 -0.3 -0.3 -1.0 -1.0 -1.0 - - - -55 0 -
TDA8755
MAX. +7.0 +7.0 +7.0 +1.0 +1.0 +1.0 +5.0 VCCD +6 +150 +70 +150
UNIT V V V V V V V V mA C C C
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 70 UNIT K/W
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
TDA8755
CHARACTERISTICS VCCA = V6 to V10 = 4.75 to 5.25 V; VCCD = V32 to V18 = 4.75 to 5.25 V; VCCO = V23 to V18 = 4.75 to 5.25 V; AGND and DGND shorted together; VCCA to VCCD = -0.25 to +0.25 V; VCCO to VCCD = -0.25 to +0.25 V; VCCA to VCCO = -0.25 to +0.25 V; Tamb = 0 to +70 C; typical values measured at VCCA = VCCD = VCCO = 5 V and Tamb = 25 C; unless otherwise specified. SYMBOL Supply VCCA VCCD VCCO ICCA ICCD ICCO Inputs CLK (PIN 17) VIL VIH IIL IIH ZI CI VIL VIH IIL IIH CLPY (PIN 5) V5 I5 V11, 12 I11, 12 INY (PIN 3) VI(p-p) ZI CI input voltage, full range (peak-to-peak value) input impedance input capacitance fi = 4.43 MHz fi = 6 MHz fi = 6 MHz 0.93 - - 1.0 30 1 1.07 - - V k pF clamp voltage for 16 output code clamp output current - - - - 3.725 50 3.30 50 - - - - V A V A LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current input impedance input capacitance Vclk = 0.4 V Vclk = 2.7 V fclk = 20 MHz fclk = 20 MHz 0 2.0 -400 - - - 0 2.0 Vclk = 0.4 V Vclk = 2.7 V -400 - - - - - 4 4.5 - - - - 0.8 VCCD - 100 - - 0.8 VCCD - 100 V V A A k pF analog supply voltage digital supply voltage output stages supply voltage analog supply current digital supply current output stages supply current 4.75 4.75 4.75 - - - 5.0 5.0 5.0 46 55 9 5.25 5.25 5.25 55 66 12 V V V mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
CE, CLP AND HREF (PINS 14 TO 16) LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current V V A A
CLPU AND CLPV (PINS 11 AND 12) clamp voltage for 128 output code clamp output current
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8755
MAX.
UNIT
INU AND INV (PINS 7 AND 9) VI(p-p) ZI CI ct Outputs SDN (PIN 8) Vref VREG IL VOL VOH IOZ fclk(max) fclk(min) tCPH tCPL reference voltage line regulation load current 4.75 V VCCA 5.25 V - - -2 IO = 0.4 mA IO = 1.5 mA HIGH level output voltage output current in 3-state mode IO = -0.4 mA 0.4 V < VO < VCCD 0 0 2.4 -20 3.32 4.0 - - - - - - - - - - - - 0.4 0.5 VCCD +20 - 2.0 - - - - 0 - - - 1.0 0.5 2.0 - V mV mA input voltage, full range (peak-to-peak value) input impedance input capacitance fi = 1.5 MHz fi = 2 MHz fi = 2 MHz 0.93 - - - 1.03 30 1 -55 1.13 - - -50 V k pF
INPUTS ISOLATION crosstalk between Y, U and V dB
DIGITAL OUTPUTS D0 TO D7 AND D'0 TO D'3 (PINS 24 TO 31 AND 19 TO 22) LOW level output voltage V V V A
Switching characteristics maximum clock frequency minimum clock frequency clock pulse width HIGH clock pulse width LOW 20 - 20 20 - - - - - - - - - - MHz MHz ns ns
Analog signal processing (fclk = 20 MHz; 50% clock duty factor) Gdiff diff f1 fall SVRR1 SVRR2 differential gain differential phase harmonics (full-scale), all components supply voltage ripple rejection 1 supply voltage ripple rejection 2 note 1; see Fig.8 note 1; see Fig.8 note 2; see Fig.10 note 3 note 3 2 3 - -54 -40 1.0 0.4 0.3 1.0 7.1 % deg dB dB dB %/V
fundamental harmonics (full-scale) note 2
Transfer function (50% clock duty factor) INL DNL AILE EB DC integral non-linearity DC differential non-linearity AC integral non-linearity effective bits fclk = 2 MHz fclk = 2 MHz note 4 note 5; Fig.10 LSB LSB LSB bits
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8755
MAX.
UNIT
Timing (fclk = 20 MHz); note 6; see Figs 3 to 7 tds th td tdZH tdZL tdHZ tdLZ tr tf tsu th tr tf tCLP Notes 1. Low frequency ramp signal (VI(p-p) = full-scale and 64 s period) combined with a sinewave input voltage (VI(p-p) = 0.25 full-scale, fi = maximum permitted frequency) at the input. 2. The input conditions are related as follows: a) Y channel: VI(p-p) = 1.0 V; fi = 4.43 MHz b) U/V channel: VI(p-p) = 1.0 V; fi = 1.5 MHz. 3. Supply voltage ripple rejection: a) SVRR1 is the variation of the input voltage producing output code 127 (code 15) for supply voltage variation of 0.5 V: V I ( 127 ) SVRR1 = 20 log --------------------V CCA b) SVRR2 is the relative variation of the full-scale range of analog input for a supply voltage variation of 0.5 V: ( V I ( 0 ) - V I ( 255 ) ) 1 SVVR2 = ------------------------------------------------ x ----------------V I ( 0 ) - V I ( 255 ) V CCA 4. Full-scale sinewave (fi = 4.43 MHz for Y and fi = 1.5 MHz for U and V; fclk = 20 MHz). 5. The number of effective bits is measured using a 20 MHz clock frequency. This value is given for a 4.43 MHz input frequency on the Y channel (1.5 MHz on the U and V channels). This value is obtained via a Fast Fourier Transform (FFT) treatment taking 4 x Tclk (clock periods) acquisition points per period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB x 6.02 + 1.76 dB. 6. Output data acquisition is available after the maximum delay time of td. 7. U and V output data is not valid during tCLP. sampling delay time output hold time output delay time 3-state output delay time 3-state output delay time 3-state output delay time 3-state output delay time clock rise time clock fall time HREF set-up time HREF hold time data output rise time data output fall time minimum time for active clamp note 7; see Fig.9 enable-to-HIGH enable-to-LOW disable-to-HIGH disable-to-LOW - 7 - - - - - 3 3 7 3 - - 3 1 - 33 10 10 8 4 5 5 - - 12 16 - - - 42 14 14 11 6 - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns s
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
Table 1 Mode selection CE 1 0 Table 2 Output data coding OUTPUT PORT Y BIT D7 D6 D5 D4 D3 D2 D1 D0 U V D'3 D'2 D'1 D'0 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 OUTPUT DATA Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 D7 TO D0; D'3 TO D'0 high impedance active; binary
TDA8755
Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U 01 U 00 V01 V00
t CPH
andbook, full pagewidth
t CPL
CLK
1.4 V
sample N
sample N 1
sample N 2
sample N 3
sample N 4
sample N 5
V
l th t ds 2.4 V
D0 to D7
DATA N4
DATA N3
DATA N2
DATA N1 td
DATA N
DATA N1
MSA646
1.4 V 0.4 V
Fig.3 Timing diagram (INY signal).
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
TDA8755
andbook, full pagewidth
V CCD CE 50 %
t dHZ HIGH 90 % output data t dLZ HIGH output data LOW 10 % 50 % t dZL LOW
t dZH
50 %
TEST tdLZ
V CCD 3.3 k
S1 VCCD VCCD GND GND
tdZL tdHZ tdZH
MBD874
TDA8755 15 pF CE
S1
fCE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
handbook, halfpage
TDA8755
D0 to D7 15 pF test probe TEK P6201
MLA733 - 1
Fig.5
Load circuit for the 3-state output timing measurement.
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
TDA8755
handbook, full pagewidth
CLK
sample N
sample N 4
1
2
3
4
5
HREF t su output data N4 N3 N2 N1 N sample N output data valid th
MLA732 - 1
The output data is valid 4 clock periods after HREF goes HIGH.
Fig.6 Timing definition for set-up and hold times (HREF signal).
4 clock periods (Tclk )
handbook, full pagewidth
sample N
sample N 4 x T clk
CLK
HREF sample N 4 (Tclk 1) output data valid output data N4 N3 N3
MLA731 - 1
When the HREF period is a multiple of 4 clock periods, the output data is valid without any clock delay. The internal circuit always gives an internal delay of 4 clock periods as illustrated in Fig.6.
Fig.7 Timing diagram (HREF signal).
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
TDA8755
handbook, full pagewidth
0.3 V
Y, U and V channel 1.2 V
0.3 V
64 s
MSA644
Y channel = 4.43 MHz sinewave. U, V channel = 1.5 MHz sinewave.
Fig.8 Input test signal for differential gain and phase measurements.
handbook, full pagewidthdigital
output level
MSA645
255
black-level clamping Y : 16 U,V : 128 0 time CLP t CLP
Fig.9 Clamping control timing.
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
TDA8755
handbook, full pagewidth
0
MBD873
amplitude (dB) 20
40
60
80
100
120 0 1.25 2.50 3.75 5.00 6.25 7.50 8.75 f (MHz) 10.00
Effective bits: 7.30; THD = -53.35 dB. Harmonic levels (dB): 2nd = -58.38; 3rd = -60.03; 4th = -57.30; 5th = -69.38; 6th = -67.09.
Fig.10 Fast Fourier Transform (fclk = 20 MHz; fi = 4.43 MHz).
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
APPLICATION INFORMATION
TDA8755
andbook, full pagewidth
n.c. 10 nF AGND
1
32
VCCD 10 nF
5V
REG1
2
31
D7 DGND
INY
(3)
3
30 29
D6
4.7 F REG2 220 nF 4 D5
AGND
AGND
CLPY
(1)
5 6
28 27
D4
5V 10 nF
VCCA
D3
INU
(3)
7
26
D2
4.7 F SDN 8 25 D1
+ 3.35 V
(2)
10 nF INV
(3)
TDA8755
9 10 24 23 D0 VCCO 10 nF 4.7 F AGND
5V
AGND
CLPU
(1)
11
22
D'3 DGND
AGND
(1)
CLPV
12 13
21 20
D'2
AGND 220 nF
REG3
D'1
CE
14
19
D'0
CLP
15
18
DGND
HREF
16
17
MLA735 - 1
CLK
The analog and digital supplies should be separated and decoupled. (1) Clamp capacitors must be determined in accordance with the application; recommended values are CLPY = 18 nF, CLPU and CLPV = 33 nF. (2) It is possible to use the reference output voltage pin SDN to drive other analog circuits under the limits indicated in Chapter "Characteristics". (3) Input signal pins have a high bandwidth. It is necessary to take special care on PCB layout to avoid any interaction from other signals (digital clocks for example).
Fig.11 Application diagram.
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
TDA8755
andbook, full pagewidth Y
12 U
VDRAM 1 x TMS4C2970
12
SAA4940 NOISE REDUCTION INCLUDING CROSS-COLOUR REDUCTION
12
SAA7158
Y
TDA8755 VDRAM 1 x TMS4C2970 12
U 12 VIDEO ENHANCEMENT, LFR PROCESSING V AND DACs 2
to video processor
V
2 12 12/13.5/16/18 MHz VCO1 VSYNC SC1 data 8 2 VCO2B C bus
MSA642
control
32/36 MHz VCO2A
MEMORY CONTROLLER SAA4951
H2, V2 (32 kHz/100 Hz) 27 MHz
to deflection processor
control I2 C
2
MICROCONTROLLER PCB83C652
Fig.12 Block diagram of a full-options Improved Picture Quality (IPQ) module.
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
TDA8755
andbook, full pagewidth Y
U
TDA8755
12
VDRAM 1x TMS4C2970
12
VIDEO ENHANCEMENT AND DACs
Y
U
to video processor
V
SAA7165
V
2 I C bus 12/13.5/16/18 MHz VCO1 VSYNC SC1 data 8 VCO2B control 32/36 MHz VCO2A
2
MEMORY CONTROLLER SAA4951
H2, V2 (32 kHz/100 Hz) 27 MHz
to deflection processor
control I2 C
2
MSA643
MICROCONTROLLER PCB83C652
Fig.13 Block diagram of an economic Improved Picture Quality (IPQ) module.
1995 Mar 09
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
PACKAGE OUTLINE
handbook, full pagewidth SO32: plastic small outline package; 32 leads; body width 7.5 mm
TDA8755
SOT287-1
D
E
A X
c y HE vM A
Z 32 17
Q A2 A1 pin 1 index Lp 1 e bp 16 wM L detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 0.02 0.01 c 0.27 0.18 0.011 0.007 D (1) 20.7 20.3 0.81 0.80 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.42 0.39 L 1.4 0.055 Lp 1.1 0.4 0.043 0.016 Q 1.2 1.0 0.047 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.95 0.55 0.037 0.022
0.012 0.096 0.004 0.086
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-25
1995 Mar 09
17
Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
SOLDERING Plastic small outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8755
Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Product specification
YUV 8-bit video low-power analog-to-digital interface
NOTES
TDA8755
1995 Mar 09
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Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., 15/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)480 6960/480 6009 India: Philips INDIA Ltd, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)282 6707 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD38 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
533061/30/03/pp20 Document order number: Date of release: 1995 Mar 09 9397 750 00027
Philips Semiconductors

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