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KS0108B
INTRODUCTION
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
100 QFP
The KS0108B is a LCD driver LSl with 64 channel output for dot matrix liquid crystal graphic display system. This device consists of the display RAM, 64 bit data latch 64 bit drivers and decoder logics. It has the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix Iiquid crystal driving signals corresponding to stored data.The KS0108B composed of the liquid crystal display system in combination with the KS0107B (64 common driver)
FEATURES
* Dot matrix LCD segment driver with 64 channel output * Input and Output signal - Input: 8 bit parallel display data Control signal from MPU Splitted bias voltage (V1R, V1L, V2R, V2L, V3R. V3L, V4R, V4L) - Output: 64 channel waveform for LCD driving. * Display data is stored in display data RAM from MPU. * Interface RAM - Capacity: 512 bytes (4096 bits) - RAM bit data: RAM bit data = 1:ON RAM bit data- = 0:OFF * Applicable LCD duty: 1/32~1/64 * LCD driving voltage: 8V~17V(V -VEE) DD * Power supply voltage: + 5V 10% Driver COMMON KS0107B SEGMENT Other KS0108B Controller MPU
* High voltage CMOS process. * 100QFP and bare chip available.
KS0108B
BLOCK DIAGRAM
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
DB<0:7>
CLK1 CLK2
CS1B CS2B INPUT REGISTER OUTPUT REGISTER CS3 I/O BUFFER R/W RS E 8 8 RSTB
DISPLAY ON/OFF 1
BUSY
INSTRUCTION DECODER
6 3 Y-COUNTER 6 X-DECODER Y-DECODER 6 64 DISPLAY START LINE REGISTER 8 ADC
CL
PAGE SELECTOR
Z DECODER
6
64 DISPLAY DATA RAM 5128=4096 bits
8
FRM
64
DATA LATCH
64 V0L V2L V3L V5L M LCD DRIVER V0R V2R V3R V5R
S64
S63
S2
S1
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
Fig.2. 100QFP Top
V EE1 DB1 DB0 V3L V2L V5L V0L S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DB2 81 DB3 82 DB4 83 DB5 84 DB6 85 DB7 86 NC NC NC CS3 90 CS2B 91 92 93 CS1B RSTB R/W 94 RS CL CLK2 97 CLK1 98 E 99 96 95 89 88 87 S22 V SS S1 S2 S3 S4 S5 S6 S7 S8 S9 50 49 48 47 46 45 44 43 42 41 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32
KS0108B
40 39 38 37 36 35 34 33 32 31
S33 S34 S35 S36 S37 S38 S39 S40 S41 S42
KS0108B
FRM 100
1 ADC
2 M
3 V DD
4 V3R
5 V2R
6 V5R
7 V0R
8 V EE2
9 S64
10 S63
11 S62
12 S61
13 S60
14 S59
15 S58
16 S57
17 S56
18 S55
19 S54
20 S53
21 S52
22 S51
23 S50
24 S49
25 S48
26 S47
27 S46
28 S45
29 S44
30 S43
View
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCIPTION
PIN (NO) 3 78 73, 8 SYMBOL VDD VSS VEE1.2 INPUT/OUTPUT DESCRIPTION Power For internal logic circuit (+5V10%) GND (0V) For LCD driver circuit VSS=0V, VDD=5V3/410% VDD-VEE=8V~17V VEE1 and VEE2 is connected by the same voltage. Power Bias supply voltage terminals to drive the LCD. Select Level V0L(R), V5L(R) Input Non-Select Level V2L(R), V3L(R)
74, 7 76, 5 77, 4 75, 6 92 91 90 2 1
V0L, V0R V2L, V2R V3L, V3R V5L, V5R CS1B CS2B CS3 M ADC
Input Input
100
FRM
Input
99
E
Input
98 97 96
CLK1 CLK2 CL
Input
Input
95
RS
Input
94
R/W
Input
79~86
DB0~DB7
Input/Output
Chip selection In order to interface data for input or output The terminals have to be CS1B=L, CS2B=L, and CS3=H. Alternating signal input for LCD driving. Address control signal of Y address counter. ADC=HDB<0:7>=0Y0S1 DB<0:7>=63Y63S64 ADC=LDB<0:7>=0Y63S64 DB<0:7>=63Y0S1 Synchronous control signal. Presets the 6-bit Z counter and syncronizes the common signal with the frame signal when the frame signal becomes high. Enable signal. write mode (R/W=L) data of DB<0:7> is latched at the falling edge of E. read mode (R/W=H) DB<0:7> appears the reading data while E is at high level. 2 phase clock signal for internal operation. Used to execute operations for input/output of display RAM data and others. Display synchronous signal. Display data is latched at rising time of the CL signal and increments the Z-address counter at the CL falling time. Data or Instruction. RS=HDB<0:7> : Display RAM Data RS=LDB<0:7> : Instruction Data Read or Write. R/W=H Data appears at DB<0:7> and can be read by the CPU while E=H, CS1B=L, CS2B=L and CS3=H. R/W=LaeDisplay data DB<0:7> can be written at falling of E when CS1B=L, CS2B=L and CS3=H. Data bus. There state I/O common terminal.
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCRIPTION (continued)
PIN (NO) 72~9 NAME S1~S64 INPUT/OUTPUT DESCRIPTION Output LCD Segment driver output. Display RAM data 1:ON Display RAM data 0:OFF (Relation of display RAM data & M) M L H 93 RSTB Input DATA L H L H Output Level V2 V0 V3 V5
87~89
NC
Reset signal. When RSTB=L, (1) ON/OFF register becomes set by 0. (display off) (2) Display start line register becomes set by 0 (Z-address 0 set, display from line 0) After releasing reset, this condition can be changed only by instruction. No connection.(open)
MAXIMUM ABSOLUTE LIMIT
Characteristic Operating Voltage Supply Voltage Driver Supply Voltage Symbol VDD VEE VB VLCD T OPR T STG Value -0.3~+7.0 VDD-19.0~VDD+0.3 -0.3~VDD+0.3 VEE-0.3~VDD+0.3 -30~+85 -55~+125 Unit V V V V C C Note *1 *4 *1,3 *2
Operating Temperature Storage Temperature *1. Based on VSS=0V. *2. Applies the same supply voltage to V and VEE2. VLCD=VDD-VEE. EE1 *3. Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and DB0~DB7. *4. Applies V0L(R), V2L(R), V3L(R) and V5L(R). Voltage level: VDDV0L=VORV2L=V2RV3L=V3RV5L=V5RVEE.
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
ELECTRICAL CHARACTERISTICS
DC Characteristics DD=4.5~5.5V, VSS=0V, VDD-VEE=8~17V, Ta=-30~+85C) (V Characteristic Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Three-state(OFF) Input Current Driver Input Leakage Current Operating Current Symbol VIH1 VIH2 VIL1 VIL2 VOH VOL ILKG ITSL IDIL IDD1 IDD2 RON Condition IOH=-200A IOL=1.6mA VIN=VSS~VDD VIN=VSS~VDD VIN=VEE~VDD During Display During Access Access Cycle=1MHz VDD-VEE=15V 3/4ILOAD =0.1mA Min 0.7VDD 2.0 0 0 2.4 -1.0 -5.0 -2.0 Typ Max VDD VDD 0.3VDD 0.8 0.4 1.0 5.0 2.0 100 500 7.5 Unit V V V V V V A A A A A K Note *1 *2 *1 *2 *3 *3 *4 *5 *6 *7 *7 *8
On Resistance
*1. CL, FRM, M, RSTB, CLK1, CLK2 2. CS1B, CS2B, CS3, E, R/W, RS, DB0~DB7 3. DB0~DB7 4. Excepted DB0~DB7 5. DB0~DB7 at High lmpedance 6. V0L(R), V2L(R), V3L(R), V5L(R) 7. 1/64 duty, FCLK=250KHZ, Frame Frequency=70HZ, Output: No Load 8. VDD~VEE=15.5V V0L(R)>V2L(R)=VDD-2/7 (VDD-VEE)>V3L(R)=VEE+2/7(VDD-VEE)>V5L(R)
AC Characteristics(VDD=5V10%, VSS=0V, Ta=-30C~+85C)
(1) Clock Timing Characteristic CLK1, CLK2 Cycle Time CLK1 `LOW' Level Width CLK2 `LOW' Level Width CLK1 `HIGH' Level Width CLK2 `HIGH' Level Width CLK1-CLK2 Phase Difference CLK2-CLK1 Phase Difference CLK1, CLK2 Rise Time CLK1, CLK2 Fall Time Symbol tCY tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR tF Min 2.5 625 625 1875 1875 625 625 Typ Max 20 150 150 Unit S
ns
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
tCY tWH1 tR
tF CLK1 0.7VDD 0.3VDD tWL1
tD12
tD21
CLK2
0.7VDD 0.3VDD tWH2
tF
tWLL
tF tCY
Fig 1. External clock waveform
(2) Display Control Timing Characteristic FRM Delay Time M Delay Time CL `LOW' Level Width CL `HIGH' Level Width
Symbol tDF tDM tWL tWH
tW L
Min -2 -2 35 35
Typ -
Max +2 +2 -
Unit us us us us
CL
0.7VDD 0.3VDD tD F 0.7VDD tD F tW H
FRM
0.3VDD
tD M
M
0.7VDD 0.3VDD
Fig 2. Display control signal waveform
KS0108B
(3) MPU Interface Chatacteristic E Cycle E High Level Width E Low Level Width E Rise Time E Fall Time Address Set-Up Time Address Hold Time Data Set-Up Time Data Delay Time Data Hold Time (Write) Data Hold Time (Read)
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
Symbol tC tWH tWL tR tF tASU tAH tSU tD tDHW tDHR
tC
Min 1000 450 450 140 10 200 10 20
Typ -
Max 25 25 320 -
Unit ns ns ns ns ns ns ns ns ns ns ns
E 2.0V 0.8V tWL tWH
tR R/W tAH
tF
tASU
tASU
tAH
CS1B-CS3,RS
0.8V
2.0V
tDSU
tDH
DB0-7
Fig 3. MPU write timing
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
tC
E tWL tWH
tK
tF
R/W
tASU
tAH
tASU
tAH
CS1B-CS3,RS
tD
tDH
DB0-7
Fig 3. MPU write timing
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
APPLICATION CIRCUIT
1.1/64 duty common driver(KS0107B) interface circuit
Rf
Cf
from MPU
~ RSTB R CR C CS1B CS2B CS3 R/W RS E DB0 DB7
~
VDD ADC V0 V5 V1 V4 VEE VOR,VOL V5R,V5L V1R,V1L V4R,V4L VEE DIO1 DIO2 M FRM CLK1 CLK2 Open Open M FRM CLK1 CLK2 CL2 S1 S64 VSS SEG1 LCD C64 COM64 SEG64 VOR,VOL
VDD
V0 V5 V1 V4 VEE
KS0108B
V5R,V5L V2R,V3L V3R,V3L VEE1, VEE2 VSS
KS0107B
VDD VDD SHL FS MS PCLK2 DS2 DS1 VSS
CL2
CL
COM1
VDD V0 R1 V1 R1 V2 R2 V3 R1 V4 R1 V5
VEE
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
OPERATING PRINCIPLES & METHODS
1. I/O Buffer Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC can operate regardless CS1B-CS3. 2. Input register Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is written into input register. Then Writing it into display RAM. Data latched for falling of the E signal and write automatically into the display data RAM by internal operation. 3. Output register Output register stores the data temporarily from display data RAM when CS1B, CS2B, CS3 is in active mode and R/W and RS=H, stored data in display data RAM is latched in output register. When CS1B to CS3 is in active mode and R/W=H, RS=L, status data (busy check) can read out. To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output register. In second access, MPU can read data which is latched. That is, to read the data in display data RAM, it needs dummy read. But status read is not needed dummy read. RS L H R/W L H L H Function Instruction Status read (busy check) Data write (from input register to display data RAM) Data read (from display data RAM to output register)
4. Reset Reset can be initialized system by setting RSTB terminal at low level when turning power on, receiving instruction from MPU. When RSTB becomes low, following procedure is occured. 1. Display off 2. Display start line register become set by 0.(Z-address 0) While RSTB is low, any instruction except status read can be accepted. Reset status appers at DB4. After DB4 is low, any instruction can be accepted. The Conditions of power supply at initial power up are shown in table 1. Table 1. Power Supply Initial Conditions Item Symbol Reset Time tRS Rise Time tR
VDD
Min 1.0 4.5[V]
Typ -
Max 200
Unit us ns
tRS tR
RSTB
0.7VDD 0.3VDD
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
5. Busy flag Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in internal operating. When busy flag is low, KS0108B can accept the data or instruction. DB7 indicates busy flag of the KS0108B.
6. Display On/Off Flip-Flop The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non selective voltage appears on segment output terminals regardless of display RAM data. The display on/off flip-flop can changes status by instruction. The display data at all segment disappear while RSTB is low. The status of the flip-flop is output to DB5 by status read instruction. The display on/off flip-flop synchronized by CL signal. 7. X Page Register X page register designates page of the internal display data RAM. It has not count function. An address is set by instruction. 8. Y address counter Y address counter designates address of the internal display data RAM. An address is set by instruction and is increased by 1 automatically by read or write operations of display data. 9. Display Data RAM Display data RAM stores a display data for liquid crystal display. To express on state dot matrix of liquid crystal display, write data 1. The other way, off state writes 0. Display data RAM address and segment output can be controlled by ADC signal. ADC=H DB<0:7>=0 - Y-address 0 - A0 - S1 DB<0:7>=63 - Y-address 63 - A63 - S64 ADC=L DB<0:7>=0 ~ Y-address 63 - A63 - S64 DB<0:7>=63 ~ A0 - S1 ADC terminal connect the VDD or VSS. 10. Display Start Line Register The display start line register indicates of display data RAM to display top line of liquid crystal display. Bit data (DB<0:5>) of the display start line set instruction is latched in display start line register. Latched data is transferred to the Z address counter while FRM is high, presetting the Z address counter. It is used for scrolling of the liquid crystal display screen.
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
DISPLAY CONTROL INSTRUCTION
The display control instructions control the internal state of the KS0108B. Instruction is received from MPU to KS0108B for the display control. The following table shows various instructions. Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Display ON/OFF L L L L H H H H H L/H Controls the display on or off. Internal status and display RAM data is not affected. L:OFF, H:ON Set Address L L L H Sets the Y address in Y address (0~63) the Y address counter. Set Page L L H L H H H Sets the X address at Page ( X address) the X address register. (0~7) Display Start L L H H Indicates the display Display start line Line data RAM displayed at (0~63) the top of the screen. L L L L Read status. R L O Status Read L H B BUSY L: Ready E N U H: In operation S / S ON/OFF L: Display ON E O Y H: Display OFF T F RESET L: Normal F H: Reset Write Display H L Writes data (DB0:7) into Write Data Data display data RAM. After writing intruction, Y address is increased by 1 automatically. Read Display H H Reads data (DB0:7) from Read Data Data display data RAM to the data bus.
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
2. Timing diagram (1/64 duty)
KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
3.
LCD Panel interface application circuit
KS0108B NO. 1 S1 S64
KS0108B NO. 2 S1 S64
KS0108B NO. 8 S1 S64
COM1 KS0107B (Master) C1 C2 C3 COM64 COM2 COM3
C64
LCD PANEL
(128x480 dots) C1 C2 C3 COM67 C64 COM65 COM66
KS0107B (Master)
COM128
S1
S64 NO.9 KS0108B
S1
S64 NO.10 KS0108B
S1
S64 NO.16 KS0108B
KS0108B
PAD DIAGRAM
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
3
2
1
100
99
98
97
96
95
94
93
92
91
90
86
85
84
83
82
81
80
79
78
77 76 75 74 73 72 71 70 69
Y
68 67 66
(0,0)
X
65 64 63
CHIP SIZE : 40904020 PAD SIZE : 100100 UNIT : i m
62 61 60 59 58 57 56 55 54 53 52
* "KS0108B" Marking : easy to find the PAD No.30
26 27 28 29
KS0108B
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
KS0108B
PAD LOCATION
PAD NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 PAD NAME ADC M VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
COORDINATE X -1140 -1275 -1410 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1487 -1187 -1062 -937 -812 Y 1845 1845 1845 1809 1684 1559 1434 1309 1165 1040 915 790 665 540 415 290 165 40 -84 -209 -334 -459 -584 -709 -834 -959 -1099 -1239 -1379 -1845 -1845 -1845 -1845 -1845
PAD NUMBER 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
PAD NAME S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5
COORDINATE X -687 -562 -437 -312 -187 -62 62 187 312 437 562 687 812 937 1062 1187 1487 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 Y -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1379 -1239 -1099 -959 -834 -709 -584 -459 -334 -209 -84 41 166 291 416 541 666
PAD NUMBER 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
PAD NAME S4 S3 S2 S1 VEE1 V0L V5L V2L V3L VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
COORDINATE X 1882 1882 1882 1882 1882 1882 1882 1882 1882 1412 1277 1142 1007 882 757 632 507 382 NC NC NC Y 791 916 1041 1166 1310 1435 1559 1684 1809 1845 1845 1845 1845 1845 1845 1845 1845 1845
CS3 CS2B CS1B RSTB R/W RS CL CLK2 CLK1 E FRM
245 120 -5 -130 -255 -380 -505 -630 -755 -880 -1005
1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845

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