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INTEGRATED CIRCUITS
DATA SHEET
TDA10085HT Single chip DVB-S/DSS channel receiver
Product specification Supersedes data of 2000 March 16 File under Integrated Circuits, IC02 2001 Aug 31
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
CONTENTS 11 2 3 4 5 6 7 8 9 10 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 16 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
TDA10085HT
2001 Aug 31
2
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
1 FEATURES
TDA10085HT
* DSS and DVB-S compliant single chip demodulator and forward error correction * Dual 6-bit Analog-to-Digital Converter (ADC) on-chip * PLL that allows using a low-cost crystal (typically 4 MHz) * DiSEqC 1.X from 1 to 8 byte-long sequences with modulated or unmodulated output * DSS dish control * Digital cancellation of ADC offset * Simultaneous parallel and serial output interfaces * Variable rate BPSK/QPSK coherent demodulator * Modulation rate variable from 1 to 49 Mbauds * Automatic gain control output * Digital symbol timing recovery: - Acquisition range up to 960 ppm * Carrier offset cancellation up to one half of the sampling frequency * Digital carrier recovery: - Acquisition range up to 12% of the symbol rate * Half-Nyquist filters: roll-off = 0.35 for DVB and 0.2 for DSS * Interpolating and anti-aliasing filters to handle variable symbol rates * Channel quality estimation * Spectral inversion ambiguity resolution * Viterbi decoder: - Supported rates from 1/2 to 8/9 - Constraint length K = 7 with G1 = 1718 and G2 = 1338 - Viterbi output BER measurement - Automatic code rate search within 1/2, 2/3 and 6/7 in DSS mode - Automatic code rate search within 1/2, 2/3, 3/4, 5/6 and 7/8 in DVB-S mode * Convolutional de-interleaver and Reed Solomon decoder according to DVB and DSS specifications * Automatic frame synchronization * Selectable DVB-S descrambling * I2C-bus interface * 64-pin TQFP package * CMOS technology (0.2 m, 1.8 V to 3.3 V). 2 APPLICATIONS * DVB-S receivers (ETS 300-421) * DSS receivers. 3 GENERAL DESCRIPTION
The TDA10085 is a single-chip channel receiver for satellite television reception matching both DSS and DVB-S standards. The device contains a dual 6-bit flash ADC, variable rate BPSK/QPSK coherent demodulator and forward error correction functions. The ADC interfaces directly with I and Q analog baseband signals. After analog-to-digital conversion, the TDA10085 implements a bank of cascadable filters as well as anti-alias and half-Nyquist filters. An analog AGC signal is generated using an amplitude estimation function. The TDA10085 performs clock recovery at twice the baud rate and achieves coherent demodulation without any feedback to the local oscillator. Forward error correction is built around two error-correcting codes: a Reed-Solomon (outer code) and a Viterbi decoder (inner code). The Reed-Solomon decoder corrects up to 8 erroneous bytes among the N (204) bytes of one data packet. A convolutional de-interleaver is located between the Viterbi output and the Reed-Solomon decoder input. The de-interleaver and Reed-Solomon decoder are automatically synchronized according to a frame synchronization algorithm that uses the sync pattern present in each packet. The TDA10085 is controlled via an I2C-bus interface. The circuit operates at sampling frequencies up to 100 MHz, can process variable modulation rates and achieves transmission rates up to 45 Mbaud. Furthermore, for dish control applications, hardware supports DiSEqc 1.x with control access via the I2C-bus. An interrupt line that can be programmed to activate on events or on timing information is provided. Designed in 20 micron CMOS technology and housed in a TQFP64 package, the TDA10085 operates over the commercial temperature range.
2001 Aug 31
3
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
4 ORDERING INFORMATION TYPE NUMBER TDA10085HT 5 PACKAGE
TDA10085HT
VERSION NAME TQFP64 DESCRIPTION plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm SOT357-1
BLOCK DIAGRAM
handbook, full pagewidth
VDDE5 24
DVCC 7
VDDI 3, 8, 26, 38, 55 PWM ENCODER
PLLVCC 4
VDD3 10
AVD 16 CARRIER SYNC
ADVD 42
VDDE 27, 44, 57
VAGC
30
62 AGC DETECTION ADC OFFSET CANCELLATION AGC DETECTION 61 60 DUAL 6-BIT ADC VIN1 VIN2 15 12 59 COMPLEX MULTIPLIER FILTER BANK HALF-NYQUIST FILTERS 54 53 52 NCO XIN XOUT 1 2 PLL VITERBI DECODER ENSERI VREFN VREFP TMD CLB# SADDR0 IICDIV SCL SDA SCL-0 SDA-0 46 17 20 33 32 29 28 I2C-BUS TUNER SWITCH DISECQ 63 22K 21 22 31 5 6 9, 25, 39, 56, 64 VSSI 23, 45, 58 VSSE I2C-BUS INTERFACE CONTROL LOGIC 47 48 49 50 19 13 14 18 REED SOLOMON DECODER OUTPUT INTERFACE 37 34 CLOCK SYNC 51
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DE-INTERLEAVER
DE-SCRAMBLER
FEL TMS TCK TRST TDI TDO
TDA10085HT
BOUNDARY SCAN
35 36 40 41
PSYNC UNCOR DEN OCLK
11 AVS
43 ADVS
MGU427
CTRL1 CTRL2 CTRL3
PLLGND DGDND
Fig.1 Block diagram.
2001 Aug 31
4
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
6 PINNING SYMBOL XIN XOUT VDDI PLLVCC PLLGND DGND DVCC VDDI VSSI VDD3 AVS VIN2 VREFN PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 TYPE I I supply supply ground ground supply supply ground supply ground I O DESCRIPTION
TDA10085HT
crystal oscillator input and output pins; in a typical application, a fundamental oscillator crystal is connected between pins XIN and XOUT; see note 1 digital core supply voltage (typically 1.8 V) analog supply voltage for the PLL (typically 3.3 V) analog ground for the PLL digital PLL core ground voltage; see note 2 digital PLL core supply voltage (typically 1.8 V) digital ADC supply voltage (typically 1.8 V) digital ADC ground voltage; see note 2 analog ADC supply voltage (typically 3.3 V) analog ground voltage analog signal input for channel Q; see note 1 negative analog voltage reference output (typically 1.25 V); a decoupling capacitor (typically 0.1 F) must be placed as close as possible between VREFN and GND positive analog voltage reference output (typically 2 V); a decoupling capacitor (typically 0.1 F) must be placed as closed as possible between VREFP and GND analog signal input for channel I; see note 1 analog supply voltage (typically 3.3 V); a 0.1 F decoupling capacitor must be placed between AVD and AVS SADDR0 input signal is the LSB of the I2C-bus address of the TDA10085; other bits of the address are set internally to 000111, therefore the complete I2C-bus address is (MSB to LSB): 0, 0, 0, 1, 1, 1 plus the SADDR0 bit; see note 1 test input; must be connected to ground for normal operation; see note 1 enable serial interface input; when HIGH, the serial transport stream is present on the boundary scan pins (TRST, TDO, TCK, TDI and TMS); when LOW, the boundary scan pins are available; note 1 input to select the I2C-bus internal system clock frequency (depends on the crystal frequency); internal I2C-bus clock is XIN when IICDIV = 0 and XIN/4 if IICDIV = 1; see note 1 control line output 1; this pin function is directly programmable through the I2C-bus interface; default value is logic 1; open-drain output requiring an external pull-up resistor to 3.3 V or to 5 V control line output 2; this pin function is directly programmable through the I2C-bus interface; default value is logic 1; open-drain output requiring an external pull-up resistor to 3.3 V or to 5 V digital ground voltage; see note 2 digital 5 V supply voltage; required for the 5 V tolerance of inputs digital core ground voltage; see note 2
VREFP
14
O
VIN1 AVD SADDR0
15 16 17
I supply I
TMD ENSERI
18 19
I I
IICDIV
20
I
CTRL1
21
OD
CTRL2
22
OD
VSSE VDDE5 VSSI
23 24 25
ground supply ground
2001 Aug 31
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Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
SYMBOL VDDI VDDE SDA_0
PIN 26 27 28
TYPE supply supply I/OD
DESCRIPTION digital core supply voltage (typically 1.8 V) digital supply voltage (typically 3.3 V) I2C-bus bidirectional serial input/ open drain output; equivalent to SDA but with a high-impedance state programmable via the I2C-bus; a pull-up resistor must be connected between this pin and DVCC I2C-bus clock output; equivalent to SCL but with a high-impedance state programmable via the I2C-bus; open drain output requiring an external pull-up resistor to 5 V PWM encoded output signal for AGC; the refresh frequency of AGC information is the sampling frequency divided by 2048, the maximum signal frequency on the VAGC output is 1/4 x AGC sampling clock; the VAGC output can be selected by I2C-bus to be open-drain or have 3.3 V capability (typically, output VAGC is fed to the AGC amplifier through a single RC network) control line 3 input/open drain output; this pin function is directly programmable through the I2C-bus interface and is an input by default; it requires a pull-up resistor to 3.3 or 5 V, or a pull-down resistor to GND I2C-bus bidirectional serial data input/output; the open-drain output requires a pull-up resistor (typically 2.2 k) to be connected between SDA and 5 V for proper operation I2C-bus clock input; nominally a square wave with a maximum frequency of 400 kHz generated by the system I2C-bus master; see note 1 boundary scan mode: test mode select input/output; provides the logic levels needed to change the TAP controller from state to state serial mode enabled (ENSERI = 1): serial TS uncorrectable output; when not in serial mode, TMS must be set to VSS
SCL_0
29
OD
VAGC
30
O or OD
CTRL3
31
I/OD
SDA
32
I/OD
SCL
33
I
TMS
34
I/O
TCK
35
I/O
boundary scan mode: test clock input/output; TCK is an independant clock used to drive the TAP controller serial mode enabled (ENSERI = 1): TCK is the serial TS clock output; when not in serial mode, TCK must be set to VSS
TRST
36
I/O
boundary scan mode: test reset input/output; TRST is an active-LOW reset input to the TAP controller serial mode enabled (ENSERI = 1): test reset input/output; TRST is the serial TS PSYNC output; when not in serial mode, TRST must be set to VSS
FEL
37
OD
front-end locked output signal that goes HIGH when demodulator, Viterbi decoder and de-interleaver are all synchronized; open-drain output requiring an external pull-up resistor to 3.3 or 5 V; can be set via the I2C-bus to be an interrupt pin digital core supply voltage (typically 1.8 V) digital core ground voltage; see note 2 boundary scan mode: test data and instruction serial input serial mode enabled (ENSERI = 1): serial TS data output; must be set to VSS when not in serial mode
VDDI VSSI TDI
38 39 40
supply ground I/O
2001 Aug 31
6
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
SYMBOL TDO
PIN 41
TYPE I/O
DESCRIPTION boundary scan mode: test data serial output; output provided on the falling edge of TCK serial mode enabled (ENSERI = 1): serial TS enable input; must be set to VSS when not in serial mode
ADVD ADVS VDDE VSSE CLB#
42 43 44 45 46
supply ground supply ground I
analog supply voltage for the 2nd PLL (typically 1.8 V) analog ground voltage for the 2nd PLL digital supply voltage (typically 3.3 V) digital ground voltage; see note 2 asynchronous, active LOW input that clears the TDA10085; when CLB# goes LOW the circuit immediately enters its RESET mode and normal operation resumes three XIN rising edges later after CLB# returns HIGH; at RESET, the I2C-bus register contents are all initialized to their default values; the minimum width of CLB# LOW level is three XIN clock periods; pin CLB# is not TTL, 5 V tolerant packet sync output signal goes HIGH on a rising edge of OCLK each time the first byte of a packet is provided uncorrectable packet output signal goes HIGH on a rising edge of OCLK when the packet provided is uncorrectable data enable; this output signal is HIGH when there is valid data on bus DO[7:0] output clock for the parallel DO[7:0] outputs; OCLK is generated internally and depends on which interface type is selected transport stream data output bits; part of the 8-bit parallel data output after demodulation, Viterbi decoding, de-interleaving, RS decoding and de-scrambling; possible output interfaces are three parallel and two serial digital core supply voltage (typically 1.8 V) digital core ground voltage; see note 2 digital supply voltage (typically 3.3 V) digital ground voltage; see note 2 transport stream data output bits; part of the 8-bit parallel data output after demodulation, Viterbi decoding, de-interleaving, RS decoding and de-scrambling; possible output interfaces are three parallel and two serial 22 kHz output used to control the antenna LNB (output is controlled via the I2C-bus interface) digital core ground voltage; see note 2
PSYNC UNCOR DEN OCLK DO0 DO1 DO2 DO3 VDDI VSSI VDDE VSSE DO4 DO5 DO6 DO7 22K VSSI Notes
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
O O O O O O O O supply ground supply ground O O O O O ground
1. TTL, 5 V tolerant input (if VDDE5 is connected to 5 V). 2. DGND, VSSI and VSSE can be connected to the same ground plane.
2001 Aug 31
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Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
57 VDDE
50 OCLK
58 VSSE
55 VDDI
64 VSSI
56 VSSI
62 DO7
61 DO6
60 DO5
59 DO4
54 DO3
53 DO2
52 DO1
51 DO0
63 22K
handbook, full pagewidth
49 DEN 48 UNCOR 47 PSYNC 46 CLB# 45 VSSE 44 VDDE 43 ADVS 42 ADVD 41 TDO 40 TDI 39 VSSI 38 VDDI 37 FEL 36 TRST 35 TCK 34 TMS 33 SCL SDA 32
MGU426
XIN 1 XOUT 2 VDDI 3 PLLVCC 4 PLLGND 5 DGND 6 DVCC 7 VDDI 8
TDA10085HT
VSSI 9 VDD3 10 AVS 11 VIN2 12 VREFN 13 VREFP 14 VIN1 15 AVD 16 SADDR0 17 TMD 18 ENSERI 19 IICDIV 20 CTRL1 21 CTRL2 22 VSSE 23 VDDE5 24 VSSI 25 VDDI 26 VDDE 27 SDA_0 28 SCL_0 29 VAGC 30 CTRL3 31
Fig.2 Pin configuration.
2001 Aug 31
8
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); note 1 SYMBOL VVDDE VVDDI VI Tamb Tj Tsp Note DC supply voltage DC core supply voltage DC input voltage ambient temperature junction temperature solder point temperature PARAMETER -0.5 -0.5 -0.5 0 - - MIN. +4.1 +2.2
TDA10085HT
MAX. V V V C C C
UNIT
VVDDE + 0.5 70 150 300
1. Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended periods may affect device reliability. 8 THERMAL CHARACTERISTICS PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 45 UNIT K/W
SYMBOL Rth(j-a) 9
CHARACTERISTICS PARAMETER digital supply voltage digital core supply voltage digital 5 V supply voltage HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage supply current for VVDDE supply current for VVDDI TTL input; note 1 TTL input IOH = -0.8 mA IOH = -IO(max); note 4 IOL = 0.8 mA IOL = IO(max); note 4 fs = 96 MHz symbol rate 1 Mbaud 27.5 Mbauds 45 Mbauds - - - - - 0.7VVDDE 0 38 93 - 10 - - 139 - - VVDDE 0.3VVDDE 2.0 mA mA mA pF CONDITIONS 3.0 1.6 for 5 V tolerance of inputs 4.5 2.0 -0.5 2.4 - - 68 MIN. 3.3 1.8 5.0 - - - - - - TYP. 3.6 2.0 5.5 +0.8 - - 0.1 0.4 78 MAX. UNIT V V V V V V V V mA
SYMBOL VVDDE VVDDI VVDDE5 VIH VIL VOH VOL IVDDE IVDDI
VVDDE + 0.3 V
VVDDE - 0.1 -
Ci XIN fXIN VIH VIL PLL VDVCC
input capacitance
crystal frequency HIGH-level input voltage LOW-level input voltage
4 - - 1.8
MHz V V
digital PLL supply voltage
1.6
V
2001 Aug 31
9
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
SYMBOL VPLLVCC ADC VVDD3 VAVD VVIN1, VVIN2 Ci VVREFP VVREFN SINAD THD Notes
PARAMETER analog PLL supply voltage
CONDITIONS 3.0
MIN. 3.3
TYP. 3.6
MAX.
UNIT V
3 V ADC digital supply voltage analog supply voltage analog input voltage DC component AC component analog input capacitance top voltage reference bottom voltage reference ADC signal to noise and distortion ratio total harmonic distortion note 2 note 3
3.0 3.0 VVREFN - - - - - -
3.3 3.3 - 750 - 2.475 1.725 34 35
3.6 3.6 VVREFP - 16 - - - -
V V V mV pF V V dB dB
1. All inputs except pin CLB# are 5 V tolerant. 2. Signal-to-noise plus distortion ratio (SINAD): ratio between the RMS magnitude of the fundamental input frequency to the RMS magnitude of all other ADC output signals. 3. Total Harmonic Distortion (THD): ratio of the RMS sum of all harmonics of the input signal (below one half of the sampling frequency) to the RMS value at the fundamental frequency. 4. IO(max) = 8 mA for pins OCLK and TCK IO(max) = 4 mA for pins DO[7:0], DEN, PSYNC, UNCOR, TDI, TDO, TRST, TMS, SDA, SCL_O and SDA_O IO(max) = 2 mA for pins CTRL1, CTRL2, CTRL3, VAGC and FEL, 22K.
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Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
10 APPLICATION INFORMATION
TDA10085HT
handbook, full pagewidth
MIXER
x
VIN1
VAGC XIN 30 1 15
XOUT 2 51-54 59-62 8 DO[7-0]
LO from LNB 90 PHASE SHIFT PLL
VREFP VREFN
14
TDA10085HT
13
50 49 48
OCLK DEN UNCOR PSYNC
GND
x
MIXER
VIN2
47 12 28 29 32 33 SDA-0 SCL-0 SDA SCL
MGU428
The TDA10085 can receive a 4 MHz clock signal delivered by the PLL synthesizer, or can generate the sampling clock from a crystal connected between XIN and XOUT. Bypass capacitors (0.1 F) should be placed close to ADC voltage references VREFP and VREFN.
Fig.3 Front-end receiver schematic.
handbook, full pagewidth
LNB SUPPLY GENERATION
channel I LNB TUNER channel Q
VIN1
VAGC CTRL1 30 21 15
22K 63 51-54 MPEG2 59-62 8 32 33 SDA SCL transport stream DO[7-0]
VIN2
TDA10085
12 28 29 SDA-0 SCL-0
MGU429
Fig.4 Typical use of CTRL1 and 22K outputs.
2001 Aug 31
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Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
11 PACKAGE OUTLINE TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm
TDA10085HT
SOT357-1
c
y X A 48 49 33 32 ZE
e E HE A wM pin 1 index bp 17 1 16 ZD bp D HD wM B vM B vM A detail X Lp L A2 A 1 (A 3)
64
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.1 Z D(1) Z E(1) 1.45 1.05 1.45 1.05 7 0o
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT357-1 REFERENCES IEC 137E10 JEDEC MS-026 EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-12-27 00-01-19
2001 Aug 31
12
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
12 SOLDERING 12.1 Introduction to soldering surface mount packages
TDA10085HT
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
12.5 Suitability of surface mount IC packages for wave and reflow soldering methods
TDA10085HT
SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 13 DATA SHEET STATUS DATA SHEET STATUS(1) Objective specification PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
Preliminary specification
Qualification
Product specification
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2001 Aug 31
14
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
14 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 PURCHASE OF PHILIPS I2C COMPONENTS 15 DISCLAIMERS
TDA10085HT
Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2001 Aug 31
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/04/pp16
Date of release: 2001
Aug 31
Document order number:
9397 750 08489

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