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| TISP61CAP3 PROGRAMMABLE OVERVOLTAGE PROTECTOR Copyright (c) 1997, Power Innovations Limited, UK SEPTEMBER 1994 - REVISED SEPTEMBER 1997 PROGRAMMABLE SLIC OVERVOLTAGE PROTECTION q Programmable Voltage Triggered SCR with high Holding Current Transistor Buffered Inputs for Low VGG current Rated for International Surge Wave Shapes WAVE SHAPE 10/700 s 10/1000 s STANDARD CCITT IX K17 REA PE-60 ITSP A 38 30 P PACKAGE (TOP VIEW) q (Tip) K1 1 2 3 4 8 7 6 5 K1 (Tip) A A (Ground) (Ground) (Gate) G NC (Ring) K2 q K2 (Ring) MD6XAV NC - No internal connection Terminal typical application names shown in parenthesis description The TISP61CAP3 is a programmable overvoltage protector designed to protect SLIC applications against lightning and transients induced by ac power lines. Normally the VGG (Gate) terminal will be connected to the negative supply rail of the SLIC When a negative transient exceeds the negative supply rail voltage of the SLIC it will cause the thyristor to crowbar, shunting the surge to ground. The high crowbar holding current prevents dc latchup as the transient subsides. Positive transients are clipped by diode action. device symbol K1 G K2 A SD6XAE Terminals K1, K2 and A correspond to the alternative line designators of T, R and G or A, B and C. The negative protection voltage is controlled by the voltage, VGG, applied to the G terminal. absolute maximum ratings RATING Non-repetitive peak on-state pulse current (see Notes 1, 2 and 3) 5/310 s (CCITT IX K17, open-circuit voltage wave shape 1.5 kV, 10/700 s) 10/1000 s (REA PE-60, open-circuit voltage wave shape 10/1000 s) Non-repetitive peak on-state current, 50 Hz, 1 s (see Notes 1 and 2) Maximum gate current Repetitive peak off-state voltage Maximum gate supply voltage ITSM IGM VDRM VGG(max) ITSP 38 30 2.5 2 - 80 - 80 A rms A V V A SYMBOL VALUE UNIT NOTES: 1. Above 70C, derate linearly to zero at 150C case temperature 2. This value applies when the initial case temperature is at (or below) 70C. The surge may be repeated after the device has returned to thermal equilibrium. 3. Most PTT's quote an unloaded voltage waveform. In operation the TISP essentially shorts the generator output. The resulting loaded current waveform is specified. PRODUCT INFORMATION Information is current as of publication date. Products conform to specifications in accordance with the terms of Power Innovations standard warranty. Production processing does not necessarily include testing of all parameters. 1 TISP61CAP3 PROGRAMMABLE OVERVOLTAGE PROTECTOR SEPTEMBER 1994 - REVISED SEPTEMBER 1997 electrical characteristics, TJ = 25C PARAMETER VF V FR Forward voltage Forward recovery voltage Gate cathode voltage VGK(BO) TEST CONDITIONS IF = 5 A dv/dt = 300 V/s di/dt < 10 A/s RSOURCE = 30 RSOURCE = 300 MIN TYP MAX 3 7 UNIT V V at breakover (V(BO) - VGG) Impulse gate cathode dv/dt = -250 V/ms -72 < VGG < -10 V -3 V VGK(BO) voltage at breakover (V(BO) - VGG) On-state voltage Off-state current Switching current Holding current Gate reverse current with cathode open Gate reverse current in the on-state Gate reverse current in the forward conducting state Peak gate switching current Off-state capacitance Critical rate of rise of off-state voltage dv/dt = -300 V/s di/dt < -10 A/s IT = -4 A VD = -80 V dv/dt = -250 V/ms di/dt = 30 mA/s VGG = -72 V VGG = -72 V -72 < VGG < -10 V -72 < VGG < -10 V VGG = -80 V -72 < VGG < -10 V -72 < VGG < -10 V RSOURCE = 30 -15 -3 -10 V V A A A VT ID IS IH IGAO IGAT RSOURCE = 300 -0.15 -0.15 -10 A mA IT = -0.5 A IT = 1 A IT = 5 A -72 < VGG < -10 V VD = -3 V VD = -48 V RSOURCE = 300 (see Note 4) -50 -10 -30 -1 IGAF VGG = -72 V mA IGSM Coff dv/dt NOTE dv/dt = -250 V/ms -72 < VGG < -10 V 5 150 80 mA pF V/s VGG = -72 V, linear ramp, Maximum ramp value > 0.85 VGG 4: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The third terminal is connected to the guard terminal of the bridge. PRODUCT INFORMATION 2 TISP61CAP3 PROGRAMMABLE OVERVOLTAGE PROTECTOR SEPTEMBER 1994 - REVISED SEPTEMBER 1997 PARAMETER MEASUREMENT INFORMATION +i ITSP Quadrant I Forward Conduction Characteristic ITSM IF VF VGK(BO) VGG VD ID -v +v I(BO) IS IH VT IT ITSM V(BO) VS Quadrant III Switching Characteristic ITSP -i PM6XAA Figure 1. VOLTAGE-CURRENT CHARACTERISTIC PRODUCT INFORMATION 3 TISP61CAP3 PROGRAMMABLE OVERVOLTAGE PROTECTOR SEPTEMBER 1994 - REVISED SEPTEMBER 1997 MECHANICAL DATA P008 plastic dual-in-line package This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions The package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to secure the package in the board during soldering. Leads require no additional cleaning or processing when used in soldered assembly. P008 10,2 (0.400) MAX 8 7 6 5 Designation per JEDEC Std 30: PDIP-T8 Index Dot C L 7,87 (0.310) 7,37 (0.290) T.P. 6,60 (0.260) 6,10 (0.240) C L 1 2 3 4 1,78 (0.070) MAX 4 Places 5,08 (0.200) MAX Seating Plane 0,51 (0.020) MIN 105 90 8 Places 3,17 (0.125) MIN 2,54 (0.100) T.P. 6 Places (see Note A) 0,533 (0.021) 0,381 (0.015) 8 Places 0,36 (0.014) 0,20 (0.008) 8 Places ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position MDXXABA PRODUCT INFORMATION 4 TISP61CAP3 PROGRAMMABLE OVERVOLTAGE PROTECTOR SEPTEMBER 1994 - REVISED SEPTEMBER 1997 IMPORTANT NOTICE Power Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the information being relied on is current. PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except as mandated by government requirements. PI accepts no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor is any license, either express or implied, granted under any patent right, copyright, design right, or other intellectual property right of PI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS. Copyright (c) 1997, Power Innovations Limited PRODUCT INFORMATION 5 |
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