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MICRONAS
DAC 3550A Stereo Audio DAC
Edition July 23, 1999 6251-109-4E 6251-467-1DS
MICRONAS
DAC 3550A
Contents Page 3 3 5 5 6 6 6 6 6 6 7 7 8 8 8 9 9 9 9 10 10 10 12 12 12 12 13 13 14 15 17 17 18 20 25 25 25 26 26 27 27 27 28 32 Section 1. 1.1. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.9. 2.10. 2.10.1. 2.10.2. 2.11. 2.12. 2.13. 2.14. 3. 3.1. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.3.4. 3.4. 3.5. 3.6. 3.7. 3.7.1. 3.7.2. 3.7.3. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.5.1. 4.5.2. 4.6. 5. Title Introduction Main Features Functional Description I2S Interface Interpolation Filter Variable Sample and Hold 3rd-order Noise Shaper and Multibit DAC Analog Low-pass Input Select and Mixing Matrix Postfilter Op Amps, Deemphasis Op Amps, and Line-Out Analog Volume Headphone Amplifier Clock System Standard Mode MPEG Mode I2C Bus Interface Registers Chip Select Reduced Feature Mode Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Audio Pins Oscillator and Clock Pins Other Pins Pin Configuration Pin Circuits Control Registers Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Applications Line Output Details Recommended Low-Pass Filters for Analog Outputs Recommendations for Filters and Deemphasis Recommendations for MegaBass Filter without Deemphasis plus 1st-order low-pass Power-up/down Sequence Power-up Sequence Power-down Sequence Typical Applications Data Sheet History
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DAC 3550A
Stereo Audio DAC 1. Introduction The DAC 3550A is a single-chip, high-precision, dual digital-to-analog converter designed for audio applications. The employed conversion technique is based on oversampling with noise-shaping. With Micronas' unique multibit sigma-delta technique, less sensitivity to clock jitter, high linearity, and a superior S/N ratio has been achieved. The DAC 3550A is controlled via I2C bus. Digital audio input data is received by a versatile I2S interface. The analog back-end consists of internal analog filters and op amps for cost-effective additional external sound processing. The DAC 3550A provides line-out, headphone/speaker amplifiers, and volume control. Moreover, mixing additional analog audio sources to the D/A-converted signal is supported. The DAC 3550A is designed for all kinds of applications in the audio and multimedia field, such as: MPEG players, CD players, DVD players, CD-ROM players, etc. The DAC 3550A ideally complements the MPEG 1/2 layer 2/3 audio decoder MAS 3507D. No crystal required for standard applications with sample rates from 32 to 48 kHz. Crystal required only for automatic sample rate detection below 32 kHz, MPEG mode (refer to Section 2.10), and use of clock output CLKOUT. 1.1. Main Features - no master main input clock required - integrated stereo headphone amplifier and mono speaker amplifier - SNR of 103 dBA - I2C bus, I2S bus - internal clock oscillator - full-feature mode by I2C control (three selectable subaddresses) - reduced feature mode for non-I2C applications - continuous sample rates from 8 kHz to 50 kHz - analog deemphasis for 44.1 kHz - analog volume and balance: +18...-75 dB and mute - oversampling and multibit noise-shaping technique - THD better than 0.01 % - two additional analog stereo inputs (AUX) with source selection and mixing - supply range: 2.7 V...5.5 V - low-power mode - additional line-out - on-chip op amps for cost-effective external analog sound processing
Analog Inputs
WSI CLI DRI IS
2
Interpolation Filter
DAC
Input Select and Mixing
Volume and Headphone Amplifier
OUTL OUTR
Fig. 1-1: Block diagram of the DAC 3550A
demand signal
Host (PC, Controller)
MPEG clock MPEG bit stream
MAS 3507D
I2S
DAC 3550A
line out
14.725 MHz
ROM, CD-ROM, RAM, Flash Mem. ..
CLKOUT
Fig. 1-2: Typical application: MPEG Layer 3 Player
Micronas
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DAC 3550A
CLI 23
DAI 24
WSI 25 18 Vdd Vss
IS
2
Digital Supply
17
Sample Rate Detection
9
AVDD0 AVDD1 AVSS0 AVSS1 VREF AGNDC
Interpolation Filter Analog Supply
10 3 2 44
PLL Variable S & H
1
16 CLKOUT 14
SDA SCL
3rd-order Noise Shaper & Multibit DAC Osc. Analog Low-pass Filter
I 2C
15
27 26
TESTEN PORQ DEECTRL MCS1 MCS2
XTO
13
XTI
12
Control
21 19 20
AUX2L
29
32
AUX1R
AUX1L
31
Input Select Switch Matrix
30
AUX2R
DEEML FOPL FOUTL FINL
34 38 37 39
35
DEEMR FOPR FOUTR FINR
Postfilter Op Amps Deemphasis Op Amps Line-Out
42 41 43
Analog Volume
Headphone Amplifier
5 OUTL 7 OUTR
Fig. 1-3: Block diagram of the DAC 3550A
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2. Functional Description 2.1. I2S Interface The I2S interface is the digital audio interface between the DAC 3550A and external digital audio sources such as CD/DAT players, MPEG decoders etc. It covers most of the I2S-compatible formats. All modes have two common features: 1. The MSB is left justified to an I2S frame identification (WSI) transition. 2. Data is valid on the rising edge of the bit clock CLI. 16-bit mode In this case, the bit clock is 32 x fsaudio. Maximum word length is 16 bit. 32-bit mode In this case, the bit clock is 64 x fsaudio. Maximum word length is 32 bit. Left-Right Selection Standard I2S format defines an audio frame always starting with left channel and low-state of WSI. However, I2C control allows changing the polarity of WSI. Delay Bit Standard I2S format requires a delay of one clock cycle between transitions of WSI and data MSB. In order to fit other formats, however, this characteristic can be switched off and on by I2C control. Automatic Detection No I2C control is required to switch between 16- and 32-bit mode. It is recommended to switch the DAC 3550A into mute position during changing between 16- and 32-bit mode. For high-quality audio, it is recommended to use the 32-bit mode of the I2S interface to make use of the full dynamic range (if more than 16 bits are available).
Vh
CLI
Vl
Vh
DAI
15 14 13 12 11 10 9 8
Vl
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
76543210
programmable delay bit
WSI
Vh Vl
left 16-bit audio sample
right 16-bit audio sample
Fig. 2-1: I2S 16-bit mode (LR_SEL=0)
Vh
CLI
Vl
Vh
DAI
31 30 29 28 27 26 25 24
Vl
7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0
programmable delay bit
WSI
Vh Vl
left 32-bit audio sample
right 32-bit audio sample
Fig. 2-2: I2S 32-bit mode (LR_SEL=0)
Note: Volume mute should be applied before changing I2S mode in order to avoid audible clicks.
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2.2. Interpolation Filter The interpolation filter increases the sampling rate by a factor of 8. The characteristic for fsaudio = 48 kHz is shown in Fig. 2-3. 2.6. Input Select and Mixing Matrix This block is used to switch between or mix the auxiliary inputs and the signals coming from the DAC. A switch matrix allows to select between mono and stereo mode as shown in Fig. 2-4.
dB 0 -0.02 -0.04 -0.06 -0.08 -0.1 -0.12 -0.14 0 5000 10000 15000 20000 f/Hz
DAD DAI WSI
FOUTL D/A FOUTR
24.576 MHz
AUX1L AUX1R AUX2L AUX2R
AUX_MS INSEL_AUX2 INSEL_AUX1 INSEL_DAC
Fig. 2-3: 18 Interpolation filter; frequency range: 0...22 kHz Fig. 2-4: Switch matrix 2.3. Variable Sample and Hold The advantage of this system is that even at low sample frequencies the out-of-band noise is not scaled down to audible frequencies.
Mono mode is realized by adding left and right channel.
2.7. Postfilter Op Amps, Deemphasis Op Amps, and Line-Out 2.4. 3rd-order Noise Shaper and Multibit DAC The 3rd-order noise shaper converts the oversampled audio signal into a 5-bit noise-shaping signal at a high sampling rate. This technique results in extremely low quantization noise in the audio band. This block contains the active components for the analog postfilters and the deemphasis network. The op amps and all I/O-pins for this block are shown in Fig. 2-5.
2.5. Analog Low-pass The analog low-pass is a first order filter with a cut-off frequency of approximately 1.4 MHz which removes the high-frequency components of the noise-shaping signal.
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optional line-out
AVSS
AGNDC +
3.3 F/100 nF
For external components, see section "Applications"
AVOL_R
+ OUTL
150 F 1.5 k Speaker 32 47 47 16-32
VREF
FOUTL DEEML
from switch matrix
FINL FINR
FOPL FOPR
FOUTR DEEMR
-
150 F 1.5 k
Headphones
AVDD
to C (HP-switch)
+
Fig. 2-5: Postfilter op amps, deemphasis op amps, and line-out
2.8. Analog Volume The analog volume control covers a range from +18 dB to -75 dB. The lowest step is the mute position. Step size is split into a 3-dB and a 1.5-dB range:
Table 2-1: Volume Control Volume/dB 18.0 16.5 15.0 13.5 AVOL 111000 110111 110110 110101
-75 dB...-54 dB: 3 dB step size -54 dB...+18 dB: 1.5 dB step size
2.9. Headphone Amplifier The headphone amplifier output is provided at the OUTL and OUTR pins connected either to stereo headphones or a mono loudspeaker. The stereo headphones require external 47- serial resistors in both channels. If a loudspeaker is connected to these outputs, the power amplifier for the right channel must be switched to inverse polarity. In order to optimize the available power, the source of the two output amplifiers should be identical, i.e. a monaural signal. Please note, that if a speaker is connected, it should strictly be connected as shown in Fig. 2-5. Never use a separate connector for the speaker, because electrostatic discharge could damage the output transistors.
AVOL_L
For external components, see section "Applications"
-
0.0
IRPA
OUTR
-
101100 (default) 101011
-1.5 - -54.0 -57.0 - -75
Mute
-
001000 000111
-
000001 000000
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2.10. Clock System The advantage of the DAC 3550A clock system is that no external master clock is needed. Most DACs need 256 x fsaudio, 384 x fsaudio, or at least an asynchronous clock. All internal clocks are generated by a PLL circuit, which locks to the I2S bit clock (CLI). If no I2S clock is present, the PLL runs free, and it is guaranteed that there is always a clock to keep the IC controllable by I2C. The device can be set to two different modes: - Standard mode - MPEG mode In the standard mode, I2C subaddressing is possible (ADR0, ADR1, ADR2). MPEG mode always uses ADR3. To select the modes, the MCS1/MCS2 pins must be set according to Table 2-2. Table 2-2: Operation Modes
MCS1 MCS2 Mode Subaddress ADR0 ADR1 ADR2 ADR3 Default Sample Rate 32-48 kHz 32-48 kHz 32-48 kHz Automatic
2.10.1. Standard Mode - without I2C In standard mode, sample rates from 48 kHz to 32 kHz are handled without I2C control automatically. The setting for this range is the default setting. - with I2C Sample rates below 32 kHz require an I2C control to set the PLL divider. This ensures that even at low sample rates, the DAC 3550A runs at a high clock rate. This avoids audible effects due to the noiseshaping technique of the DAC 3550A. Sample rate range is continuous from 8 to 50 kHz. The I2C setting of low sample rates must follow according to Section 3.6. "Control Registers" on page 15. An additional mode allows automatic sample rate detection. In this case, the clock oscillator is required and must run at frequencies between 13.3 MHz to 17 MHz. This mode, however, does not support continuous sample rates. Only the following sample rates are allowed: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz The sample rate detection allows a tolerance of 200 ppm at WSI. If the oscillator is not used for automatic sample rate detection, it can be used as a general-purpose clock for the application. The frequency range in this case is 10 MHz to 25 MHz.
0 0 1 1
0 1 0 1
Standard Standard Standard MPEG
2.10.2. MPEG Mode This mode should be used in conjunction with MAS 3507D in MPEG player applications. In this case a 14.725 MHz signal is needed to provide a clock for the MAS 3507D and to allow an automatic sample rate detection in the DAC 3550A. All MPEG sample rates from 8 to 48 kHz can be detected. The internal processing and the DAC itself are automatically adjusted to keep constant performance throughout the entire range. I2C control for sample rate adjustment is not needed in this case. Register SR_REG[0:2] is locked to SRC_A; see Section 3.6. "Control Registers" on page 15. The MPEG sample rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz As in standard mode, the sample rate detection allows a tolerance of 200 ppm at WSI. Subaddressing is not possible in MPEG mode; this means, in multi-DAC systems, only one DAC 3550A can run in MPEG mode.
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2.11. I2C Bus Interface The DAC 3550A is equipped with an I2C bus slave interface. The I2C bus interface uses one level of subaddressing: The I2C bus address is used to address the IC. The subaddress allows chip select in multi DAC applications and selects one of the three internal registers. The registers are write-only. The I2C bus chip address is given below. dev_write = $9A. The registers of the DAC 3550A have 8- or 16-bit data size; 16-bit registers are accessed by writing two 8-bit data words. A6 1 A5 0 A4 0 A3 1 A2 1 A1 0 A0 1 R/W 0
S
dev_write
Ack sub_adr
Ack 1 byte data
Ack P
8-bit I2C write access Ack P 16-bit I2C write access
S
dev_write
Ack sub_adr
Ack 1 byte data
Ack
1 byte data
SDA SCL S
1 0
P
W R Ack Nak S P
= = = = = =
0 1 0 1 Start Stop
Fig. 2-6: I2C bus protocols for write operations
2.12. Registers In Section 3.6. "Control Registers" on page 15, a definition of the DAC 3550A control registers is shown. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in the table. All registers are write-only. The register address is coded by 3 bits (RA1, RA0) according to Table 2-3.
2.13. Chip Select Chip select allows to connect up to four DAC 3550A to an I2C control bus. The chip subaddresses are defined by the MCS1/MCS2 (Mode and Chip Select) pins. Only in standard mode, chip select is possible. MPEG mode always uses chip subaddress 3. Register address and chip select are mapped into the subaddress field in Table 2-4.
2.14. Reduced Feature Mode Table 2-3: I2C Register Address RA1 0 1 1 RA0 1 0 1 Mnemonics SR_REG AVOL GCFG Table 2-4: I2C Subaddress The mnemonics used in the DAC 3550A demo software of Micronas are given in the last column. 7 MCS2 6 MCS1 5 4 3 2 1 RA1 0 RA0 If I2C control is not used, the IC is in the default mode (see Section 3.6. "Control Registers" on page 15) after start-up. Default Volume setting is 0 dB and digital audio input is set to standard I2S. Sample rates from 32 kHz to 48 kHz are supported in this mode. Applications with no need for volume control or analog input could use this mode.
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DAC 3550A
3. Specifications 3.1. Outline Dimensions
10 x 0.8 = 8 0.17 33 34 13.2 23 22 10 x 0.8 = 8 0.375 0.8 10 0.8
1.3 12 1 1.75 13.2 11
1.75
44
2.0 2.15 0.1
10
D0024/2E
Fig. 3-1: 44-Pin Plastic Metric Quad Flat Package (PMQFP44) Weight approximately 0.4 g Dimensions in mm
3.2. Pin Connections and Short Descriptions NC = not connected, leave vacant LV = if not used, leave vacant VSS = if not used, connect to VSS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin Name AGNDC AVSS1 AVSS0 NC OUTL NC OUTR NC AVDD0 AVDD1 NC XTI XTO CLKOUT SCL IN IN/OUT OUT IN/OUT IN IN OUT OUT Type IN/OUT IN IN Connection
(if not used)
= obligatory; connect as described in application diagram VDD = connect to VDD Short Description Analog reference Voltage VSS 1 for audio back-end VSS 0 for audio output amplifiers Not connected Audio Output: Headphone left or Speaker + Not connected Audio Output: Headphone right or Speaker - Not connected VDD 0 for audio output amplifiers VDD 1 for audio back-end Not connected Quartz oscillator pin 1 Quartz oscillator pin 2 Clock Output I2C clock
X
X X X LV LV LV LV LV X X LV X X LV LV
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DAC 3550A
Pin No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Pin Name SDA VSS VDD MCS1 MCS2 DEECTRL NC CLI DAI WSI PORQ TESTEN NC AUX2L AUX2R AUX1L AUX1R NC DEEML DEEMR NC FOUTL FOPL FINL NC FOUTR FOPR FINR VREF
Type IN/OUT IN IN IN IN IN
Connection
(if not used)
Short Description I2C data Digital VSS Digital VDD I2C Chip Select 1 I2C Chip Select 2 Deemphasis on/off Control Not connected I2S Bit Clock I2S Data I2S Frame Identification Power-On Reset, active-low Test Enable Not connected AUX2 left input for external analog signals (e.g. tape) AUX2 right input for external analog signals (e.g. tape) AUX1 left input for external analog signals (e.g. FM) AUX1 right input for external analog signals (e.g. FM) Not connected Deemphasis Network Left Deemphasis Network Right Not connected Output to left external filter Filter op amp inverting input, left Input for FOUTL or filter op amp output (line out) Not connected Output to right external filter Right Filter op amp inverting input Input for FOUTR or filter op amp output (line out) Analog reference Ground
LV X X X X VSS LV VSS
IN IN IN IN
VSS VSS VDD X LV
IN IN IN IN
LV LV LV LV LV
OUT OUT
LV LV LV
OUT IN/OUT IN/OUT
X X X LV
OUT IN/OUT IN/OUT IN
X X X X
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DAC 3550A
3.3. Pin Descriptions 3.3.1. Power Supply Pins The DAC 3550A combines various analog and digital functions which may be used in different modes. For optimized performance, major parts have their own power supply pins. All VSS power supply pins must be connected. VDD (18) VSS (17) The VDD and VSS power supply pair are connected internally with all digital parts of the DAC 3550A. AVDD0 (9) AVSS0 (3) AVDD0 and AVSS0 are separate power supply pins that are exclusively used for the on-chip headphone/ loudspeaker amplifiers. AVDD1 (10) AVSS1 (2) The AVDD1 and AVSS1 pins supply the analog audio processing parts, except for the headphone/loudspeaker amplifiers. FOUTL (37) FOPL (38) FINL (39) FOUTR (41) FOPR (42) FINR (43) Filter op amps are provided in the analog baseband signal paths. These inverting op amps are freely accessible for external use by these pins. The FOUTL/R pins are connected with the buffered output of the internal switch matrix. The FOPL/R-pins are directly connected with the inverting inputs of the filter op amps. The FINL/R pins are connected with the outputs of the op amps. The driving capability of the FOUTL/R pins is not sufficient for standard line output signals. Only the FINL/R pins are suitable for line output. OUTL (5) OUTR (7) The OUTL/R pins are connected to the internal output amplifiers. They can be used for either stereo headphones or a mono loudspeaker. The signal of the right channel amplifier can be inverted for mono loudspeaker operation. Caution: A short circuit at these pins for more than a momentary period may result in destruction of the internal circuits.
3.3.2. Analog Audio Pins AGNDC (1) Reference for analog audio signals. This pin is used as reference for the internal op amps. This pin must be blocked against VREF with a 3.3 F capacitor. Note: The pin has a typical DC-level of 1.5/2.25 V. It can be used as reference input for external op amps when no current load is applied. VREF (44) Reference ground for the internal band-gap and biasing circuits. This pin should be connected to a clean ground potential. Any external distortions on this pin will affect the analog performance of the DAC 3550A. AUX1L (31) AUX1R (32) AUX2L (29) AUX2R (30) The AUX pins provide two analog stereo inputs. Auxiliary input signals, e.g. the output of a conventional receiver circuit or the output of a tape recorder can be connected with these inputs. The input signals have to be connected by capacitive coupling.
3.3.3. Oscillator and Clock Pins XTI (12) XTO (13) The XTI pin is connected to the input of the internal crystal oscillator, the XTO pin to its output. Both pins should be directly connected to the crystal and two ground-connected capacitors (see application diagram). CLKOUT (14) The CLKOUT pin provides a buffered output of the crystal oscillator. Caution: Power dissipation limit may be exceeded in case of short to VSS or VDD. CLI (23) DAI (24) WSI (25) These three pins are inputs for the digital audio data DAI, frame indication signal WSI, and bit clock CLI. The digital audio data is transmitted in an I2S-compatible format. Audio word lengths of 16 and 32 bits are supported, as well as SONY and Philips I2S protocol. SCL (15) SDA (16) SCL (serial clock) and SDA (serial data) provide the connection to the serial control interface (I2C).
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3.3.4. Other Pins TESTEN (27) Test enable. This pin is for test purposes only and must always be connected to VSS. PORQ (26) This pin may be used to reset the chip. If not used, this pin must be connected to VDD. DEEML (34) DEEMR (35) These pins connect an external analog deemphasis network to the signal path in the analog back-end. This connection can be switched on and off by an internal switch which is controlled either by I2C or the DEECTRL-pin. DEECTRL (21) If no I2C-control is used, deemphasis can be switched on and off with this pin. MCS1 (19) MCS2 (20) Mode select pins to select MPEG, Standard Mode, and I2C subaddress.
DEEML DEEMR NC FOUTL FOPL FINL NC FOUTR FOPR FINR VREF AUX1L AUX1R NC
3.4. Pin Configuration
NC AUX2L AUX2R TESTEN PORQ WSI DAI CLI
33 32 31 30 29 28 27 26 25 24 23 34 35 36 37 38 39 40 41 42 43 44 1 AGNDC AVSS1 AVSS0 NC OUTL NC NC OUTR 2 3 4 5 6 7 8 9 10 11 NC AVDD1 AVDD0 22 21 20 19 18 NC DEECTRL MCS2 MCS1 VDD VSS SDA SCL CLKOUT XTO XTI
DAC 3550A
17 16 15 14 13 12
Fig. 3-2: 44-pin PMQFP package
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3.5. Pin Circuits
VDD
FOUTn
N VSS Fig. 3-3: Input/Output Pins SDA, SCL
AGNDC Fig. 3-8: Output Pins FOUTL, FOUTR
XTO
500 k
Fig. 3-4: Input Pins DAI, WSI, PORQ, CLI XTI Fig. 3-9: Input/Output Pins XTI, XTO VDD P N VSS Fig. 3-5: Output Pin CLKOUT AGNDC
mono/stereo
AUXnL
sel/nonsel
AGNDC
mono/stereo
ext. filter network FOUTn DEEM FOPn FINn
AUXnR
sel/nonsel
Fig. 3-10: Input Pins AUX1R, AUX1L, AUX2R, AUX2L, AGNDC (DEEMCTRL)
AGNDC
Fig. 3-6: Pins FINR, FOPR, FINL, FOPL, DEEML, DEEMR AGNDC
OUTn
Fig. 3-11: Output Pins OUTL, OUTR AGNDC
125 k
VDD VREF AVSS0/1 VSS Fig. 3-7: Pins AGNDC, VREF Fig. 3-12: Input Pins MCS1, MCS2, DEECTRL
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3.6. Control Registers
I2C Subaddress (hex) Number of Bits Mode Function Default Values (hex) Name
SAMPLE RATE CONTROL SR_REG 01 8 w sample rate control bit[7:5] bit[4] not used, set to 0 L/R-bit 0 (WSI = 0 left channel)1) 1 (WSI = 0 right channel)1) Delay-Bit 0 No Delay 1 1 bit Delay sample rate control 000 32-48 kHz 001 26-32 kHz 010 20-26 kHz 011 14-20 kHz 100 10-14 kHz 101 8-10 kHz 11x2) autoselect LR_SEL 0H
bit[3]
SP_SEL
bit[2:0]
SRC_48 SRC_32 SRC_24 SRC_16 SRC_12 SRC_8 SRC_A
ANALOG VOLUME AVOL 02 16 w audio volume control bit[15] bit[14] not used, set to 0 deemphasis on/off 0 deemphasis off 1 deemphasis on DEEM 2C2CH
bit[13:8] analog audio volume level left: 000000 mute -75 dB 000001 101100 +0 dB (default) 111000 +18 dB bit[7:6] bit[5:0] not used, set to 0 analog audio volume level right 000000 mute -75 dB 000001 101100 +0 dB (default) 111000 +18 dB
AVOL_L
AVOL_R
1) 2)
see Fig. 2-1 and Fig. 2-2 on page 5 don't care
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DAC 3550A
I2C Subaddress (hex)
Number of Bits
Mode
Function
Default Values (hex)
Name
Global Configuration GCFG 03 8 w global configuration bit[7] bit[6] not used, set to 0 select 3V-5 V mode 0 3V 1 5V power-mode 0 normal 1 low power AUX2 select 0 AUX2 off 1 AUX2 on AUX1 select 0 AUX1 off 1 AUX1 on DAC select 0 DAC off 1 DAC on (default) aux-mono/stereo 0 stereo 1 mono invert right power amplifier 0 not inverted 1 inverted SEL_53V 4H
bit[5]
PWMD
bit[4]
INSEL_AUX2
bit[3]
INSEL_AUX1
bit[2]
INSEL_DAC
bit[1]
AUX_MS
bit[0]
IRPA
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3.7. Electrical Characteristics 3.7.1. Absolute Maximum Ratings Symbol TA TS Pmax VSUPA VSUPD VIdig1 Parameter Ambient Operating Temperature1) Storage Temperature Power Dissipation Analog Supply Voltage2) Digital Supply Voltage Input Voltage, digital inputs AVDD0/1 VDD MCS1, MCS2, DEECTRL WSI, CLI, DAI, PORQ, SCL, SDA Pin Name Min. 0 Max. 70 125 500 Unit
C C
mW V V V
-40
-0.3 -0.3 -0.3
6 6 VSUPD + 0.3
VIdig2
Input Voltage, digital inputs
-0.3
6
V
IIdig VIana IIana IOaudio IOdig
1) 2) 3) 4)
Input Current, all digital inputs Input Voltage, all analog inputs Input Current, all analog inputs Output Current, audio output3) Output Current, all digital outputs4) OUTL/R
-5 -0.3 -5 -0.2 -10
+5 VSUPA + 0.3 +5 0.2 10
mA V mA A mA
=standard temperature range, DAC 3550A tested in extended temperature range on request Both have to be connected together! These pins are NOT short-circuit proof! Total chip power dissipation must not exceed absolute maximum rating
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
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3.7.2. Recommended Operating Conditions Symbol Parameter Pin Name Min. Typ. Max. Unit
Temperature Ranges and Supply Voltages TA VSUPA1 VSUPD Ambient Temperature Range1) Analog Audio Supply Voltage Digital Supply Voltage AVDD0/1 VDD 0 3.02) 2.7 3.3 3.3 70 5.5 5.5
C
V V
Relative Supply Voltages VSUPA Analog Audio Supply Voltage in relation to the Digital Supply Voltage AVDD0/1 VSUPD -0.25 V 5.5 V
Analog Reference CAGNDC1 CAGNDC2 Analog Reference Capacitor Analog Reference Capacitor AGNDC AGNDC 1.0 3.3 10
F
nF
Analog Audio Inputs VAI VAI Analog Input Voltage AC, SEL_53V = 0 Analog Input Voltage AC, SEL_53V = 1 AUXnL/R3) AUXnL/R3) 0.35 0.525 0.7 1.05 Vrms Vrms
Analog Filter Input and Output ZAFLO ZAFLI Analog Filter Load Output4) Analog Filter Load Input4) FOUTL/R FINL/R 7.5 6 5.0 7.5 Analog Audio Output ZLO ZAOL_HP ZAOL_SP Audio Line Output5) (680 Series Resistor required) Analog Output Load HP (47 Series Resistor required) Analog Output Load SP (bridged) Analog Output Load SP (Stereo)
1) 2) 3) 4) 5)
k pF k pF
FINL/R OUTL/R OUTL/R
10 1.0 32 400 32 50 16 100
k nF
pF pF pF
=standard temperature range, DAC 3550A tested in extended temperature range on request typically operable down to 2.7 V, without loss in performance n = 1 or 2 Please refer to Section 4.2. "Recommended Low-Pass Filters for Analog Outputs" on page 25. Please refer to Section 4.1. "Line Output Details" on page 25.
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DAC 3550A
Symbol I2C Input fI2C1 fI2C2 Digital Inputs VIH VIL
Parameter
Pin Name
Min.
Typ.
Max.
Unit
I2C Clock Frequency, I2S active I2C Clock Frequency, I2S inactive
SCL
400 100
kHz kHz
Input High Voltage Input Low Voltage
CLI, WSI, DAI, PORQ, SCL, SDA
0.5x VDD 0.2x VDD
V
V
Quartz Characteristics FP REQ C0 Load Resonance Frequency at Cl = 20 pF Equivalent Series Resistance Shunt (parallel) Capacitance 13.3 14.725 12 3 17 30 5 MHz
pF
Load at CLKOUT Output Cload
1) 2) 3) 4) 5)
Capacitance
CLKOUT
0
50
pF
=standard temperature range, DAC 3550A tested in extended temperature range on request typically operable down to 2.7 V, without loss in performance n = 1 or 2 Please refer to Section 4.2. "Recommended Low-Pass Filters for Analog Outputs" on page 25. Please refer to Section 4.1. "Line Output Details" on page 25.
Micronas
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DAC 3550A
3.7.3. Characteristics At TA = 0 to 70 C*, VSUPD = 2.7 to 5.5 V, VSUPA = 3.0 to 5.5 V; typical values at TJ = 27 C, VSUPD = VSUPA = 3.3 V, quartz frequency = 14.725 MHz, duty cycle = 50 %, positive current flows into the IC
Symbol Digital Supply IVDD IVDD Current Consumption Current Consumption VDD VDD 5 8 mA mA VSUPD =3 V VSUPD =5 V Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Digital Input Pin - Leakage II Input Leakage Current CLI, WSI, DAI, TESTEN, PORQ, DEECTRL, MCS1/2
1
A
VGND VI VSUP
Digital Output Pin - Clock Out VOH VOL I2C Bus Ron Output Impedance SCL, SDA 60 Iload = 5 mA, VSUPD = 2.7 V Output High Voltage Output Low Voltage CLKOUT
- 0.3
VSUPD 0.3
V V
no load at output
Analog Supply IAVDD Current Consumption Analog Audio, SEL_53V = 0 SEL_53V = 1 PSRRAA Power Supply Rejection Ratio for Analog Audio Output AVDD0/1, OUTL/R AVDD0/1 8 1.5 11 2 50 20 PSRRLO Power Supply Rejection Ratio for Line Output AVDD0/1, FINL/R 50 40 Reference Frequency Generation VDCXTI CLI Vxtalout DC Voltage at Oscillator Pins Input Capacitance at Oscillator Pin Voltage Swing at Oscillator Pins, pp Oscillator Start-Up Time XTI/O XTI/O XTI/O 60 0.5 * VSUPA 3 100 50 V pF % VSUP A ms AVDD/VDD 2.5 V 11 15 mA mA mA mA dB dB dB dB PWMD = 0, Mute PWMD = 1, Mute PWMD = 0, Mute PWMD = 1, Mute 1 kHz sine at 100 mVrms 100 kHz sine at 100 mVrms 1 kHz sine at 100 mVrms 100 kHz sine at 100 mVrms
* =standard temperature range, DAC 3550A tested in extended temperature range on request
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DAC 3550A
Symbol Analog Audio VAO
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Analog Output Voltage AC
OUTL/R, FOUTL/R, FINL/R
0.65
0.7
0.75
Vrms
SEL_53V = 0, RL > 5 k, Analog Gain = 0 dB Input = 0 dBFS digital SEL_53V = 1 f = 1 kHz, sine wave, RL > 5 k 0.5 Vrms to AUXnL/R SEL_53V = 0, RL = 32 , Analog Gain = +3 dB, distortion < 1%, external 47 series resistor required SEL_53V = 1 RL = 32 (bridged), Analog Gain = +3 dB, distortion < 10%, SEL_53V = 0, IRPA = 1 SEL_53V = 1
1.0 GAUX Gain from Auxiliary Inputs to Line Outputs Output Power (Headphone) AUXnL/R, FINL/R OUTL/R
1.05 0
1.1 0.5
Vrms dB
-0.5
PHP
5
mW
12 PSP Output Power (Speaker) OUTL/R 120
mW mW
280 GAO dGAO1 dGAO2 EGA1 EGA2 EGA3 EdGA SNRAUX Analog Output Gain Setting Range Analog Output Gain Step Size Analog Output Gain Step Size Analog Output Gain Error Analog Output Gain Error Analog Output Gain Error Analog Output Gain Step Size Error Signal-to-Noise Ratio from Analog Input to Line Output Signal-to-Noise Ratio from Analog Input to Headphone Output OUTL/R OUTL/R OUTL/R OUTL/R OUTL/R OUTL/R OUTL/R AUXn, FINL/R AUXn, OUTn
mW 18 dB dB dB 2 1 0.5 0.5 dB dB dB dB dB dB
-75
3.0 1.5
-75 dB...-54 dB -54 dB...+18 dB -46.5 dBAnalog Gain -54 dB -40.5 dBAnalog Gain -45 dB -39 dB -48 dB
+18 dBAnalog Gain +18 dBAnalog Gain Analog Gain:
Analog Gain:
-2 -1 -0.5 -0.5
98 93
SEL_53V = 0: input -40 dB below 0.7 Vrms Analog Gain = 0 dB, BW =20 Hz...20 kHz unweighted
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DAC 3550A
Symbol SNR1
Parameter Signal-to-Noise Ratio
Pin Name OUTL/R
Min. 89
Typ. 91
Max.
Unit dB
Test Conditions RL 32 (external 47 series resistor required) BW =20 Hz...0.5 fs unweighted, Analog Gain = 0 dB, Input = -20 dBFS RL 5 k, Rdec 612 BW etc. as above 16 bit I2S, SEL_53V = 0 32 bit I2S, SEL_53V = 0 16 bit I2S, SEL_53V = 1 32 bit I2S, SEL_53V = 1 32 bit I2S, SEL_53V = 1 RL 32 (external 47 series resistor required) BW = 20 Hz..0.5 fs unweighted Analog Gain= -40.5 dB, Input = -3 dBFS BW = 20 Hz...22 kHz unweighted, no digital input signal, Analog Gain = Mute 0...0.446 fs (no external filters used) 0.55...7.533 fs (no external filters used) (no external filters used) BW = 20 Hz...22 kHz, unweighted, RL > 5 k Input 1 kHz at 0.5 Vrms Rdec 612 BW = 20 Hz...0.5 fs, unweighted, RL > 5 k Input 1 kHz at -3 dBFS Rdec 612 BW = 20 Hz...0.5 fs, unweighted, RL 32 (47 series resistor required), Analog Gain = 0 dB, Input 1 kHz at -3 dBFS
FINL/R
90
92
dB
94 96 98 103 SNR2 Signal-to-Noise Ratio OUTL/R 58 62
dB dB dB dBA dB
LevMute
Mute Level
OUTL/R
-110
dBV
RD/A
D/A Pass Band Ripple
OUTL/R, FOUTL/R
-0.1
dB
AD/A
D/A Stop Band Attenuation
40
dB
BWAUX THDALO
Bandwidth for Auxiliary Inputs Total Harmonic Distortion from Auxiliary Inputs to Line Outputs
AUXnL/R, FINL/R AUXnL/R, FINL/R
760 0.01
kHz %
THDDLO
Total Harmonic Distortion (D/A converter to Line Output)
FINL/R
0.01
%
THDHP
Total Harmonic Distortion (Headphone)
OUTL/R
0.05
%
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DAC 3550A
Symbol THDSP
Parameter Total Harmonic Distortion (Speaker)
Pin Name OUTL/R
Min.
Typ.
Max. 0.5
Unit %
Test Conditions BW = 20 Hz...0.5 fs, unweighted, RL 32 (speaker bridged), Analog Gain = 0 dB, Input 1 kHz at -3 dBFS f = 1 kHz, sine wave, RL > 7.5 k Analog Gain = 0 dB, Input = -3 dBFS or 0.5 Vrms to AUXnL/R f = 1 kHz, sine wave, OUTL/R: RL 32 (47 series resistor required) Analog Gain = 0 dB, Input = -3 dBFS or 0.5 Vrms to AUXnL/R f = 1 kHz, sine wave, FOUTL/R: RL > 7.5 k OUTL/R: RL 32 (47 series resistor required) Analog Gain = 0 dB, Input = -3 dBFS and 0.5 Vrms to AUXnL/R SEL_53V = 0 RL >> 10 M, referred to VREF SEL_53V = 1 RL >> 10 M, referred to VREF
XTALKLO
Cross-Talk Left/Right Channel (Line Output)
AUXnL/R, FOUTL/R, FINL/R
-70
-80
dB
XTALKHP
Crosstalk Left/Right Channel (Headphone)
OUTL/R
-70
-80
dB
XTALK2
Crosstalk between Input Signal Pairs
AUXnL/R
-70
-80
dB
VAGNDC
Analog Reference Voltage
AGNDC
1.5
V
2.25
V
Micronas
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DAC 3550A
Symbol RIAUX
Parameter Input Resistance at Input Pins
Pin Name AUXnL/R
Min. 12.1 11.6
Typ. 15
Max. 17.9 19.0
Unit k k
Test Conditions TJ = 27 C TA = 0 to 70 C1) Input selected, PWMD = 0 i = 10 A, referred to VREF TJ = 27 C TA = 0 to 70 C1) Input not selected i = 10 A, referred to VREF TJ = 27 C PWMD = 1 i = 200 A, referred to VREF PWMD = 1, Mute i = 10 A, referred to VREF referred to AGNDC Mute referred to AGNDC PWMD = 0, referred to AGNDC PWMD = 0, referred to AGNDC Analog Gain = Mute, PWMD switched from 0 to 1
24.2 23.3
30
35.8 37.9
k k
ROOUT
Output Resistance at Output Pins
OUTL/R
700
ROFILT
Output Resistance of Filter Pins Offset Voltage at Input Pins Offset Voltage at Output Pins Offset Voltage at Filter Output Pins Offset Voltage at Filter Input Pins Difference of DC Voltage at Output Pins after Back-end Low Power Sequence
FINL FINR
15 11.25
k k 20 10 20 20 10 mV mV mV mV mV
VOffI VOffO VOffFO VOffFI dVDCPD
AUXnL/R OUTL/R FOUTL/R FINL/R OUTL/R
-20 -10 -20 -20 -10
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Micronas
DAC 3550A
4. Applications 4.1. Line Output Details
Rdec FINL(R) Cline
AVSS
Rin
2nd-order
11 k 11 k
11 k 220 pF
1.0 nF
AVSS
FOUTL(R)
FOPL(R)
FINL(R)
-
Fig. 4-1: Use of FINL/R as Line Outputs Table 4-1: Load at FINL/R when used as Line Output for external amplifier Filter Order 1st, 2nd, 3rd Rdec 680 Rin > 10 k Frequency 24 kHz 30 kHz Gain Fig. 4-3: 2nd-order low-pass filter Table 4-3: Attenuation of 2nd-order low-pass filter
Rdec:Resistor used for decoupling Cline from FINL(R) to achieve stability
Cline: Capacitive load according to e.g. cable,
-1.5 dB -3.0 dB
amplifier Rin: Input resistance of amplifier
3rd-order
15 k 7.5 k 7.5 k 120 pF
4.2. Recommended Low-Pass Filters for Analog Outputs*
1st-order
15 k 330 pF FOUTL(R) 15 k
7.5 k
1.8 nF
AVSS
1.8 nF
FOPL(R)
FINL(R)
-
FOUTL(R)
FOPL(R)
FINL(R)
Fig. 4-4: 3rd-order low-pass filter Table 4-4: Attenuation of 3rd-order low-pass filter
-
Fig. 4-2: 1st-order low-pass filter Table 4-2: Attenuation of 1st-order low-pass filter Frequency 24 kHz 30 kHz Gain
Frequency 18 kHz 24 kHz
Gain 0.17 dB
-0.23 dB -3.00 dB
-2.2 dB -3.0 dB
30 kHz
* without deemphasis circuit
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DAC 3550A
4.3. Recommendations for Filters and Deemphasis
R3 R1 R1 R2 R4 C3 R5 C4 C1
ON OFF
4.4. Recommendations for MegaBass Filter without Deemphasis plus 1st-order low-pass
R2 R3 R4 R5 C2 C3
C1
C2
AVSS
FOUTL(R)
FOPL(R)
FINL(R)
DEEML(R)
FOUTL(R)
FOPL(R)
FINL(R)
-
-
Fig. 4-5: General circuit schematic Table 4-5: Resistor and Capacitor values 1st order R1 (k) C1 (pF) R2 (k) C2 (pF) R3 (k) C3 (pF) R4 (k) R5 (k) C4 (nF) 0 open 18 open 18 180 0 18 1.8 11 1000 11 180 11 22 1.0 2nd order 3rd order 7.5 560 7.5 270 15 82 7.5 22 1.0
Fig. 4-6: General circuit schematic Table 4-6: Resistor and Capacitor values DC-Gain = 10 dB fc1 = 100 Hz fc2 = 330 Hz R1 (k) C1 (nF) R2 (k) R3 (k) R4 (k) R5 (k) C2 (nF) C3 (pF) 13 47 0 15 15 13 47 180
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Micronas
DAC 3550A
4.5. Power-up/down Sequence In order to get a click-free power-up/down characteristic, it is recommended to use the following sequences: 4.5.2. Power-down Sequence 1. Stop I2S data. 2. Send I2C: LOW POWER. 3. Switch VDD, AVDD0/1 to 0. 4.5.1. Power-up Sequence 1. Start VDD from 0 to +3.3 V and start AVDD0/1 from 0 to +3.3 V/+5 V. AVDD should not ramp up faster than VDD. 2. Release PORQ from 0 to AVDD0/1. 3. Send I2C: volume, input select, speaker, ... optional. 4. Start I2S data. The most important point is: PORQ has to ramp up after AVDD0/1, simply by using a 10-k pull-up resistor to AVDD0/1 and a 2.2-nF capacitor to ground. No further control on PORQ is needed.
VDD
90% VDD
AVDD
90% AVDD
PORQ
0.7 xAVDD <0.2xVDD
<30 ms
Fig. 4-7: Power-up sequence
Micronas
27
DAC 3550A
4.6. Typical Applications
A
Fig. 4-8: Application circuit schematic 1: Standard application with analog deemphasis. Oscillator not needed.
28
n
Micronas
DAC 3550A
A
n
Fig. 4-9: Application circuit schematic 2: MPEG application with analog Megabass and 14.725 MHz crystal
Micronas
A
29
DAC 3550A
demand signal
Host (PC, Controller)
MPEG clock MPEG bit stream
MAS 3507D
I2S
DAC 3550A
line out
14.725 MHz
ROM, CD-ROM, RAM, Flash Mem. .. CLKOUT
Fig. 4-10: MPEG Layer-3 Player
FM-TUNER
DEMOD
L
R
Optical Pickup
DSP & SERVO
I2S
DAC DAC 3550A 3550A
line out
384 x fs
CLKOUT
Fig. 4-11: CD-Player with FM-Radio
TUNER
18.432 MHz
ADRBUS
MSP 34xx
DATA BCLK LRCLK 32 kHz
I2S
DRP 3510 A
DAC DAC 3550A 3550A
line-out
18.432 MHz
Fig. 4-12: ADR Receiver
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Micronas
DAC 3550A
Micronas
31
DAC 3550A
5. Data Sheet History 1. Final data sheet: "DAC 3550A Stereo Audio DAC, Edition July 23, 1999, 6251-467-1DS. First release of the final data sheet.
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-467-1DS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Micronas
DAC 3550A
Preliminary Data Sheet Supplement
Subject: Data Sheet Concerned: Supplement: Edition:
New Package for DAC 3550A DAC 3550A 6251-467-1PD, Edition April 23, 1999 No. 2/ 6251-467-1PDS May 18, 1999
New Package for DAC 3550A: 49-Ball Plastic Ball Grid Array (PBGA49)
1. Outline Dimensions
D0026/1E
Fig. 1: 49-Ball Plastic Ball Grid Array (PBGA49) Dimensions in mm
MICRONAS INTERMETALL
page 1 of 3
DAC 3550A
2. Pin Connections and Short Descriptions NC = not connected, leave vacant X = obligatory; connect as described in application circuit diagram Unassigned pins must be left vacant. Pin No. / Pin ID
PMQFP 44-pin PBGA 49-ball
PRELIMINARY DATA SHEET SUPPLEMENT
LV = if not used, leave vacant VSS = if not used, connect to VSS VDD = connect to VDD
Pin Name
Type
Connection
(If not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
B5 A6 B4
AGNDC AVSS1 AVSS0 NC
BID SUPPLY SUPPLY
X X X LV
Analog reference voltage VSS 1 for audio back-end VSS 0 for audio output amplifiers Not connected Audio output: headphone left or speaker + Not connected Audio output: headphone right or Speaker - Not connected VDD 0 for audio output amplifiers VDD 1 for audio back-end Not connected Quartz oscillator pin 1 Quartz oscillator pin 2 Clock output I2C clock I2C data Digital VSS Digital VDD I2C chip sSelect 1 I2C chip select 2 Deemphasis on/off control Not connected I2S bit clock I2S data I2S frame identification Power-on-reset, active-low
C4
OUTL NC
OUT
LV LV
A3
OUTR NC
OUT
LV LV
A2 A1
AVDD0 AVDD1 NC
SUPPLY SUPPLY
X X LV
C3 C2 D2 C1 D3 D1 E1 F2 F1 G1
XTI XTO CLKOUT SCL SDA VSS VDD MCS1 MCS2 DEECTRL NC
IN BID OUT BID BID SUPPLY SUPPLY IN IN IN
X X LV LV LV X X X X VSS LV VSS
E3 F3 F4 G4
CLI DAI WSI PORQ IN IN IN
VSS VSS VDD
page 2 of 3
MICRONAS INTERMETALL
PRELIMINARY DATA SHEET SUPPLEMENT
DAC 3550A
Pin No. / Pin ID
PMQFP 44-pin PBGA 49-ball
Pin Name
Type
Connection
(If not used)
Short Description
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
F5
TESTEN NC
IN
X LV
Test enable Not connected AUX2 left input for external analog signals (e.g. tape) AUX2 right input for external analog signals (e.g. tape) AUX1 left input for external analog signals (e.g. FM) AUX1 right input for external analog signals (e.g. FM) Not connected Deemphasis network, left Deemphasis network, right Not connected Output to left external filter Filter op amp inverting input, left Input for FOUTL or filter op amp output (line out) Not connected Output to right external filter Right filter op amp inverting input Input for FOUTR or filter op amp output (line out) Analog reference ground
G5 F6 G6 G7
AUX2L AUX2R AUX1L AUX1R NC
IN IN IN IN
LV LV LV LV LV
E5 E6
DEEML DEEMR NC
OUT OUT
LV LV LV
F7 D6 E7
FOUTL FOPL FINL NC
OUT BID IN/OUT
X X X LV
D7 C6 C7 A7
FOUTR FOPR FINR VREF
OUT BID IN/OUT IN
X X X X
MICRONAS INTERMETALL
page 3 of 3

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