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| S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode release by interrupt -- Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 MICROCONTROLLER The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture. The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 is the microcontroller which has mask-programmable ROM. The S3P80A4/P80A8/P80A5/P80B4/P80B8/P80B5 is the microcontroller which has one-time-programmable EPROM. Using a proven modular design approach, Samsung engineers developed the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 by integrating the following peripheral modules with the powerful SAM87 RC core: -- Three programmable I/O ports, including two 8-bit ports and one 3-bit port, for a total of 19 pins. -- Internal LVD circuit and eight bit-programmable pins for external interrupts. -- One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). -- One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. -- One 8-bit counter with auto-reload function and one-shot or repeat control. The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 is a versatile general-purpose microcontroller which is especially suitable for use as remote transmitter controller. It is currently available in a 24-pin SOP and SDIP package. 1-1 PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 FEATURES CPU * Timers and Timer/Counters * SAM87RC CPU core Memory * One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer function One 8-bit timer/counter (Timer 0) with two operating modes; Interval mode and PWM mode. One 16-bit timer/counter with one operating modes; Interval mode Program memory (ROM) - S3C80A4/C80B4: 4-Kbyte (0000H-0FFFH) - S3C80A8/C80B8: 8-Kbyte (0000H-1FFFH) - S3C80A5/C80B5: 15,872 byte (0000H-3E00H) * * Low Voltage Detect Circuit * * Low voltage detect for reset or Back-up mode. Low level detect voltage - S3C80A4/C80A8/C80A5: 2.20 V (Typ) 200 mV - S3C80B4/C80B8/C80B5: 1.90 V (Typ) 200 mV * Data memory: 256-byte RAM Instruction Set * * 78 instructions IDLE and STOP instructions added for powerdown modes Auto Reset Function * Reset occurs when stop mode is released by P0. When a falling edge is detected at Port 0 during Stop mode, system reset occurs. Instruction Execution Time * * 500 ns at 8-MHz fOSC (minimum) Interrupts * * Operating Temperature Range * -40C to + 85C 13 interrupt sources with 10 vector. 5 level, 10 vector interrupt structure Operating Voltage Range I/O Ports * * * * Two 8-bit I/O ports (P0-P1) and one 3-bit port (P2) for a total of 19 bit-programmable pins Eight input pins for external interrupts 1.7 V to 3.6 V at 4 MHz fOSC 2.0 V to 3.6 V at 8 MHz fOSC Package Type * Carrier Frequency Generator * 24-pin SOP/SDIP One 8-bit counter with auto-reload function and one-shot or repeat control (Counter A) Back-up mode * When VDD is lower than VLVD, the chip enters Back-up mode to block oscillation and reduce the current consumption. 1-2 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7/INT0-INT4 P1.0-P1.7 LVD TEST XIN XOUT Main OSC Port 0(INTR) Port 1 Internal Bus P2.0/T0PWM Port I/O and Interrupt Control Port 2 P2.1/REM P2.2 8-bit Basic Timer 8-bit Timer/ Counter SAM87RI CPU Carrier Generator (Counter A) 15-Kbyte ROM 256-Byte Register File 16-bit Timer/ Counter Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PIN ASSIGNMENTS VSS XIN XOUT TEST P0.0/INT0/INTR P0.1/INT1/INTR RESET/P0.2/INT2/INTR RESET P0.3/INT3/INTR P0.4/INT4/INTR P0.5/INT4/INTR P0.6/INT4/INTR P0.7/INT4/INTR 24 1 23 2 22 3 21 4 5 S3C80A4/C80A8/C80A5 20 6 C80B4/C80B8/C80B5 19 18 7 17 8 24-SOP/SDIP 16 9 (TOP VIEW) 15 10 14 11 13 12 VDD P2.2 P2.1/REM/SCLK P2.0/T0PWN/T0CK/SDAT P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Figure 1-2. Pin Assignment Diagram (24-Pin SOP/SDIP Package) 1-4 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. Pin Descriptions Pin Names P0.0-P0.7 Pin Type I/O Pin Description I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. Interrupt with Reset(INTR) is assigned to Port 0. I/O port with bit-programmable pins. Configurable to input mode or output mode. Pin circuits are either push-pull or nchannel open-drain type. Pull-up resistors are assignable by software. 3-bit I/O port with bit-programmable pins. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with pull-up resistors are assignable by software. The two pins of port 2 have high current drive capability. System clock input and output pins Test signal input pin (for factory use only; must be connected to VSS). Power supply input pin Ground pin Circuit Type 1 24-Pin Number 5-12 Shared Functions INT0 - INT4/INTR P1.0-P1.7 I/O 2 13-20 P2.0 P2.1 P2.2 I/O 3 4 5 21-23 REM/T0CK XIN, XOUT TEST - I - - 2, 3 4 - - VDD VSS - - - - 24 1 - - 1-5 PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PIN CIRCUITS VDD Pull-up Resistor Pull-up Enable VDD Data Input/Output Output Disable VSS External Interrupt Noise filter INTR (Interrupt with RESET) Stop Figure 1-3. Pin Circuit Type 1 (Port 0) NOTE Interrupt with reset (INTR) is assigned to port 0 of S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5. It is designed to release stop status with reset. When the falling/rising edge is detected at any pin of Port 0 during stop status, non vectored interrupt INTR signal occurs, after then system reset occurs automatically. It is designed for a application which are using "stop mode" like remote controller. If stop mode is not used, INTR do not operates and it can be discarded. 1-6 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW VDD Pull-up Resistor Pull-up Enable VDD Data Input/Output Open-drain Output Disable VSS Normal Input Noise filter Figure 1-4. Pin Circuit Type 2 (Port 1) VDD Pull-up Resistor (Typical 21K ) Pull-up Enable P2CON.0 VDD Port 2.0 Data T0_PWN M U X Data P2.0/T0PWN Open-drain Output Disable VSS P2.0 Input Figure 1-5. Pin Circuit Type 3 (P2.0) 1-7 PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 VDD Pull-up Resistor (Typical 21K) Pull-up Enable P2CON.1 VDD Port 2.1 Data CAOF(CACON.0) Carrier On/Off (P2.5) M U X Data P2.1/REM/T0CK Open-Drain Output Disable P2.1 Input T0CK Noise filter VSS Figure 1-6. Pin Circuit Type 4 (P2.1) VDD Pull-up Resistor (Typical 21K) Pull-up Enable VDD Data In/Out Open-drain Output Disable VSS Normal Input Figure 1-7. Pin Circuit Type 5 (P2.2) 1-8 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ELECTRICAL DATA 13 OVERVIEW -- I/O capacitance ELECTRICAL DATA In this section, S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by a Reset -- A.C. electrical characteristics -- Input timing for external interrupts (port 0) -- Oscillation characteristics -- Oscillation stabilization time 13-1 ELECTRICAL DATA S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 Table 13-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current High Symbol VDD VIN VO I OH I OL - - All output pins One I/O pin active All I/O pins active Output current Low One I/O pin active Total pin current for ports 0, 1, and 2 Total pin current for port 3 Operating temperature Storage temperature TA TSTG - - Conditions Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 + 40 - 40 to + 85 - 65 to + 150 C C Unit V V V mA mA Table 13-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 3.6 V) Parameter Operating Voltage Symbol VDD Conditions f OSC =8MHz (Instruction clock = 1.33 MHz) Min 2.0 1.7 0.8 VDD VDD - 0.3 0 Typ - - - Max 3.6 3.6 VDD VDD Unit V f OSC = 4MHz (Instruction clock = 0.67 MHz) Input High voltage VIH1 VIH2 All input pins except VIH2 and VIH3 XIN All input pins except VIL2 and VIL3 XIN VDD= 2.4 V, IOH = - 6 mA Port 2.1 only, TA = 25C VDD = 2.4 V, IOH = - 2.2mA Port 2.0, 2.2, TA = 25C VDD = 2.4 V, IOH = - 1 mA All output pins except Port2, TA = 25 C V Input Low voltage VIL1 VIL2 - 0.2 VDD 0.3 V Output High voltage VOH1 VOH2 VOH3 VDD - 0.7 VDD - 0.7 VDD - 1.0 - - V - - 13-2 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ELECTRICAL DATA Table 13-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 3.6 V) Parameter Output Low voltage Symbol VOL1 VOL2 VOL3 Input High leakage current ILIH1 Conditions VDD = 2.4 V, IOL = 12 mA, port 2.1 only, TA = 25 C VDD = 2.4 V, IOL = 5 mA IOL = 1 mA - Min Typ 0.4 Max 0.5 Unit 0.4 0.5 Port 2.0,2.2, TA = 25 C 0.4 1.0 Ports 0 and 1, TA = 25 C VIN = VDD All input pins except XIN and XOUT VIN = VDD, XIN and XOUT VIN = 0 V All input pins except XIN, XOUT VIN = 0 V XIN and XOUT VOUT = VDD All output pins VOUT = 0 V All output pins VDD = 2.4V, VIN = 0 V; VDD = 3.6 V 10% 8-MHz crystal 4-MHz crystal Idle mode; VDD = 3.6 V 10 % 8-MHz crystal 4-MHz crystal Stop mode; VDD = 3.6 V TA = 25 C , Ports 0-2 - 5 2.6 - 1.0 9 5 2.5 mA - - 44 - - 55 - - - - 1 A ILIH2 Input Low leakage current ILIL1 ILIL2 Output High leakage current Output Low leakage current Pull-up resistors ILOH ILOL RL1 IDD1 20 -1 - 20 1 -1 95 A A K A Supply current (note) IDD2 0.7 - 1 2.0 6 uA IDD3 NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. 13-3 ELECTRICAL DATA S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 Table 13-3. Characteristics of Low Voltage Detect circuit (TA = - 40 C to + 85 C) Parameter Hysteresys Voltage of LVD (Slew Rate of LVD) Low level detect voltage (S3C80A4/C80A8/C80A5) Low level detect voltage (S3C80B4/C80B8/C80B5) Symbol V VLVD VLVD Conditions - - - Min - 2.0 1.70 Typ 30 2.20 1.90 Max 300 2.40 2.1 Unit mV V V Table 13-4. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions - VDDDR = 1.0 V Stop mode Min 1.0 - Typ - - Max 3.6 1 Unit V A Table 13-5. Input/output Capacitance (TA = - 40C to + 85 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min -- Typ -- Max 10 Unit pF Table 13-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C) Parameter Interrupt input, High, Low width Symbol tINTH, tINTL Conditions P0.0-P0.7, VDD =3.6 V Min 200 Typ 300 Max -- Unit ns 13-4 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ELECTRICAL DATA tINTL tINTH 0.8 VDD 0.2 VDD NOTE: The unit tCPU means one CPU clock period. Figure 13-1. Input Timing for External Interrupts (Port 0) Table 13-7. Oscillation Characteristics (TA = - 40 C + 85 C) Oscillator Crystal Clock Circuit C1 XIN Conditions CPU clock oscillation frequency Min 1 Typ - Max 8 Unit MHz XOUT C2 Ceramic C1 XTIN CPU clock oscillation frequency 1 - 8 MHz XTOUT C2 External clock External Clock Open Pin XIN XOUT XIN input frequency 1 - 8 MHz 13-5 ELECTRICAL DATA S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 Table 13-8. Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 3.6 V) Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization wait time f OSC > 400 kHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input High and Low width (tXH, tXL) tWAIT when released by a reset (1) Test Condition Min - - 25 - Typ - - - 216/ f OSC - Max 20 10 500 - Unit ms ms ns ms tWAIT when released by an interrupt (2) - - ms NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON. Instruction Clock Instruction Clock 1.33 MHz 1.00 MHz 670 kHz 500 kHz A 250 kHz B 8 MHz 6 MHz 4 kHz 8.32 kHz 1 2 3 4 5 6 7 400 kHz Supply Voltage (V) Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) A 1.7 V: 4 MHz b 2.0 V: 8 MHz Figure 13-2. Operating Voltage Range of S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 13-6 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 MECHANICAL DATA 14 OVERVIEW 10.30 0.30 MECHANICAL DATA The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller is currently available in a 24-pin SOP and SDIP package. 0-8 #24 #13 0.20 24-SOP-375 7.50 0.15 0.10 15.74 MAX 15.34 0.20 2.50 MAX 2.30 0.10 MAX (0.69) 0.38 + 0.10 - 0.05 1.27 NOTE: Dimensions are in millimeters. Figure 14-1. 24-Pin SOP Package Mechanical Data 0.05 MIN 0.85 0.20 #1 #12 + 0.10 - 0.05 9.53 14-1 MECHANICAL DATA S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 #24 #13 0-15 6.40 0.20 #1 #12 23.35 MAX 0.20 22.95 0.20 0.51 MIN 0.46 0.10 (1.70) 0.89 0.10 1.778 NOTE: Dimensions are in millimeters. Figure 14-2. 24-Pin SDIP Package Mechanical Data 14-2 3.30 0.30 5.08 MAX 3.25 0.2 5 +0 - 0 .10 .05 24-SDIP-300 7.62 |
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