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SL2150D
Cable Tuner Front End LNA with AGC Data Sheet
Features
* * * * * Single chip dual output Wide dynamic range on both channels Independent AGC facility incorporated into all channel paths Independent disable facility incorporated into all channel paths Full ESD protection. (Normal ESD handling procedures should be observed)
DS5545 ISSUE 2.1 April 2002
Ordering Information SL2150D/KG/LH1S (tubes) SL2150D/KG/LH1T (tape and reel)
Description
The SL2150D is a wide dynamic range front end for tuner applications.
Applications
* * * Multi-tuner cable set top box and cable modem applications Data communications systems Terrestrial TV tuner loop though
The device offers two buffered outputs from a single input, where both paths contain an independently controllable AGC and disable facility.
AGC1
AGC2
AGC Control RFINPUT RFINPUTB Power Splitter AGC Control
RFOUT1 RFOUT1B
RFOUT2 RFOUT2B
Power Down
DIS1
DIS2
Figure 1 - SL2150D Block Diagram
Zarlink products and associated documents marked "Eng" ("ENGineering Samples") are or relate to products in development and not released to production. All ENGineering Samples are supplied only for testing and on the express understanding that (i) they have not been fully tested or characterized under intended modes of operation and may contain defects; (ii) Zarlink makes no representation or warranty regarding them; and (iii) Zarlink disclaims any liability for claims, demands and damages, including without limitation special, indirect and consequential damages, resulting from any loss arising out of the application, use or performance of them. ENGineering Samples may be changed or discontinued by Zarlink at any time without notice.
SEMICMF.019
1
SL2150D
NC# NC# NC# Vcc Vcc Vcc Vcc
Data Sheet
Vee Vee RFOUT1 RFOUT1B Vcc Vcc Vcc VEE (PACKAGE PADDLE) 1 Vcc Vcc RF INPUT RF INPUT DIS1 Vee DIS22 SL2150D
Vee Vee VFOUT2 RFOUT2B NC# AGC2 AGC1
LH28
# Pins marked NC should be connected to Vee
Figure 2 - Pin Allocation
1.0
Quick Reference Data
NB all data applies with differential termination and single ended source both of 75. Characteristics RF input operating range Conversion gain, with external load as in Figure 11 maximum minimum Input NF, both paths enabled at maximum conversion gain CTB, both paths enabled, all gain settings * CSO, both paths enabled, all gain settings * CXM, both paths enabled, all gain settings * Input impedance Input VSWR Output impedance differential, all loops (requires external load for example as in Figure 11) Input to output isolation (both outputs) Output to output isolation Table 1 - Reference Data
*132 channel matrix at +15 dBmV per channel, 75 source impedance
Units 50-860 11 -25 6.4 -66 -64 -60 75 8 440 30 25 MHz dB dB dB dBc dBc dBc dB dB dB
2
SEMICMF.019
Data Sheet
2.0 Functional Description
SL2150D
The SL2150D is a broadband wide dynamic range dual output tuner front end LNA with AGC. It also has application is any system where a wide dynamic range broadband power splitter is required. The pin assignment is contained in Figure 2 and the block diagram in Figure 1.The port internal peripheral circuits are contained in Figure 14. In normal application the RF input is interfaced to the device input. The input preamplifier is designed for low noise figure, within the operating region of 50 to 860 MHz and for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides an impedance match to a 75 source; the typical impedance is shown in Figure 4. The input NF is shown in Figure 6. The output of the preamplifier is then power split to two independently controlled AGC stages. Each AGC stage provides for a minimum of 30 dB of gain control across the input frequency range. The typical AGC characteristic and NF versus gain setting are contained in Figure 5 and Figure 7 respectively. Finally each of the AGC stages drive an output buffer of differential output impedance of 440 , which provides a nominal 11 dB of conversion gain when terminated into a differential 75 load, as in Figure 11. Each channel AGC and output buffer can be independently powered down. In application it is important to avoid saturation of the output stage, therefore it is recommended that the output standing current be sunk to Vcc through an inductor. A resistive pull up can also be used as shown in Figure 13 "Example Application Driving 100 Load with Resistive Pull Up", however the resistor values should not exceed 20 ohm single ended. If an inductive current sink is used the maximum available gain from the device is circa 26 dB. This gain can be reduced by application of an external load between the differential output ports. The gain can be approximately calculated from the following formula:
- GAIN = 20*log ((Parallel combination of 440 ohm and external load between ports)/22 ohm)+2dB
For example when driving a 100 ohm load as in Figure 12, the gain equals
- GAIN = 20 *log ((440 *100)/(440+100)/22)+2dB =12dB.
SEMICMF.017
3
SL2150D
1nF 3
Data Sheet
RF INPUT SL2150D
RFIN F TYPE 5.1nH
1nF
4 RF INPUTB MABAES0029 1:1
Figure 3 - Input Network
CH1
S11
1 U FS
4_: 133.23
16 Nov 2001 10:10:47 55.758 10.44 nH 850.000 000 MHz
PRm Cor Avg 16 Smo
Z0 75
1_: 169.02 -44.117 50 MHz

2_: 49.916 -57.436 250 MHz 3_: 31.238 -5.5576 500 MHz
4
3
1
2
START 50.000 000 MHz
STOP 850.000 000 MHz
Figure 4 - Typical single-end input impedance
4
SEMICMF.019
Data Sheet
Typical AGC vs Control Voltage 15
SL2150D
5
-5
-15 Gain (dB)
-25
-35
-45
-55
-65 0.5 0.7 0.9 -4 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 AGC Voltage volts (V)
Figure 5 - Typical AGC versus Control Voltage Characteristic
Typical Noise Figure vs Frequency (Vagc=3V, Maximum Gain) 9 8.5 8 7.5 7 NF(dB) 6.5 6 5.5 5 4.5 4 50 150 250 350 450 Frequency (MHz) 550 650 750 850
Figure 6 - Input Noise Figure at 25C
SEMICMF.017
5
SL2150D
Typical Variation in Noise Figure vs. Gain Setting 20
Data Sheet
18
16 Noise Figure (dB)
14
12
10
8
6 -10
-8
-6
-4
-2
0
2 Gain (dB)
4
6
8
10
12
Figure 7 - Typical Variation in NF versus Gain Setting
132 channel matrix, 75 ohm source, all channels at +15dBmV. Input and output conditions as in Fig 3 and Fig 12. -50
-60 CSO,CTB (dBS)
CSO (dBC) CTB (dBC)
-70
-80 -20
-15
-10
-5
0
Figure 8 - Typical Variation In CSO and CTB Versus Backoff from Maximum Gain
6
SEMICMF.019
Data Sheet
SL2150D
50 Driven output stage C D Directional coupler A B Port 1
Network Analyzer Monitored output stage C D Directional coupler phase relationship A C0 D 180 B 0 0 Directional coupler A B 50 Port 2
Figure 9 - Test Condition for Output Crosstalk
Driven output stage C D Directional coupler A B
50
Port 1
Monitored input stage
Network Analyzer Port 2
Directional coupler phase relationship A C0 D 180 B 0 0
Figure 10 - Test Condition for Output to Input Crosstalk
SEMICMF.017
7
SL2150D
Data Sheet
Vcc 100nF 100pF
SL2150D
MABAES0029 1:1 1nF
To 75 load
FTYPE
Figure 11 - Example Application Driving 75 load
Vcc
10H
10H
1nF SL2150D 100
1nF
Figure 12 - Example Application Driving 100 Load with Inductive Pull up
8
SEMICMF.019
Data Sheet
SL2150D
Vcc 2x 20
1nF SL2150D Note: External resistor values must not exceed 20 100
1nF
Figure 13 - Example Application Driving 100 Load with Resistive Pull Up
SEMICMF.017
9
SL2150D
Vcc INPUT
Data Sheet
INPUT DECOUPLED
440
440 Output 2.5V
1 k
270 3.9V 2.5V
1k
32 mA
32 mA
Output Ports
RF Input Port
30 k 1.6V 1.5k
AGC INPUT 1.5V 1.7 k
20 k
AGC INPUT
AGC Port
DIS Port
Figure 14 - Port Peripheral Circuitry
10
SEMICMF.019
Data Sheet
3.0 Electrical Characteristics
SL2150D
Test conditions (unless otherwise stated). T amb =-20o to 85o C, Vee=0V, Vcc=5V+-5% These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated.
Electrical Characteristics
Characteristic Supply current pin min typ 190 110 42 50 3, 4 6.8 75 8 6.4 7.2 max 220 140 60 860 units mA mA mA MHz dB dB See Figure 4 See Figure 4 Tamb=270C, see Figure 6 All loops at maximum conversion gain See Figure 7 Power gain from 75 single ended source to differential 75 load, with application as in Figure 11. Vagcip=3.0V Vagcip=0.5V Vagcip=Vee AGC monotonic from Vee to Vcc. Refer to Functional description section for information on calculating maximum gain with other load conditions See note (2) See note (3) See note (2) See note (3) See note (2) Conditions Both outputs enabled One output enabled Both outputs disabled
Input frequency range Input impedance Input return loss Input Noise Figure
Variation in NF with gain adjust Gain
-1
dB/dB
maximum minimum minimum
9.5
11 -50
12.5 -25
dB dB dB
CSO CTB CXM
-66 -62 -65 -62 -60
dBc dBc dBc dBc dBc
SEMICMF.017
11
SL2150D
Electrical Characteristics (continued)
Characteristic Input P1dB Gain variation within channel pin min typ +4.5 0.25 max units dBm dB
Data Sheet
Conditions All gain settings, with load as in Figure 11 Channel bandwidth 8 MHz within operating frequency range, all loops, all gain settings Differential Standing current that any external load has to sustain. Vagcip =Vee to Vcc
Output impedance Output port DC standing current AGC1, 2 input leakage current DIS1, 2 input Input high voltage Input low voltage Leakage current Crosstalk between outputs
11,12, 24,25 11,12, 24,25 8,9 6, 7 2.8 Vee -200 -200
440 50
mA
200
A
Vcc 0.8 200 -25
V V A dB
Output disabled Output enabled DIS1, 2 = Vee to Vcc All gain settings, measured differential output to differential output, driven ports in phase and monitored ports out of phase, see Figure 9 All gain settings, measured differential output to single ended input, driven ports in phase, see Figure 10
Crosstalk between outputs and RF input
-30
dB
Note 1: Note 2: Note 3:
All power levels are referred to 75,and 0 dBm =109 dBV. Load as in Figure 11 & Figure 12, at maximum gain, 132 channel matrix, 75 ohm source with all channels at +15 dBmV, assuming power match. Load as in Figure 11 & Figure 12, all gain settings, 132 channel matrix, 75 ohm source with all channels at +15 dBmV, assuming power match.
12
SEMICMF.019
Data Sheet
Absolute Maximum Ratings All voltages are referred to Vee at 0V
Characteristic Supply voltage RF input voltage All I/O port DC offsets Storage temperature Junction temperature Package thermal resistance, chip to ambient Power consumption at 5.25V ESD protection 1.5 -0.3 -55 min -0.3 max 6 8 Vcc+0.3 150 125 35 1155
o
SL2150D
units V dBm V
o o
conditions
Differential
C C Power applied Paddle to be soldered to ground plane
C/W
mW kV Mil-std 883B method 3015 cat1
SEMICMF.017
13
SL2150D
4.0 SL2150D Demonstration Board
Data Sheet
The SL2150D demonstration board is designed to allow testing of device functionality as a stand alone power splitter. It allows for testing of the AGC function and independent testing of all channels. The SL2150D is designed to interface differentially into a silicon tuner such as the SL2101 with simple inductive or resistive pull-ups. However to facilitate testing the differential output is converted to a single ended signal through a balun, the differential conversion is necessary for achieving second order performance. All outputs require a DC return path to Vcc to prevent output saturation. This can be provided by the balun, inductive pull up or resistive pull up. In the case of a resistive pull up the maximum load value is 20. The balun also provides the DC bias to the outputs; all outputs have to be DC 'shorted' to Vcc to prevent saturation of the output stages. All input and output terminations are 75. The board schematic and board layouts are contained in Figure 15 and Figures 16-19 respectively. Operation note The supply voltage must be connected and enabled before any AGC or disable voltage is applied unless these supplies currents are limited to <1 mA or else permanent damage may occur through the ESD structures on the device.
4.1
Pin Connections
All references are with the board oriented as in bottom view on figure (2). Pin 1 of the header is defined as the left-hand pin.
4.1.1
Power supply
A single 5V supply is required. Power is supplied through the two-pin header PL1, located top right hand corner. Pin 1 2 Function Vcc Vee
4.1.2
RF input
The RF input F type, SK1, is located on the right hand side of the board.
4.1.3
RF outputs
Output 1 is the F type connector, SK2, located at the top of the board. Output 2 is the F type connector, SK5, located at the bottom of the board
4.1.4
AGC & Disable control
AGC & Disable controls are connected through the 5-pin header, PL2, located in the bottom right hand corner. See note on connection of supplies in power supply section. Pin allocation is as follows:
14
SEMICMF.019
Data Sheet
Pin 1 2 3 4 5 Function Disable 1 Disable 2 Vagc 1 Vagc 2 Vee
SL2150D
AGC control voltage is Vee to 3V for minimum to maximum gain setting. Disable control voltage is 0V for enable, 3V for disable.
4.2 4.2.1
Test Procedure CSO
CSO is tested using an RDL matrix generator set to deliver all channels from 55.25 MHz to 859.25 MHz at 15 dBmV per carrier. Each output is tested independently over maximum gain setting through 15 dB of gain reduction. The output intermodulation is monitored on a spectrum analyzer with video bandwidth of 1 kHz and resolution bandwidth of 10 kHz. To avoid intermodulation in the test set up the output channel is filtered through a narrow band filter and then amplified to compensate for insertion loss. The higher of all CSO beats is recorded. Under gain reduction the amplitude is normalized to channel 2 output at the required AGC onset
4.2.2
CTB
CTB is tested using an RDL matrix generator set to deliver all channels from 55.25 MHz to 859.25 MHz at 15 dBmV per carrier. Each output is tested independently over maximum gain setting through 15 dB of gain reduction. The output intermodulation is monitored on a spectrum analyzer with video bandwidth of 1 kHz and resolution bandwidth of 10 kHz. To minimize intermodulation in the test set up the output channel is filtered through a narrow band filter and then amplified to compensate for insertion loss. CTB is measured with N+-1 also disabled since these channels were found to produce intermodulation in the filter and the post amplifier. Under gain reduction the amplitude is normalized to channel 2 output at the required AGC onset.
4.2.3
CXM
CTB is tested using an RDL matrix generator set to deliver all channels from 55.25 MHz to 859.25 MHz at 15 dBmV per carrier with 100% modulation at line rate. Each output is tested independently over maximum gain setting through 15 dB of gain reduction. To minimize cross modulation in the test set up the output channel is filtered through a narrow band filter and then amplified to compensate for insertion loss. The amplifier output is then demodulated on a first spectrum analyzer set to linear mode with maximum resolution and video bandwidth. The video out of the first spectrum analyzer, which will be the demodulated AM on the carrier, is connected to a second spectrum analyzer centred on line rate frequency with video averaging enabled. The cross modulation can then be monitored on the second spectrum
SEMICMF.017
15
SL2150D
analyzer.
Data Sheet
The CXM is measured with modulation disabled on N+-1 since these channels were found to produce cross modulation in the filter and the post amplifier. Under gain reduction the amplitude is normalized to channel 2 output at the required AGC onset.
4.2.4
Gain
Gain is measured using a network analyzer with 50/75 pads to ensure correct source and load impedance.
4.2.5
AGC
Output amplitude at a given channel is measured on a spectrum analyzer with all AGC settings from 0V to Vcc.
4.2.6
S11
S11 is measured at the test board RF input F type connector, using a network analyzer calibrated to 75 F type connector.
4.2.7
S22
S22 is not measured since the device is not designed to be impedance matched on its output. Rather the output load is used as the terminating impedance for the device.
4.2.8
NF
NF is measured using a NF meter with a 50/75 pad on the input.
16
SEMICMF.019
Data Sheet
2 1 Vcc 5 C1 C2 100nF 100nF 100nF 4 C3 C4 C27 C6 28 27 26 25 24 23 22 C7 IC 1 CNR Corner Vcc Vcc Vcc RFOUT4B RFOUT4 Vee Vee C19 1nF 1 TX5 4 5 MABAES0029 L1 5.1nH C20 1nF 3 5 4 3 1 Paddle SL2150F 8 9 10 11 12 13 14 PAD C25 1nF SK4 FTYPE TX2 MABAES0029 3 Vcc 1 Vcc TX3 MABAES0029 5 4 C9 100nF C32 100pF C31 100pF C8 100nF 21 20 19 18 17 16 15 RFOUT1B RFOUT1 Vee Vee Vee RFOUT2 RFOUT2B 100nF 100nF 470nF 100nF TX1 MABAES0029 1 3 Vcc C5 100nF C30 100pF C24 1nF C23 1nF
C11 100nF
C13 C10 1 2 3 4 5 MOLEX5 100nF C14 C15
100nF 3 100nF 100nF 1 TX4 MABAES0029 5 4
AGC3 AGC4 Vee RFOUT3B RFOUT3 Vee Vee
SEMICMF.017
PL1 MOLEX2 SK2 FTYPE SK3 FTYPE 1 2 3 4 5 6 7 Vcc Vcc RFINPUTB RFINPUT Vee AGC1 AGC2 Vcc C33 100pF C18 100nF C26 1nF SK5 FTYPE PL2 C12 C16 C17 100nF 100nF 100nF
Figure 15 - SL2150D evaluation PCB Schematic
SK1 FTYPE
SL2150D
17
SL2150D
Data Sheet
Figure 16 - SL2150D evaluation PCB (Top View)
Figure 17 - SL2150D evaluation PCB (Layer 2 view)
18
SEMICMF.019
Data Sheet
SL2150D
Figure 18 - SL2150D evaluation PCB (Layer 3 view)
Figure 19 - SL2150D evaluation PCB (Bottom View Mirrored)
SEMICMF.017
19
SL2150D
Data Sheet
20
SEMICMF.019
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