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TC94A14F/FA/FB
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC94A14F,TC94A14FA,TC94A14FB
Digital Servo Single-Chip Processor for Use in CD Player
TC94A14F/FA/FB is a single-chip processor which incorporates the following functions: sync separation protection, interpolation, EFM decoder, error correction, micro controller interface, digital equalizer for use in servo LSI, and servo control circuit. TC94A14F/FA/FB also incorporates a 1-bit DA converter. Combining TC94A14F/FA/FB with digital servo head amp TA2157F/FN enables very simple and completely adjustment-free CD player systems.
TC94A14F
Features
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * Capable of decoding the text data. Sync pattern detection, sync signal protection, and synchronization can be made correctly. Built-in EFM demodulation circuit and sub code demodulation. Capable of correcting dual C1 correction and quadruple C2 correction using the CIRC correction theoretical format. The TC94A14F/FA/FB respond to variable playback system. Jitter absorbing capacity of 6 frame. Built-in 16 KB RAM. Built-in digital out circuit. Built-in L/R independent digital attenuator. Audio output responds to bilingual function. Output format for audio out can be selected 32fs, 48fs or 64fs modes. Read-timing-free sub code Q data and capable of synchronous output with audio data. Built-in data slicer and analog PLL (adjustment-free VCO). Capable of automatic adjustment function of focus and tracking servos for loop gain, offset and balance. Built-in RF gain automatic adjustment circuit. Built-in digital equalizer for phase compensation. Built-in focus and tracking servo control circuit. Search control corresponds to every mode and can realize high speed and stable search. Lens-kick and feed-kick are using speed-controlled form. Built-in AFC and APC circuits for CLV servo of disc motor. Built-in anti-defect and anti-shock circuit. Built-in 8 times over sampling digital filter and 1-bit DA converter. Built-in analog filter for 1-bit DA converter. Built-in zero data detection output circuit. The TC94A14F/FA capable of 4 times speed operation. Built-in micro controller interface circuit. CMOS silicon structure and high speed, low power consumption. 64-pin flat package. Weight QFP64-P-1414-0.80A: 0.5 g (typ.) LQFP64-P-1010-0.50: 0.4 g (typ.) QFP64-P-1212-0.65: 0.45 g (typ.)
TC94A14FB TC94A14FA
Built-in RAM for digital equalizer for coefficient, and capable of variable pickup.
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Block Diagram (top view)
XVDD3 XVSS3 TESIN AVDD3 RFGC TEBC VDD3 VSS3 VREF DMO FMO FOO 33 32 TEZI Clock generator 31 TEI D/A 30 SBAD LPF 1-bit DAC 29 FEI Servo control A/D 28 RFRP 27 RFZI ROM RAM Digital equalizer automatic adjustment circuit 26 RFCT 25 AVDD3 24 RFI 23 SLCO 22 AVSS3 VCO 21 VCOF 20 PVREF Sub code decoder PLL TMAX 19 LPFO 18 LPFN 17 TMAX 1 BCK 2 LRCK 3 AOUT 4 DOUT 5 IPF 6 VDD3 7 VSS3 8 SBOK 9 CLCK 10 DATA 11 SFSY 12 SBSY 13 IO0 14 IO1 15 PVDD3 16 PDO
48 DVSS3 49 RO 50 DVDD3 51 DVR 52 LO 53 DVSS3 54 ZDET 55 VSS5 56
47
46
45
44
43
42
41
40
39
38
37
36
35
34
PWM
Address circuit
Correction circuit
BUS0 57 BUS1 58 BUS2 59 BUS3 60 BUCK 61 /CCE 62 /RST 63 VDD5 64 Microcontroller interface
16 k RAM
CLV servo
Data slicer
Synchronous guarantee EFM decoder Audio out circuit Digital output
TRO
SEL
XO
XI
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Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol BCK LRCK AOUT DOUT IPF VDD3 VSS3 SBOK CLCK DATA SFSY SBSY IO0 IO1 PVDD3 PDO I/O O 3-5I/F O 3-5I/F O 3-5I/F O 3-5I/F O 3-5I/F 3/4 3/4 O 3-5I/F I/O 3-5I/F O 3-5I/F O 3-5I/F O 3-5I/F I/O 3-5I/F 3/4 O AI/F Function Description Bit clock output pin. 32fs, 48fs, or 64fs selectable by command. L/R channel clock output pin. "L" for L channel and "H" for R channel. Output polarity can be inverted by command. Audio data output pin. MSB-first or LSB-first selectable by command. Digital data output pin. Outputs up to double-speed playback. Remarks Normal speed: 32fs = 1.4112 MHz Normal speed: 44.1 kHz 3/4 Based on CP-1201
Correction flag output pin. When set to "H", AOUT output cannot Alias: C2PO be corrected by C2 correction processing. Digital 3.3 V power supply voltage pin. Digital GND pin. Subcode Q data CRCC result output pin. "H" level when result is OK. Subcode P-W data read clock I/O pin. I/O polarity selectable by command. Subcode P-W data output pin. Playback frame sync signal output pin. Subcode block sync signal output pin. "H" level at S1 when subcode sync is detected. General-purpose input / output pins. Input port at reset. Schmitt input 3/4 3/4 3/4 3/4 3/4 3/4
Schmitt at input
PLL-only 3.3 V power supply voltage pin. EFM and PLCK phase difference signal output pin. TMAX detection result output pin. TMAX Detection Result TMAX Output "PVDD3" "HiZ" "AVSS3" Analog input Analog output
3/4 4-state output (PVDD3, HiZ, PVREF, AVSS3)
17
TMAX
O AI/F
Longer than fixed period Within fixed period Shorter than fixed period
3-state output (PVDD3, HiZ, AVSS3)
18 19 20 21 22 23 24 25
LPFN LPFO PVREF VCOF AVSS3 SLCO RFI AVDD3
I AI/F O AI/F 3/4 O AI/F 3/4 O AI/F I AI/F 3/4
Inverted input pin for PLL LPF amp. Output pin for PLL LPF amp. PLL-only VREF pin. VCO filter pin. Analog GND pin. DAC output pin for data slice level generation. RF signal input pin. Zin selectable by command. Analog 3.3 V power supply voltage pin.
3/4 Analog output 3/4 Analog output Analog input 3/4
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Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Symbol RFCT RFZI RFRP FEI SBAD TEI TEZI FOO TRO VREF RFGC TEBC SEL AVDD3 FMO DMO VSS3 VDD3 TESIN XVSS3 XI XO XVDD3 DVSS3 RO DVDD3 DVR LO DVSS3 I/O I AI/F I AI/F I AI/F I AI/F I AI/F I AI/F I AI/F O AI/F O AI/F 3/4 O AI/F O AI/F O AI/F 3/4 O AI/F O AI/F 3/4 3/4 I 3I/F 3/4 I AI/F O AI/F 3/4 3/4 O AI/F 3/4 3/4 O AI/F 3/4 Function Description RFRP signal center level input pin. RFRP signal zero-cross input pin. RF ripple signal input pin. Focus error signal input pin. Sub-beam adder signal input pin. Tracking error input pin. Inputs when tracking servo is on. Tracking error signal zero-cross input pin. Focus equalizer output pin. Tracking equalizer output pin. Analog reference power supply voltage pin. RF amplitude adjustment control signal output pin. Tracking balance control signal output pin. APC circuit ON/OFF signal output pin. At laser on, high impedance with UHS = "L", H output with UHS = "H". Analog 3.3 V power supply voltage pin. Feed equalizer output pin. Disc equalizer output pin. Digital GND pin. Digital 3.3 V power supply voltage pin. Test input pin. Normally, fixed to "L". System clock oscillator GND pin. System clock oscillator input pin. System clock oscillator output pin. System clock oscillator 3.3 V power supply voltage pin. DA converter GND pin. R-channel data forward output pin. DA converter 3.3 V power supply pin. Reference voltage pin. L-channel data forward output pin. DA converter GND pin. Analog output (AVSS3~AVDD3) Remarks Analog input: Zin = 33 kW Analog input Analog input Analog input Analog input Analog input Analog input: Zin = 10 kW
3/4 3-state output (PWM carrier = 88.2 kHz) (AVDD3, VREF, AVSS3) 3-state output 3/4 3-state output (PWM carrier = 88.2 kHz) (AVDD3, VREF, AVSS3)
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
3/4
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Pin No. 55 56 57 58 59 60 61 62 63 64 Symbol ZDET VSS5 BUS0 BUS1 BUS2 BUS3 BUCK /CCE /RST VDD5 I 3-5I/F I 3-5I/F I 3-5I/F 3/4 Microcontroller interface clock input pin. Microcontroller interface chip enable signal input pin. At "L", BUS0 to BUS3 are active. Reset signal input pin. At reset, "L". Microcontroller interface 5 V power supply pin. Schmitt input Schmitt input Built-in pull-up resistor 3/4 Schmitt input Microcontroller interface data I/O pins. CMOS ports I/O O 3-5I/F 3/4 Function Description 1 bit DA converter zero data detection flag output pin. Microcontroller interface GND pin. Remarks 3/4 3/4
I/O 3-5I/F
Note: AI/F: analog input/output pin 3-5I/F: 3-5 interface built-in pin (5 V input/output pin) 3I/F: 3 V input/output pin
Maximum Ratings (unless otherwise specified, GND reference, Ta = 25C)
Characteristics Symbol VDD5 Rating -0.3~6.0 Unit Remarks 64-56 pin 6-7 pin Power supply voltage VDD3 V 15, 25, 39-22 pin 43-42 pin 48-45 pin 51-49, 54 pin Input voltage VIN5 VIN3 -0.3~ VDD5 + 0.3 -0.3~ VDD3 + 0.3 1910 Power dissipation PD 1000 1310 Operating temperature Storage temperature Topr Tstg -40~+85 -55~+150 C C mW 9, 13, 14, 57~63 pin V 18, 24, 26~32, 44 pin TC94A14F TC94A14FA TC94A14FB
-0.3~4.5
3/4 3/4
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Electrical Characteristics DC Characteristics (1)
(unless otherwise specified, VDD5 = 5 V, VDD3 = AVDD3 = DVDD3 = XVDD3 = PVDD3 = 3.3 V, Ta = 25C)
Characteristics Symbol VDD5 VDD3 Operating power supply voltage AVDD3 DVDD3 XVDD3 PVDD3 Normal speed Operating power supply current Double speed 4 times speed "H" level Input voltage 1 "L" level "H" level Input current 1 "L" level "H" level Tri-state leak current 1 "L" level "H" level "L" level Output current 1 "H" level "L" level "H" level Input voltage 2 "L" level "H" level Input current 2 "L" level "H" level Tri-state leak current 2 "L" level "H" level "L" level "H" level Output current 2 "L" level "H" level "L" level VREF output on resistance Pull-up resistance IDD5 (1) IDD3 (1) IDD5 (2) IDD3 (2) IDD5 (3) IDD3 (3) VIH5 VIL5 IIH5 IIL5 ITLH5 ITLL5 IOH5 (1) IOL5 (1) IOH5 (2) IOL5 (2) VIH3 VIL3 IIH3 IIL3 ITLH3 ITLL3 IOH3 (1) IOL3 (1) IOH3 (2) IOL3 (2) IOH3 (3) IOL3 (3) RON RUP RO1 Pin built-in output resistance RO2 3/4 Pins grouped as 6 and 7 in the following table 3/4 3.3 3/4 Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 CMOS input pins except for analog input pins (5 V) VIH5 = 5 V VIL5 = 0 V VIH5 = 5 V VIL5 = 0 V Pins grouped as 1, 2, 3 in the following table XI = 16.9344 MHz Test Condition 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.5 3/4 3/4 -1.0 3/4 -1.0 3/4 2.0 3/4 4.0 2.3 3/4 3/4 -1.0 Pins grouped as 4 and 5 in the following table 3/4 -1.0 3/4 2.0 2 30 2.5 35 3 40 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 -80 80 -121 121 3/4 50 5.0 5 50 6 mA 60 7 70 3/4 1.5 1.0 3/4 1.0 3/4 -2.0 3/4 -4.0 3/43/4 1.0 1.0 3/4 1.0 3/4 -2.0 3/4 mA V mA mA V 3.0 3.3 3.6 V Min 4.5 Typ. 5.0 Max 5.5 Unit
mA
VOH5 = 4.6 V Pins grouped as 1 in V = 0.4 V the following table
OL5
VOH5 = 4.6 V Pins grouped as 2 and 3 in the VOL5 = 0.4 V following table CMOS input pins except for analog input pins (3 V) VIH3 = 3.3 V VIL3 = 0 V VIH3 = 3.3 V VIL3 = 0 V
mA
VOH3 = 2.9 V Pins grouped as 4 in V = 0.4 V the following table
OL3
mA
VOH3 = 2.9 V Pins grouped as 5 in V = 0.4 V the following table
OL3
3/4 3/4 3/4 3/4
3/4 25 3/4
3/4 3/4 3/4 3/4
500 75 3/4 kW W kW mA
VOH3 = 2.9 V Pins grouped as 6 in V = 0.4 V the following table
OL3
3/4 Pins grouped as 8 in the following table Pins grouped as 5 in the following table
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DC Characteristics (2)
(unless otherwise specified, VDD5 = VDD3 = AVDD3 = DVDD3 = XVDD3 = PVDD3 = 3.3 V, Ta = 25C)
Characteristics Symbol VDD5 VDD3 Operating power supply voltage AVDD3 DVDD3 XVDD3 PVDD3 Normal speed Operating power supply current Double speed 4 times speed "H" level Input voltage "L" level "H" level Input current "L" level "H" level Tri-state leak current "L" level "H" level "L" level "H" level "L" level Output current "H" level "L" level "H" level "L" level "H" level "L" level VREF output on resistance Pull-up resistance IDD3 (1) Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Test Condition 3/4 3/4 3/4 3/4 3/4 3/4 3/4 32 55 3.0 3.3 3.6 V Min Typ. Max Unit
IDD3 (2)
3/4
XI = 16.9344 MHz
3/4
37.5
66
mA
IDD3 (3) VIH3 VIL3 IIH3 IIL3 ITLH3 ITLL3 IOH3 (1) IOL3 (1) IOH3 (2) IOL3 (2) IOH3 (3) IOL3 (3) IOH3 (4) IOL3 (4) IOH3 (5) IOL3 (5) RON RUP RO1
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 CMOS input pins except for analog input pins (3 V) VIH3 = 3.3 V VIL3 = 0 V VIH3 = 3.3 V VIL3 = 0 V Pins grouped as 4 and 5 in the following table
3/4 2.3 3/4 3/4 -1.0 3/4 -1.0 3/4 1.0 3/4 2.0 3/4 2.0
43 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 -80 80 -121 121 3/4 80 5.0 3.3
77 3/4 1.0 1.0 3/4 1.0 3/4 -1.0 3/4 -2.0 3/4-2.0 3/4 mA mA mA
V
mA
VOH3 = 2.9 V Pins grouped as 1 in V = 0.4 V the following table
OL3
VOH3 = 2.9 V Pins grouped as 2 and 3 in the VOL3 = 0.4 V following table VOH3 = 2.9 V Pins grouped as 4 in V = 0.4 V the following table
OL3
VOH3 = 2.9 V Pins grouped as 5 in V = 0.4 V the following table
OL3
3/4 3/4 3/4 3/4
3/4 50 3/4 3/4
3/4 3/4 3/4 3/4
500 120 3/4 kW 3/4 W kW mA
VOH3 = 2.9 V Pins grouped as 6 in V = 0.4 V the following table
OL3
3/4 Pins grouped as 8 in the following table Pins grouped as 5 in the following table Pins grouped as 6 and 7 in the following table
Pin built-in output resistance RO2
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Pin Group 1 2 3 4 5 6 7 8 Pin Name SBOK, SFSY, SBSY, IO0, IO1, ZDET BCK, LRCK, AOUT, DOUT, IPF, CLCK, DATA BUS3, BUS2, BUS1, BUS0 SEL, TMAX PDO RFGC, TEBC, FMO, DMO FOO, TRO /RST
AC Characteristics
(unless otherwise specified, VDD5 = 5 V, VDD3 = AVDD3 = DVDD3 = XVDD3 = PVDD3 = 3.3 V, Ta = 25C) 1. Microcontroller Interface Timing
Characteristics /CCE = "H" pulse width Data disable time /CCE, BUCK delay time BUCK, /CCE delay time BUCK = "L" pulse width BUCK = "H" pulse width (1) BUCK = "H" pulse width (2) BUCK = "H" pulse width (3) BUCK = "H" pulse width (4) Write data setup time Write data hold time Data disable time Read data access time Symbol tCC tSZ1 tCB tBC tBLW tBLW tBHW tBHW tBHW tBHW tWS tWH tSZ2 tRD Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Test Condition 3/4 BUCK rise reference /CCE fall reference BUCK rise reference Write, SRC mode QDRC mode Write, SRC mode QDRC mode (normal speed) QDRC mode (double speed) QDRC mode (4 speed) BUCK rise reference BUCK rise reference BUCK fall reference BUCK fall reference Min 120 0 0 0 120 240 120 3000 1500 800 60 20 0 0 Typ. 3/4 3/4 3/4 Max 3/4 3/4 3/4 Unit
3/4
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
3/4
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 ns
(1)
Write command mode
tCB tBC tCC
/CCE tBLW tBHW BUCK tSZ2 BUSi (input) tWS CM tWH CL Write mode DM DL
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(2) Write command mode: Bxxxxx, Fxxxxx commands
tCB /CCE tBLW tBHW BUCK tSZ2 BUSi (input) tWS CM tWH CL Write mode DM DL EM EL tBC tCC
(3)
Read command mode
tCB tBC tCC
/CCE tBLW tBHW BUCK tSZ2 BUSi (input) tWS CM tRD BUSi (input) tSZ1 RDO Read mode RDn tWH
2. AOUT Data Output Timing
Characteristics Transfer time (1) "H" level "L" level "H" level Transfer time (2) "L" level tpHL2 tpLH2 tpHL2 Symbol tpLH1 tpHL1 tpLH2 Test Circuit 3/4 3/4 3/4 3/4 LRCK Test Condition Min 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 Max 5 5 5 5 ns Unit
AOUT
tpHL1 tpLH1
BCK
LRCK
AOUT
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3. DATA, CLCK Input/Output Timing
(1) CLCK input mode (regardless of setting of HS and UHS bits of SPEED command)
Characteristics Clock pulse width Input setup time Transfer time (1) "L" level "H" level "L" level Transfer time (2) "H" level "L" level "H" level "L" level Symbol tHW tLW tSU tpHL1 tpLH52 tpHL52 tpLH52 tpHL52 Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Test Condition CLCK input mode CLCK input mode CLCK input mode CLCK input mode Min 50 50 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 3/4 3/4 3/4 5 ns 15 15 20 20 Unit
VDD5 = 3.3 V
tpHL1 SFSY tSU CLCK tHW
tpHL52, tpLH52 tpHL32, tpLH32
tLW
DATA
SUBP
SUBQ
(2)
CLCK output mode (tHW, tLW, tpLH3 only, 1/n at n speed)
Characteristics Symbol "H" level "L" level tHW tLW tpHL1 tpLH52 tpHL52 tpLH32 tpHL32 tpLH3 Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Test Condition CLCK output mode CLCK output mode CLCK output mode Min 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 950 950 5 15 15 20 20 850 ns Unit
Clock pulse width Transfer time (1)
"L" level "H" level "L" level
Transfer time (2) "H" level "L" level Transfer time (3) "H" level
VDD5 = 3.3 V CLCK output mode
tpHL1 SFSY tpLH3 CLCK tHW
tpHL52, tpLH52 tpHL32, tpLH32
tLW
DATA
SUBP
SUBQ
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4. SBSY, SBOK Input/Output Timing
Characteristics Transfer time (1) "H" level "L" level "H" level Transfer time (2) "L" level tpHL2 Symbol tpLH1 tpHL1 tpLH2 Test Circuit 3/4 3/4 3/4 3/4 SBSY Test Condition Min 3/4 3/4 3/4 3/4 tpHL1 Typ. 3/4 3/4 3/4 3/4 Max 5 10 15 20 ns Unit
SBOK
tpLH1 SFSY tpLH2 tpHL2 SBSY
SBOK
5. Output Pin Timing
Characteristics Output rise time 5 (1) Output fall time 5 (1) Output rise time 3 (1) Output fall time 3 (1) Output rise time 5 (2) Output fall time 5 (2) Output rise time 3 (2) Output fall time 3 (2) Output rise time 5 (3) Output fall time 5 (3) Output rise time 3 (3) Output fall time 3 (3) Output rise time 5 (4) Output fall time 5 (4) Symbol tor51 tof51 tor31 tof31 tor52 tof52 tor32 tof32 tor53 tof53 tor33 tof33 tor54 tof54 3/4 3/4 3/4 VDD5 = 3.3 V 3/4 VDD5 = 3.3 V 3/4 VDD5 = 3.3 V Test Circuit Test Condition Pins grouped as 1 below Min 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 7 12 14 24 7 7 14 14 7 7 14 14 10 10 ns Unit
Pins grouped as 2 below
Pins grouped as 3 below
Pins grouped as 4 below
Pin Group 1 2 3 4
Pin Name SBOK, SFSY, SBSY, IO0, IO1, ZDET BCK, LRCK, AOUT, DOUT, IPF, CLCK, DATA BUS3, BUS2, BUS1, BUS0 TMAX, SEL
VOH VOH/2 VSS tor tof
90%
10%
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Analog Circuit Characteristics
1. AD Converter
Characteristics Resolution FE TE Sampling frequency SBAD RFRP Conversion input range Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 AVSS = 0 V AVDD3 = 3.3 V 3/4 Test Condition 3/4 Min 3/4 3/4 3/4 3/4 3/4 0.15 AVDD3 Typ. 8 176.4 176.4 88.2 176.4 3/4 Max 3/4 3/4 3/4 3/4 3/4 0.85 AVDD3 V kHz Unit bit
2. DA Converter (focus and tracking equalizer output)
Characteristics Number of bits Sampling frequency Signal output range Test Circuit 3/4 3/4 3/4 Test Condition 3/4 3/4 AVSS = 0 V, AVDD3 = 3.3 V Min 3/4 3/4 AVSS3 Typ. 3/4 3/4 3/4 Max 5 2.8 AVDD3 Unit bit MHz V
3. PLL Filter Amp
Characteristics I/O signal range Frequency characteristic Test Circuit 3/4 3/4 Test Condition 3/4 -3dB point (Gain = 1) Min AVSS3 3/4 Typ. 3/4 8 Max PVDD3 3/4 Unit V MHz
4. VCO (PLL)
Characteristics Center oscillation frequency Frequency variable range Test Circuit 3/4 3/4 3/4 Test Condition LPFO = VREF [VCOGSL] bit = "L" [VCOGSL] bit = "H" Min 3/4 3/4 3/4 Typ. 34 50 60 Max 3/4 3/4 3/4 Unit MHz %
5. TEZI Signal Comparator
Characteristics Input range Hysteresis voltage Test Circuit 3/4 3/4 Test Condition 3/4 VREF reference Min AVSS3 3/4 Typ. 3/4 50 Max AVDD3 3/4 Unit V mV
6. RFZI Signal Comparator
Characteristics Input range Hysteresis voltage Test Circuit 3/4 3/4 Test Condition 3/4 VREF reference Min AVSS3 3/4 Typ. 3/4 50 Max AVDD3 3/4 Unit V mV
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7. Data Slicer Circuit
(1) Comparator
Characteristics Input amplitude Test Circuit 3/4 Test Condition VREF reference Min 0.6 Typ. 1.2 Max 2.0 Unit Vpp
(2)
R-2R DAC (digital slicer DAC)
Characteristics Test Circuit 3/4 3/4 Test Condition 3/4 3/4 Min AVSS3 3/4 Typ. 3/4 2.5 Max AVDD3 3/4 Unit V kW
Output conversion range Output impedance
8. Audio DAC Characteristics
Characteristics Total harmonic distortion + noise Symbol THD + N (1) THD + N (2) S/N (1) S/N ratio S/N (2) Dynamic range Cross talk Analog output amplitude DR CT DAC out 1 1 1 1 Test Circuit 1 Test Condition 1 kHz sine wave, full-scale input 10 kHz sine wave, full-scale input Internal Zero detect = OFF Internal Zero detect = ON 1 kHz sine wave, -60dB input conversion 1 kHz sine wave, full-scale input 1 kHz sine wave, full-scale input Min 3/4 3/4 87 95 85 3/4 790 Typ. -88 -80 92 100 90 -90 820 Max -80 -75 3/4 3/4 3/4 -85 850 Unit dB
dB
dB dB mVrms
Test Circuit 1: Application circuit is used.
TC94A14F/FA/FB application circuit Lout Rout 20 kHz ideal LPF Distortion meter
LPF: Filter with built-in Shibasoku 725D Distortion meter: Shibasoku 725D equivalent Characteristic THD + N, CT S/N, DR Distortion Filter Setting A-weight OFF ON A-weight: IEC-A equivalent
Application Circuit
TC94A14F/FA/FB DVSS3 3.3 V RO XVDD3 XI 1 M9 16.9344 MHz DVDD3 22 mF DVR XO XVSS3 LO DVSS3 270 W 3.3 mF 2200 pF 10 k9 L-ch analog output 270 W 3.3 mF 10 k9 3.3 V 2200 pF R-ch analog output
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Package Dimensions
Weight: 0.5 g (typ.)
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Package Dimensions
Weight: 0.4 g (typ.)
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Package Dimensions
Weight: 0.45 g (typ.)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
17
2002-11-18

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