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| Y2310 Z PRELIMINARY CY2310ANZ 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs Features * One input to 10 output buffer/driver * Supports up to four SDRAM SO-DIMMs * Two additional outputs for feedback * I2CTM interface for output control * Low skew outputs * Up to 100 MHz operation * Multiple VDD and VSS pins for noise reduction * Dedicated OE pin for testing * Space-saving 28-pin SSOP package * 3.3V operation Functional Description The CY2310ANZ is a 3.3V buffer designed to distribute high-speed clocks in mobile PC applications. The part has 10 outputs, 8 of which can be used to drive up to four SDRAM SO-DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium II(R) processors. The CY2310ANZ can be used in conjunction with the CY2281 or similar clock synthesizer for a full Pentium II motherboard solution. The CY2310ANZ also includes an I2C interface which can enable or disable each output clock. On power-up, all output clocks are enabled. A separate Output Enable pin facilitates testing on ATE. Block Diagram Pin Configuration 28-pin SSOP Top View SDRAM0 SDRAM1 SDRAM2 SDRAM3 V DD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD SDRAM8 VSS VDDIIC SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 BUF_IN SDATA I2C Decoding SCLOCK SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 VDD SDRAM7 SDRAM6 VSS VDD SDRAM5 SDRAM4 VSS OE VDD SDRAM9 VSS VSSIIC SCLOCK OE Intel and Pentium II are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 September 4, 1998 PRELIMINARY Pin Summary Name VDD VSS VDDIIC VSSIIC BUF_IN OE SDATA SCLK SDRAM [0-3] SDRAM [4-7] SDRAM [8-9] Pins 1, 5, 10, 19, 24, 28 4, 8, 12, 17, 21, 25 13 16 9 20 14 15 2, 3, 6, 7 22, 23, 26, 27 11, 18 Description 3.3V Digital voltage supply Ground I2C Voltage supply Ground for I2C Input clock CY2310ANZ Output Enable, three-states outputs when LOW. Internal pull-up to VDD I2C data input, internal pull-up to VDD I2C clock input, internal pull-up to VDD SDRAM byte 0 clock outputs SDRAM byte 1 clock outputs SDRAM byte 2 clock outputs Device Functionality OE 0 1 SDRAM [0-17] High-Z 1 x BUF_IN Serial Configuration Map * The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved and unused bits should be programmed to "0". * I2C Address for the CY2310ANZ is: Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 27 26 23 22 ----Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Initialize to 0 Initialize to 0 Initialize to 0 Initialize to 0 A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ---- Byte 0:SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enabled Bit Pin # Initialize to 0 Initialize to 0 Initialize to 0 Initialize to 0 SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Description Bit 7 -Bit 6 -Bit 5 -Bit 4 -Bit 3 7 Bit 2 6 Bit 1 3 Bit 0 2 Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 18 11 ------Description SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 2 PRELIMINARY Maximum Ratings Supply Voltage to Ground Potential............... -0.5V to +7.0V DC Input Voltage (Except BUF_IN) .......-0.5V to VDD + 0.5V DC Input Voltage (BUF_IN) ........................... -0.5V to +7.0V Storage Temperature .................................-65C to +150C CY2310ANZ Max. Soldering Temperature (10 sec.) ....................... 260C Junction Temperature ................................................ 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions Parameter VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Description Min. 3.135 0 20 Max. 3.465 70 30 7 Unit V C pF pF Electrical Characteristics Parameter VIL VILiic VIH IIL IIL IIH VOL VOH IDD IDD IDD IDD IDDS Description Input LOW Voltage Input LOW Voltage Input HIGH Voltage[1] Input LOW Current (BUF_IN input) Input LOW Current (Except BUF_IN Pin) Input HIGH Current Output LOW Voltage[2] Output HIGH Voltage Supply Current Supply Current Supply Current[2] Supply Current Supply Current [2] [2] [1] 2 Test Conditions Except I C pins For I C pins only 2 Min. Max. 0.8 0.7 Unit V V V A A A V V mA mA mA mA A 2.0 VIN = 0V VIN = 0V VIN = VDD IOL = 25 mA IOH = -36 mA Unloaded outputs, 100 MHz Loaded outputs, 100 MHz Unloaded outputs, 66.67 MHz Loaded outputs, 66.67 MHz BUF_IN=VDD or VSS All other inputs at VDD 2.4 200 360 150 230 500 -10 -10 10 100 10 0.4 Notes: 1. BUF_IN input has a threshold voltage of VDD/2. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3 PRELIMINARY Switching Characteristics[3] Parameter Name Maximum Operating Frequency Duty Cycle[2,4] = t2 / t1 t3 t4 t5 t6 t7 t8 t9 Rising Edge Rate [2] [2] [2] CY2310ANZ Test Conditions Measured at 1.5V Measured between 0.4V and 2.4V Measured between 2.4V and 0.4V All outputs equally loaded Input edge greater than 1V/ns Input edge greater than 1V/ns Input edge greater than 1V/ns Input edge greater than 1V/ns Min. 45.0 0.9 0.9 1.0 1.0 1.0 1.0 Typ. 50.0 1.5 1.5 150 3.5 3.5 5 20 Max. 100 55.0 4.0 4.0 250 5.0 5.0 12 30 Unit MHz % V/ns V/ns ps ns ns ns ns Falling Edge Rate Output to Output Skew SDRAM Buffer LH Prop. Delay[2] SDRAM Buffer HL Prop. Delay[2] SDRAM Buffer Enable Delay [2] [2] SDRAM Buffer Disable Delay Notes: 3. All parameters specified with loaded outputs. 4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns Switching Waveforms Duty Cycle Timing t1 t2 1.5V 1.5V 1.5V All Outputs Rise/Fall Time 2.4V 0.4V t3 2.4V 0.4V t4 3.3V 0V OUTPUT Output-Output Skew OUTPUT 1.5V OUTPUT t5 1.5V 4 PRELIMINARY Switching Waveforms (continued) SDRAM Buffer LH and HL Propagation Delay CY2310ANZ INPUT OUTPUT t6 t7 SDRAM Buffer Enable and Disable Times OE Three-State OUTPUTS t8 Active t9 Test Circuit VDD 0.1 F OUTPUTS CLK out CLOAD GND 5 PRELIMINARY Application Information Clock traces must be terminated with either series or parallel termination, as they are normally done. CY2310ANZ Application Circuit CY2310ANZ: 28-PIN SSOP Summary * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25), and Rseries is the series terminating resistor. Rseries > Rtrace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F-22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. 6 PRELIMINARY CY2310ANZ Ordering Information Ordering Code CY2310ANZPVC-1 Document #: 38-00659-A Package Name O28 Package Type 28-pin SSOP Operating Range Commercial Package Diagram 28-Lead (210-Mil) Shrunk Small Outline Package O28 51-85079-B (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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