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36
PRELIMINARY
CY7C1336
64K x 32 Synchronous Flow-Through 3.3V Cache RAM
Features
* Supports 66-MHz microprocessor cache systems with zero wait states * 64K by 32 common I/O * Low Standby Power (1.65 mW, L version) * Fast clock-to-output times -- 7.5 ns (117-MHz version) * Two-bit wraparound counter supporting either interleaved or linear burst sequence * Separate processor and controller address strobes provide direct interface with the processor and external cache controller * Synchronous self-timed write * Asynchronous Output Enable * 3.3V I/Os * JEDEC-standard pinout * 100-pin TQFP packaging * ZZ "sleep" mode
Functional Description
The CY7C1336 is a 3.3V 64K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit On-Chip Counter captures the first address in a burst and increments the address automatically for the rest of the burst access. The CY7C1336 allows both interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous Chip Enable input and an asynchronous Output Enable input provide easy control for bank selection and output three-state control.
Logic Block Diagram
CLK ADV ADSC ADSP A[15:0] GW BWE BW3 BW 2
MODE (A0,A1) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D D DQ[31:24] Q BYTEWRITE REGISTERS 14 16
16
14
64KX32 MEMORY ARRAY
D DQ[23:16] Q BYTEWRITE REGISTERS D Q DQ[15:8] BYTEWRITE REGISTERS Q DQ[7:0] BYTEWRITE REGISTERS
BW1 D BW 0 CE 1 CE 2 CE 3
32
32
D ENABLE Q CE REGISTER CLK INPUT REGISTERS CLK
OE ZZ SLEEP CONTROL DQ[31:0]
Selection Guide
7C1336-117 7C1336L-117 7.5 300 270 5.0 7C1336-100 7C1336L-100 8.0 260 235 5.0 7C1336-66 7C1336L-66 9.0 260 235 5.0
Maximum Access Time (ns) Maximum Operating Current (mA)
L Maximum Standby Current (mA) Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 March 3, 1999
PRELIMINARY
Pin Configuration
CY7C1336
100-Lead TQFP
OE ADSC BW1 BW0 CE1 CE2 CE3 VDD VSS ADSP ADV 84 83 BWE BW3 BW2 CLK GW
A6
A7
A8 82
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
NC DQ16 DQ17 VDDQ VSSQ DQ18 DQ19 BYTE2 DQ20 DQ21 VSSQ VDDQ DQ22 DQ23 VSSQ VDD NC VSS DQ24 DQ25 VDDQ VSSQ DQ26 DQ27 DQ28 DQ29 VSSQ VDDQ DQ30 DQ31 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 CY7C1336 pinout
100
81
A9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
NC DQ15 DQ14 VDDQ VSSQ DQ13 DQ12 DQ11 DQ10 VSSQ VDDQ DQ9 DQ8 VSS NC VDD ZZ DQ7 DQ6 VDDQ VSSQ DQ5 DQ4 DQ3 DQ2 VSSQ VDDQ DQ1 DQ0 NC BYTE1
BYTE3
BYTE0
MODE A5
A4
A3
A2
A1
A0
A14 A15
DNU DNU A10 A11
A12
DNU DNU
V SS
2
VDD
A13
NC
PRELIMINARY
Functional Description (continued)
Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE 1, CE2, and CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the RAM core. The write inputs (GW, BWE, and BW[3:0]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Description Table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. Byte writes are allowed. During byte writes, BW0 controls DQ[7:0], BW1 controls DQ[15:8], BW2 controls DQ[23:16], and BW3 controls DQ[31:24]. All I/Os are three-stated during a byte write. Since this is a common I/O device the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQ[31:0]. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE 1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[3:0]) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the Address Register, burst counter/control logic and delivered to the RAM core. The information presented to DQ[31:0] will be written into the specified address location. Byte writes are allowed. During byte writes, BW0 controls DQ[7:0], BW1 controls DQ[15:8], BW2 controls DQ[23:16], and BW3 controls DQ[31:24]. All I/Os are three-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQ[31:0]. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE 1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the Address Register, burst counter /control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at
CY7C1336
the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH.
Burst Sequences
The CY7C1336 provides an on-chip 2-bit wraparound burst counter inside the SRAM. The burst counter is fed by A [1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to an interleaved burst sequence. Table 1. Counter Implementation for the Intel Pentium(R)/80486 Processor's Sequence First Address A [1:0] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00
Table 2. Counter Implementation for a Linear Sequence First Address A[1:0] 00 01 10 11 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ HIGH places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Leaving ZZ unconnected defaults the device into an active state. Second Address A[1:0] 01 10 11 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10
3
PRELIMINARY
Cycle Description Table[1, 2, 3]
Cycle Description Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst ADD Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 H L L L X X L L L L L X X H H X H X X H H X H CE3 X X H X X X L L L L L X X X X X X X X X X X X CE2 X L X L X X H H H H H X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSP L X X L L X X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X X L L L L L L H H H H H H WE X X X X X X X X L H H H H H H L L H H H H L L
CY7C1336
OE X X X X X X L H X L H L H L H X X L H L H X X
CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H
DQ High-Z High-Z High-Z High-Z High-Z HIGH-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Notes: 1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW. 2. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[3:0]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the write cycle. 3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
4
PRELIMINARY
Pin Descriptions
TQFP Pin Number 85 Name ADSC I/O InputSynchronous InputSynchronous Description
CY7C1336
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. A1, A0 Address Inputs, These inputs feed the on-chip burst counter as the LSBs as well as being used to access a particular memory location in the memory array. Address Inputs used in conjunction with A [1:0] to select one of the 64K address locations. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active LOW. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the rising edge. BW0 controls DQ[7:0], BW1 controls DQ[15:8], BW2 controls DQ[23:16], BW3 controls DQ [31:24]. See Write Cycle Description Table for further details. Advance Input used to advance the on-chip address counter. When LOW the internal burst counter is advanced in a burst sequence. The burst sequence is selected using the MODE input. Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct a global write, independent of the state of BWE and BW[3:0]. Global writes override byte writes. Clock Input. Used to capture all synchronous inputs to the device. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3, to select/deselect the device. CE1 gates ADSP. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low power standby mode in which all other inputs are ignored, but the data in the memory array is maintained. Leaving ZZ floating or NC will default the device into an active state. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst order. Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[15:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[31:0] are placed in a three-state condition. The outputs are automatically three-stated when a WRITE cycle is detected.
84
ADSP
36, 37 49 -44, 81-82, 99-100, 32-35 96-93
A[1:0] A[15:2]
InputSynchronous InputSynchronous
BW[3:0]
InputSynchronous
83
ADV
InputSynchronous InputSynchronous InputSynchronous Input-Clock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous InputAsynchronous -
87 88
BWE GW
89 98 97 92 86
CLK CE1 CE2 CE3 OE
64
ZZ
31
MODE
29-28, 25-22, 19-18, 13-12, 9-6, 3-2, 79-78, 75-72, 69-68, 63-62, 59-56, 53-52 15, 41, 65, 91
DQ[31:0]
I/OSynchronous
VDD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
5
PRELIMINARY
Pin Descriptions (continued)
TQFP Pin Number 17, 40, 67, 90 5, 10, 14, 21, 26, 55, 60, 71, 76 4, 11, 20, 27, 54, 61, 70, 77 1,16, 30, 50-51, 66, 80 38, 39, 42, 43 Name VSS VSSQ I/O Ground Ground Description
CY7C1336
Ground for the I/O circuitry if the device. Should be connected to ground of the system. Ground for the device. Should be connected to ground of the system.
VDDQ
I/O Power Supply -
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
NC
No Connects.
DNU
-
Do not use pins. Should be left unconnected or tied LOW. DC Input Voltage[4] .......................................... -0.5V to VDD + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................-65C to +150C Ambient Temperature with Power Applied...............................................-55C to +125C Supply Voltage on VDD Relative to GND............... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[4] ...............................................-0.5V to VDD + 0.5V
Notes: 4. Minimum voltage equals -2.0V for pulse durations of less than 20 ns. 5. TA is the "instant on" case temperature.
Operating Range
Ambient Range Temperature[5] Com'l 0C to +70C VDD VDDQ
3.3V-5%/+10% 3.3V-5%/+10%
6
PRELIMINARY
Electrical Characteristics Over the Operating Range
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[4] Input Load Current (except ZZ and MODE) Input Current of MODE Input Current of ZZ IOZ IOS IDD Output Leakage Current Output Short Circuit Current VDD Operating Supply Current
[6]
CY7C1336
Test Conditions
Min. 3.135 3.135
Max. 3.63 3.63 0.4
Unit V V V V V V A A
VDDQ = 3.3V, VDD = Min., IOH= -4.0 mA VDDQ = 3.3V, VDD = Min., IOL= 8.0 mA
2.4 1.7 -0.3 VDD + 0.3V 0.8 5
GND VI VDDQ Input = VSS Input = VDDQ Input = VSS Input = VDDQ GND VI VDD, Output Disabled VDD=Max., VOUT=GND VDD=Max., Iout=0 mA, f = fMAX =1/tCYC. 8.5-ns cycle, 117 MHz 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz 8.5-ns cycle, 117 MHz 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz 8.5-ns cycle, 117 MHz 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz
-5 -30
5 -5 30 -5 5 -300 290 260 260 261 244 244 60 50 50 2.5
A A A A mA mA mA mA mA mA mA mA mA mA mA
IDD(L).
VDD Operating Supply Current for Low Power Version
VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC
ISB1
Automatic CE Power-Down Current--TTL Inputs Switching
Max. VDD, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC
ISB2
Automatic CE Power-Down Current -- CMOS Inputs Static
Max. VDD, Device Deselected, Std. version -All VIN 0.3V or VIN > VDDQ - 0.3V, speeds f=0 8.5-ns cycle, 117 MHz 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz All speeds
ISB3
Automatic CE Power-Down Max. VDD, Device Deselected, Current--CMOS Inputs Switching, or VIN 0.3V or VIN > VDDQ - F=Max 0.3V f = fMAX = 1/tCYC Automatic CE Power-Down Cur- Max. VDD, Device Deselected, rent -- CMOS Inputs Static, F=Max VIN VIH or VIN VIL,f = 0
40 30 30 25
mA mA mA mA
ISB4
Capacitance[7]
Parameter CIN CI/O Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 5.0V Max. 6.0 8.0 Unit pF pF
Notes: 6. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 7. Tested initially and after any design or process changes that may affect these parameters.
7
PRELIMINARY
AC Test Loads and Waveforms
R1=317 OUTPUT Z0 =50 RL =50 5 pF VL =1.5V INCLUDING JIG AND SCOPE R2=351 GND 3.0 ns 3.3V OUTPUT
CY7C1336
ALL INPUT PULSES 3.0V 10% 90% 90% 10% 3.0 ns
(a)
(b)
1336-3 1336-4
Switching Characteristics Over the Operating Range[8]
-117 Parameter tCYC tCH tCL tAS tAH tCDV tDOH tADS tADH tWES tWEH tADVS tADVH tDS tDH tCES tCEH tCHZ tCLZ tEOHZ tEOLZ tEOV Clock HIGH Clock LOW Address Set-Up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise ADSP, ADSC Set-Up Before CLK Rise ADSP, ADSC Hold After CLK Rise BW[3:0], GW, BWE Set-Up Before CLK Rise BW[3:0], GW, BWE Hold After CLK Rise ADV Set-Up Before CLK Rise ADV Hold After CLK Rise Data Input Set-Up Before CLK Rise Data Input Hold After CLK Rise Chip Enable Set-Up Before CLK Rise Chip Enable Hold After CLK Rise Clock to High-Z Clock to Low-Z
[9,10,11] [9,10,11]
-100 Min. 10 4.0 4.0 2.0 0.5 7.5 8.0 2.0 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 3.5 3.5 0 3.5 3.5 0 3.5 3.5 1.0 2.0 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.0 2.0 Max. Min. 15 5.0 5.0 2.5 0.5
-66 Max. Unit ns ns ns ns ns 9.0 ns ns ns ns ns ns ns ns ns ns ns ns 6.0 5.0 6.0 ns ns ns ns ns
Description Clock Cycle Time
Min. 8.5 3.0 3.0 2.0 0.5 2.0 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 0 0
Max.
OE HIGH to Output High-Z[9,11] OE LOW to Output Low-Z[9,11] OE LOW to Output Valid
Notes: 8. Unless otherwise noted, test conditions assume signal transition time of 3.0 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads. 9. tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 10. At any given voltage and temperature, tCHZ (max) is less than tCLZ (min). 11. This parameter is sampled and not 100% tested.
8
PRELIMINARY
Timing Diagrams
READ/WRITE Timing tCH tCYC tCL
CY7C1336
CLK
tAH
B C D
tAS
ADD
A
tADS
tADH
ADSP
tADS tADH
ADSC
tADVS tADVH
ADV
tCES tCEH
CE1
tCES tCEH
CE
tWES tWEH
WE
ADSP ignored with CE1 HIGH tEOHZ
Q(A) Q(B) Q (B+1) Q (B+2) Q (B+3) Q(B) D(C) D (C+1) D (C+2) D (C+3) Q(D)
OE
tCLZ
Data In/Out
tCDV
tDOH tCHZ
Device originally deselected
WE is the combination of BWE, BW[3:0], and GW to define a write cycle (see Cycle Description Table). CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X = DON'T CARE = UNDEFINED
9
PRELIMINARY
Timing Diagrams (continued)
OE Switching Waveforms
CY7C1336
OE
tEOHZ tEOV
I/Os
three-state
tEOLZ
10
PRELIMINARY
Timing Diagrams (continued)
ZZ Mode Timing [12,13]
CY7C1336
CLK
ADSP
HIGH
ADSC CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
IDD
IDD(active) IDDZZ
tZZREC
I/Os Three-state
NotefjdfdhfdjfdfjdjdjdjNo
Notes: 12. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device. 13. I/Os are in three-state when exiting ZZ sleep mode.
11
PRELIMINARY
Ordering Information
Speed (MHz) 117 117 100 100 66 66 Ordering Code CY7C1336-117AC CY7C1336L-117AC CY7C1336-100AC CY7C1336L-100AC CY7C1336-66AC CY7C1336L-66AC Package Name A101 A101 A101 A101 A101 A101 Package Type 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack
CY7C1336
Operating Range Commercial Commercial Commercial Commercial Commercial Commercial
Document #: 38-00661-A
Package Diagram
100-Pin Plastic Thin Quad Flat Pack (TQFP) A101
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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