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2M x 8-Bit Dynamic RAM HYB5117800BSJ-50/-60/-70 Advanced Information * * * 2 097 152 words by 8-bit organization 0 to 70 C operating temperature Performance:: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns * * Single + 5 V ( 10 %) supply Low power dissipation max. 660 active mW (-50 version) max. 605 active mW (-60 version) max. 550 active mW (-70 version) 11 mW standby (TTL) 5.5. mW standby (CMOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode Fast page mode capability All inputs, outputs and clocks fully TTL-compatible 2048 refresh cycles / 32 ms Plastic Package: P-SOJ-28-3 400 mil * * * * * * Semiconductor Group 1 1.96 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM The HYB 5117800BSJ is a 16 MBit dynamic RAM organized as 2097152 words by 8-bits. The HYB 5117800BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5117800BSJ to be packaged in a standard SOJ 28 400 mil plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V ( 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type HYB 5117800BSJ-50 HYB 5117800BSJ-60 HYB 5117800BSJ-70 Pin Names A0 to A10 A0 to A9 RAS OE I/O1-I/O8 CAS WE Row Address Inputs Column Address Inputs Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply (+ 5 V) Ground (0 V) not connected Ordering Code Q67100-Q1092 Q67100-Q1093 Q67100-Q1094 Package P-SOJ-28-3 P-SOJ-28-3 P-SOJ-28-3 400 mil 400 mil 400 mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) VCC VSS N.C. Semiconductor Group 2 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM P-SOJ-28-3 (400mil) VCC I/O1 I/O2 I/O3 I/O4 WE RAS N.C. A10 A0 A1 A2 A3 VCC O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O8 I/O7 I/O6 I/O5 CAS OE A9 A8 A7 A6 A5 A4 VSS Pin Configuration Semiconductor Group 3 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM I/O1 I/O2 I/O8 WE CAS . & Data in Buffer No. 2 Clock Generator 8 Data out Buffer 8 OE 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11 Column Address Buffer(10) 10 Column Decoder Refresh Controller Sense Amplifier I/O Gating 8 Refresh Counter (11) 11 Row 1024 x8 Address Buffers(11) 11 Decoder 2048 Row Memory Array 2048x1024x8 RAS No. 1 Clock Generator Voltage Down Generator VCC VCC (internal) Block Diagram Semiconductor Group 4 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,7.0) V Power supply voltage...................................................................................................-1.0V to 7.0 V Power dissipation..................................................................................................................... 1.0 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %, tT = 5 ns Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current,any input (0 V VIH Vcc + 0.3V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT Vcc + 0.3V) Average VCC supply current: -50 ns version -60 ns version -70 ns version (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH) ICC2 Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version (RAS cycling: CAS = VIH, tRC = tRC min.) Symbol Limit Values min. max. Vcc+0.5 0.8 - 0.4 10 10 2.4 - 0.5 2.4 - - 10 - 10 Unit Test Condition V V V V A A 1) 1) 1) 1) 1) VIH VIL VOH VOL II(L) IO(L) ICC1 1) - - - - - - - 120 110 100 2 120 110 100 mA mA mA mA mA mA mA 2) 3) 4) 2) 3) 4) 2) 3) 4) - 2) 4) 2) 4) 2) 4) ICC3 Semiconductor Group 5 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %, tT = 5 ns Parameter Symbol Limit Values min. Average VCC supply current, ICC4 during fast page mode: -50 ns version -60 ns version -70 ns version (RAS = VIL, CAS, address cycling,tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC - 0.2 V) Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version -70 ns version (RAS, CAS cycling, tRC = tRC min.) Average Self Refresh Current (CBR cycle with tRAS>TRASSmin., CAS held low, WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V) max. 40 35 30 1 Unit Test Condition mA mA mA mA 2) 3) 4) 2) 3) 4) 2) 3) 4) - - - - ICC5 ICC6 1) - - - 120 110 100 mA mA mA 2) 4) 2) 4) 2) 4) ICC7 _ 1 mA Capacitance TA = 0 to 70 C,VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A10) Input capacitance (RAS, CAS, WE, OE) I/O capacitance (I/O1-I/O8) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit CI1 CI2 CIO Semiconductor Group 6 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter Symbol 16F Limit Values -50 min. -60 -70 max. - - 10k 10k - - - - 50 35 - - - 50 32 max. min. - - 10k 10k - - - - 37 25 110 40 60 15 0 10 0 15 20 15 15 60 - 50 32 5 3 - max. min. - - 10k 10k - - - - 45 30 - - - 50 32 130 50 70 20 0 10 0 15 20 15 20 70 5 3 - Unit Note common parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 90 30 50 13 0 8 0 10 18 13 13 50 5 3 - ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 Read Cycle Access time from RAS Access time from CAS OE access time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tOEA tRCS tRCH tRRH tCLZ tOFF - - - - 25 0 0 0 0 0 50 13 25 13 - - - - - 13 - - - - 30 0 0 0 0 0 60 15 30 15 - - - - - 15 - - - - 35 0 0 0 0 0 70 20 35 20 - - - - - 20 ns ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10 Access time from column address tAA Column address to RAS lead time tRAL Semiconductor Group 7 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter Symbol 16F Limit Values -50 min. -60 0 0 15 15 15 - - - 0 0 20 20 -70 max. 20 - - - max. min. 13 - - - max. min. Unit Note Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay tOEZ tDZO tCDD tODD 0 0 13 13 ns ns ns ns 12 13 14 14 Write Cycle Write command hold time Write command pulse width Write command setup time tWCH tWP tWCS 8 8 0 13 13 0 10 0 - - - - - - - - 10 10 0 15 15 0 10 0 - - - - - - - - 10 10 0 20 20 0 15 0 - - - - - - - - ns ns ns ns ns ns ns ns 16 16 13 15 Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time Data to CAS low delay tDS tDH tDZC Read-Modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time OE command hold time tRWC tRWD tCWD tOEH 126 68 31 43 13 - - - - - 150 80 35 50 15 - - - - - 180 95 45 60 20 - - - - - ns ns ns ns ns 15 15 15 Column address to WE delay time tAWD Fast Page Mode Cycle Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCP tCPA tRAS tRHPC 35 10 - 50 30 - - 30 - 40 10 - 35 - - 35 - 45 10 - 40 - - 40 - ns ns ns ns 7 200k 60 200k 70 200k ns Semiconductor Group 8 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter Symbol 16F Limit Values -50 min. -60 -70 max. - - max. min. - - 80 55 max. min. - - 95 65 Unit Note Fast Page Mode Read-Modify-Write Cycle Fast page mode read-write cycle time CAS precharge to WE tPRWC tCPWD 71 48 ns ns CAS-before-RAS Refresh Cycle CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time tCSR tCHR tRPC tWRP 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns Write hold time referenced to RAS tWRH CAS-before-RAS Counter Test Cycle CAS precharge time tCPT 35 - 40 - 40 - ns Test Mode CAS hold time Write command setup time Write command hold time tCHRT tWTS tWTH 30 10 10 - - - 30 10 10 - - - 30 10 10 - - - ns ns ns Self Refresh Cycle RAS pulse width RAS precharge time CAS hold time tRASS tRPS tCHS 100k _ 95 -50 _ _ 100k _ 110 -50 _ _ 100k _ 130 -50 _ _ ns ns ns 17 17 17 Semiconductor Group 9 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 2 TTL loads and 100 pF. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)Either tDZC or tDZO must be satisfied. 14)Either tCDD or tODD must be satisfied. 15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. Semiconductor Group 10 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRAS V tRP RAS IH VIL tCSH tRCD tRSH tCAS tRAL tCRP V IH CAS VIL tRAD tASR tASC AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA tCAH Column tASR AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA V Address AAAAAAA IH AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA VIL Row Row tRCH tRAH V tRCS tRRH tAA tOEA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA WE IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL V OE IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZC tDZO AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCDD tODD tCAC tCLZ tOEZ AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA I/O (Inputs) V AAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL tOFF I/O (Outputs) V V OH Hi Z OL Valid Data Out Hi Z tRAC AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL1 Read Cycle Semiconductor Group 11 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRAS V tRP RAS IH VIL tCSH tRCD tRSH tCAS tRAL tCAH Column tCRP V IH CAS VIL tRAD tASR tASC AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA tASR AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA V . Row Address IH AAAAAAA AAAAAAA Row VIL tRAH V tWCS t WP tCWL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA WE IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA tWCH tRWL OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDS I/O (Inputs) V IH VIL tDH Valid Data In OH I/O (Outputs) V OL V Hi Z AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA "H" or "L" WL2 Write Cycle (Early Write) Semiconductor Group 12 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRAS V tRP RAS IH VIL tCSH tRCD tRSH tCAS tRAL tCRP V IH CAS VIL tRAD tASR tASC AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA tCAH Column tASR AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA Address V AAAAAAAAA Row AAAAAAAAA AAAAAAAAA IL AAAAAAAAA V AAAAAAAAA IHAAAAAAAAA AAAAAAAAA . Row tRAH V WE IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL tRWL tWP VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEH V OE IH AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA VIL tDZO tDZC I/O (Inputs) V IH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA tODD tDS tOEZ AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tDH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL Valid Data tCLZ tOEA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA I/O (Outputs) V V OH OL Hi-Z Hi-Z AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL3 Write Cycle (OE Controlled Write) Semiconductor Group 13 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRWC tRAS V tRP RAS IH VIL V tCSH tRCD tRSH tCAS tCRP IH CAS VIL tRAH tASR V tCAH tASC tASR Row Address IH AAAA AAAA AAAA AAAA AAAA AAAA VIL Row AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Column tRAD V AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL tAWD tCWD tRWD tRWL tWP AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA WE VIL tAA tRCS V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEA tOEH AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA OE VIL tDZO tDZC V AAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA tDS tDH Valid Data in AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA I/O (Inputs) VIL tCLZ tCAC tODD tOEZ AAAAAA AAAAAA Data AAAAAA AAAAAA AAAAAA Out AAAAAA I/O (Outputs) V OL V OH tRAC AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL4 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 14 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRASP V IH tRP RAS VIL tPC tRCD V IH tCAS tCP tCAS tRHCP tRSH tCAS tCRP CAS VIL tCSH tRAH tASR tASC tCAH Column tASC tCAH tCAH tASC AAAAAAAAA AAAAAAAAA AAAAAAAAA Column AAAAAAAAA AAAAAAAAA AAAAAAAAA tRCS AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAA tRRH AAAAAAA tASR AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA V Address AAAAA IH AAAAA AAAAA AAAAA AAAAA Row AAAAA AAAAA AAAAA AAAAA AAAAA VIL AAAAA AAAAA tRAD AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA Row tRCH tRCH tRCS V IH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tRCS WE VIL tAA V AAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA V AAAAAAAAAAAAAAAAAAAAAAAAAAA tCPA tAA tOEA tOEA tCPA tAA tOEA tDZC OE IL AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA tDZC tDZO tODD AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tDZC tDZO tODD tDZO tCDD tODD AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA tOFF I/O (Inputs) V AAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA tCAC tCLZ tOFF tOEZ tCAC tCLZ tRAC OH I/O (Outputs) V OL V AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tOFF tCAC tCLZ tOEZ tOEZ AAAAA AAAAA AAAAA Valid AAAAA AAAAA Data Out AAAAA AAAAA AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data Out AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data Out AAAAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" FPM1 Fast Page Mode Read Cycle Semiconductor Group 15 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRAS V IH tRP RAS VIL tPC tRCD V IH tRSH tCP tCAS tCAS tCRP tCAS CAS VIL tRAH tASR V IH AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tRAL tCAH tASC tASC AAAAAAAAAA AAAAAAAAAA tCAH tASC AAAAAAAAAA AAAAAAAAAA tCAH tASR AAAAAAAAA AAAAAAAAA Address VIL Row AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA tRAD tWCS V tCWL tWCH tWP tWCS AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA tCWL tWCH tWP tWCS AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA tCWL tRWL WE AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA tWCH tWP AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA VIL V OE IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDH tDS I/O (Inputs) V AAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA tDH tDS AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA tDH tDS AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA VIL Valid Data In Valid Data In Valid Data In AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA OH I/O (Outputs) V OL AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA V HI-Z "H" or "L" FPM2 Fast Page Mode Early Write Cycle Semiconductor Group 16 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tCPWD tCWD tAWD tOEA tCPWD tCWD tOEA tCAH tRWD tCWD tAWD tOEA tCAH tDZC tCLZ tDZO tCSH Column tASC tAA tCAC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tWP Data In tOEH tOEZ tDH AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Column Address tCLZ AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tWP tOEH Data In tDH AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Column AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tASC tCWL tDZC tCAC tAA tCAH tCPA tCLZ AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tOEH tWP Data In tDH tOEZ tDS AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tRAL tRWL tCWL AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tRP tCRP tASR Row tODD tCAS tPRWC tCAS tRAS tODD tOEZ tAWD tASC tCPA tDZC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tCWL tCP tAA AAAAAA AAAAAA AAAAAA AAAAAA tODD tCAS I/O (Inputs) V IL Fast Page Mode Read-Modify-Write Cycle Semiconductor Group 17 OH I/O (Outputs) V IH IH IH IH IH IH V IL V IL V IL V IL V V IL V V V Address RAS CAS V WE OE V V OL AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Row AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA tASR "H" or "L" tRAD tRAH AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tRCD tRCS tRAC Data Out AAAAA AAAAA AAAAA tDS Data Out AAAAA AAAAA AAAAA tDS Data Out AAAAA AAAAA AAAAA tRSH HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRAS V tRP RAS IH VIL tCRP tRPC V IH AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA CAS VIL tRAH tASR tASR Row V Address IH AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA VIL Row AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA OH I/O (Outputs) V OL AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA V HI-Z "H" or "L" WL9 RAS-Only Refresh Cycle Semiconductor Group 18 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRP V tRAS tRP RAS IH VIL tRPC tCP tCSR tCHR tRPC tCRP AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA V CAS IH VIL tWRP tWRH V IH AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA WE VIL tOEZ V OE IH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCDD IH I/O (Inputs) V IL V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tODD OH I/O (Outputs)VOL V HI-Z tOFF AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL10 CAS-Before-RAS Refresh Cycle Semiconductor Group 19 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC V tRC tRP tRAS tRP tRAS IH RAS VIL tRCD V tRSH tCHR tCRP CAS IH VIL tRAD tASC tASR tRAH AAAAA AAAAA AAAAA AAAAA tWRP tCAH tWRH tASR Row AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Address V AAAAAAA IHAAAAAAA AAAAAAA VIL AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row AAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tRCS WE V AAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA tRRH AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tAA tOEA OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZC AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCDD tDZO V tODD tCAC tCLZ AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA I/O (Inputs) IH VIL AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA tOFF tOEZ Valid Data Out tRAC OH I/O (Outputs) V OL AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA V AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA HI-Z "H" or "L" WL11 Hidden Refresh Cycle (Read) Semiconductor Group 20 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRP V IH tRC tRAS tRP tRAS RAS VIL tRCD V IH tRSH tCHR tCRP CAS VIL tRAD tRAH tASR AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tASC tCAH tASR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Address V AAAAAAA IHAAAAAAA AAAAAAA Row AAAAAAA VIL AAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row tWCS tWCH tWP tWRP AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA tWRH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V WE AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL tDS I/O (Input) V AAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA V AAAAAAAAAAAAAAA IL AAAAAAAAAAAAAAA tDH Valid Data AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA OH I/O (Output) V OL V HI-Z AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL12 Hidden Refresh Cycle (Early Write) Semiconductor Group 21 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRP V tRASS tRPS RAS IH VIL tRPC tCSR V tCHS tCRP AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA tCP IH CAS VIL tWRP tWRH V WE IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OE IH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCDD IH I/O (Inputs) V IL V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tODD tOEZ OH I/O (Outputs) VOL V HI-Z tOFF AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL13 CAS before RAS Self Refresh Cycle Semiconductor Group 22 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRAS Read Cycle: RAS V IH V IL tRP tCSR CAS V IH V IL tCHR tCP tRSH tCAS tRAL tASC Address V IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCAH tAA tCAC tASR Row Column tWRP AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tRRH WE AAAAAAAAAAAAA V IL AAAAAAAAAAAAA AAAAAAAAAAAAA V IHAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAA tWRH AAAAAAAAAAAAAA tRCS tOEA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tRCH OE V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZC I/O (Inputs) V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VOH VOL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tODD tDZO tCLZ AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA tOFF AAAAAAAAAAAAAA tCDD tOEZ Data Out I/O (Outputs) tWRP Write Cycle: WE V IH AAAAAAAAAAAA AAAAAAAAAAAA V IL AAAAAAAAAAAA AAAAAAAAAAAA tWCS AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAA tRWL tCWL tWCH tWRH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA OE V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDS I/O (Inputs) I/O (Outputs) V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IH V IL V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDH Data In AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA HI-Z CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 23 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRP V tRC tRAS tRP RAS IH VIL tRPC tCP tCSR tCHR tRPC tCRP V CAS IH VIL AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA tASR tRAH AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA Address IHAAAAAAAAAAAAAAAAAAAAAAAAAAA Row AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA V VIL AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWTS V tWTH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA WE AAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA VIL V OE IH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA I/O (Inputs) V IL V IH tODD HI-Z AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCDD tOEZ I/O (Outputs) V V AAAAAAAAAAAAAAAAAAAAAAA OHAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA OL AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA HI-Z tOFF "H" or "L" WL15 Test Mode Entry Semiconductor Group 24 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM Test Mode As the HYB 5117800BSJ is organized internally as 1M x 16-bits, a test mode cycle using 2:1 compression can be used to improve test time. Note that in the 2M x 8 version the test time is reduced by 1/2 for a N test pattern. In a test mode "write" the data from each I/O pin is written into two 1M blocks simultaneously (all "1" s or all "0" s). In test mode "read" each I/O output is used for indicating the test mode result. If the internal two bits are equal, the I/O would indicate a "1". If they were not equal, the I/O would indicate a "0". The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test mode, a "CAS before RAS refresh", "RAS only refresh" or "Hidden refresh" can be used. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cylces. Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other addresses are don't care. Semiconductor Group 25 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM Package Outlines Plastic Package P-SOJ-28-3 (400 mil) (Small Outline J-lead, SMD) 0.8 min. 3.75 -0.5 0.5 30 O 1.27 0.51 -0.13 0.81max 0.18 M 9.4 + 0.25 0.1 11.18 +0.13 - 0.2 + 0.1 0.18 M 10.16 +0.13 - 1) 28x GPJ05699 28 15 1 18.54 Index Marking -0.25 1) 14 1) Does not include plastic or metal protrusion of 0.15 max. per side Semiconductor Group 26 |
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