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WM8766
24-bit, 192kHz 6-Channel DAC
DESCRIPTION
The WM8766 is a multi-channel audio DAC ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audio visual equipment. Three stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 192kHz are supported. Each DAC channel has independent digital volume and mute control. The audio data interface supports I2S, left justified, right justified and DSP digital audio formats The device is controlled via a 3 wire serial interface or directly using the hardware interface. These interfaces provide access to features including channel selection, volume controls, mutes, de-emphasis and power management facilities. The device is available in a 28-pin SSOP.
FEATURES
* * * * * 6-Channel DAC Audio Performance - 103dB SNR (`A' weighted @ 48kHz) DAC DAC Sampling Frequency: 8kHz - 192kHz 3-Wire SPI Serial or Hardware Control Interface Programmable Audio Data Interface Modes - I2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths Three Independent stereo DAC outputs with independent digital volume controls Master or Slave Audio Data Interface 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation 28 pin SSOP Package
* * * *
APPLICATIONS
* * * DVD Players Surround Sound AV Processors and Hi-Fi systems Automotive Audio
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc www.wolfsonmicro.com
Preliminary Technical Data, February 2004, 2.3 Copyright 2004 Wolfson Microelectronics plc
WM8766 TABLE OF CONTENTS
Preliminary Technical Data
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION 28 LEAD SSOP ...............................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION - 28 PIN SSOP ......................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 7 MASTER CLOCK TIMING ............................................................................................. 7 DIGITAL AUDIO INTERFACE - MASTER MODE ......................................................... 8 TABLE 2 DIGITAL AUDIO DATA TIMING - MASTER MODE ...................................... 8 DIGITAL AUDIO INTERFACE - SLAVE MODE ............................................................ 9 MPU INTERFACE TIMING .......................................................................................... 10
DEVICE DESCRIPTION.......................................................................................11
INTRODUCTION ......................................................................................................... 11 AUDIO DATA SAMPLING RATES............................................................................... 11 HARDWARE CONTROL MODES ............................................................................... 12 DIGITAL AUDIO INTERFACE ..................................................................................... 14 POWERDOWN MODES ............................................................................................. 17 ZERO DETECT ........................................................................................................... 18 SOFTWARE CONTROL INTERFACE OPERATION................................................... 18 CONTROL INTERFACE REGISTERS ........................................................................ 18
REGISTER MAP...................................................................................................26 DIGITAL FILTER CHARACTERISTICS ...............................................................27 DAC FILTER RESPONSES .................................................................................27
DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 28
APPLICATIONS INFORMATION .........................................................................29
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 29 SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS ................................... 30
PACKAGE DIMENSIONS ....................................................................................31 IMPORTANT NOTICE ..........................................................................................32
ADDRESS: .................................................................................................................. 32
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Preliminary Technical Data
WM8766
PIN CONFIGURATION 28 LEAD SSOP
ORDERING INFORMATION
DEVICE WM8766EDS/V WM8766GEDS/V WM8766EDS/RV TEMP. RANGE -25 to +85oC -25 to +85oC -25 to +85oC PACKAGE 28-pin SSOP 28-pin SSOP (lead free) 28-pin SSOP (tape and reel) 28-pin SSOP (lead free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 MSL3 MSL3
WM8766GEDS/RV Note: Reel quantity = 2,000
-25 to +85oC
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WM8766 PIN DESCRIPTION - 28 PIN SSOP
PIN 1 NAME MODE TYPE Digital input Control format selection 0 = Software control 1 = Hardware control DESCRIPTION
Preliminary Technical Data
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MCLK BCLK LRCLK DVDD DGND DIN1 DIN2 DIN3 DNC ML/I2S MC/IWL MD/DM MUTE TESTREF VREFN VREFP VMID NC NC VOUT1L VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R AGND AVDD
Digital input Digital input/output Digital input/output Supply Supply Digital input Digital input Digital input Do not connect Digital input Digital input Digital input Digital input/output Digital input Supply Supply Analogue output No connect No connect Analogue output Analogue output Analogue output Analogue output Analogue output Analogue output Supply Supply
Master clock; 128, 192, 256, 384, 512 or 768fs (fs = word clock frequency) Audio interface bit clock Audio left/right word clock Digital positive supply Digital negative supply DAC channel 1 data input DAC channel 2 data input DAC channel 3 data input Do not connect Software Mode: Serial interface Latch signal Hardware Mode: Input Audio Data Format Software Mode: Serial control interface clock Hardware Mode: Audio data input word length Software Mode: Serial interface data Hardware Mode: De-emphasis selection DAC Zero Flag output or DAC mute input Test reference DAC negative supply DAC positive reference supply Midrail divider decoupling pin; 10uF external decoupling No internal connection No internal connection DAC channel 1 left output DAC channel 1 right output DAC channel 2 left output DAC channel 2 right output DAC channel 3 left output DAC channel 3 right output Analogue negative supply and substrate connection Analogue positive supply
Note: Digital input pins have Schmitt trigger input buffers.
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Preliminary Technical Data
WM8766
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature after soldering Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Notes: 1. Analogue and digital grounds must always be within 0.3V of each other for normal operation of the device. -25C -65C MIN -0.3V -0.3V DGND -0.3V AGND -0.3V MAX +5V +7V DVDD +0.3V AVDD +0.3V 37MHz +85C +150C +260C +183C
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WM8766 RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Ground Difference DGND to AGND SYMBOL DVDD AVDD, VREFP AGND, VREFN, DGND -0.3 TEST CONDITIONS MIN 2.7 2.7 0 0 TYP
Preliminary Technical Data
MAX 3.6 5.5 +0.3
UNIT V V V V
Note: Digital supply DVDD must never be more than 0.3V greater than AVDD for normal operation of the device .
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs. PARAMETER Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference Voltage Potential Divider Resistance VVMID RVMID (VREFP to VMID) and (VMID to VREFN) VREFP/2 133k V SYMBOL VIL VIH VOL VOH IOL=1mA IOH= -1mA 0.9 x DVDD 0.7 x DVDD 0.1 x DVDD TEST CONDITIONS MIN TYP MAX 0.3 x DVDD UNIT V V V V Digital Logic Levels (CMOS Levels)
DAC Performance (Load = 10k, 50pF) 0dBFs Full Scale Output Voltage SNR (Note 1,2,4) SNR (Note 1,2,4) SNR (Note 1,2,4) SNR (Note 1,2,4) A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz A-weighted @ fs = 48kHz, AVDD = 3.3V A-weighted @ fs = 96kHz, AVDD = 3.3V DNR A-weighted, -60dB full scale input 1kHz, 0dBFs 1kHz Input, 0dB gain PSRR 1kHz 100mVpp 20Hz to 20kHz 100mVp-p Supply Current Analogue Supply Current Digital Supply Current AVDD, VREFP = 5V DVDD = 3.3V 13.8 11.0 mA mA 95 95 1.0 x VREFP/5 103 101 101 101 Vrms dB dB dB dB
SNR (Note 1,2,4)
99
dB
Dynamic Range (Note 2,4) Total Harmonic Distortion (THD) Mute Attenuation DAC Channel Separation Power Supply Rejection Ratio
103 -90 100 100 50 45 -80
dB dB dB dB dB dB
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Preliminary Technical Data Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted.
WM8766
All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
3.
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3. 4. 5. 6.
MASTER CLOCK TIMING
t MCLKL MCLK t MCLKH t MCLKY
Figure 1 DAC Master Clock Timing Requirements Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK Duty cycle Table 1 Master Clock Timing Requirements tMCLKH tMCLKL tMCLKY 11 11 28 40:60 60:40 ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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WM8766
DIGITAL AUDIO INTERFACE - MASTER MODE
Preliminary Technical Data
BCLK WM8766 DAC LRCLK DIN1/2/3
3
DSP/ DECODER
Figure 2 Audio Interface - Master Mode
BCLK (Output) tDL LRCLK (Output) DIN1/2/3 tDST
Figure 3 Digital Audio Data Timing - Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER LRCLK propagation delay from BCLK falling edge DIN1/2/3 setup time to BCLK rising edge DIN1/2/3 hold time from BCLK rising edge SYMBOL tDL tDST tDHT TEST CONDITIONS MIN 0 10 10 TYP MAX 10 UNIT ns ns ns
tDHT
Audio Data Input Timing Information
Table 2 Digital Audio Data Timing - Master Mode
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Preliminary Technical Data
WM8766
DIGITAL AUDIO INTERFACE - SLAVE MODE
BCLK WM8766 DAC LRCLK DIN1/2/3
3
DSP/ DECODER
Figure 4 Audio Interface - Slave Mode
tBCH BCLK tBCY LRCLK
tBCL
tDS DIN1/2/3
tLRH
tLRSU
Figure 5 Digital Audio Data Timing - Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low LRCLK set-up time to BCLK rising edge LRCLK hold time from BCLK rising edge DIN1/2/3 set-up time to BCLK rising edge DIN1/2/3 hold time from BCLK rising edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDS tDH TEST CONDITIONS MIN 50 20 20 10 10 10 10 TYP MAX UNIT ns ns ns ns ns ns ns
Audio Data Input Timing Information
Table 3 Digital Audio Data Timing - Slave Mode
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WM8766
MPU INTERFACE TIMING
Preliminary Technical Data
tCSL ML/I2S tSCY tSCH MC/IWL tSCL tSCS tCSS
tCSH
MD/DM tDSU tDHO
LSB
Figure 6 SPI Compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated PARAMETER MC/IWL rising edge to ML/I2S rising edge MC/IWL pulse cycle time MC/IWL pulse width low MC/IWL pulse width high MD/DM to MC/IWL set-up time MC/IWL to MD/DM hold time ML/I2S pulse width low ML/I2S pulse width high ML/I2S rising to MC/IWL rising SYMBOL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS MIN 60 80 30 30 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
Table 4 3-wire SPI Compatible Control Interface Input Timing Information
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Preliminary Technical Data
WM8766
DEVICE DESCRIPTION
INTRODUCTION
WM8766 is a complete 6-channel DAC including digital interpolation and decimation filters and switched capacitor multi-bit sigma delta DACs with digital volume controls on each channel and output smoothing filters. The device is implemented as 3 separate stereo DACs in a single package and controlled by a single interface. Each stereo DAC has its own data input DIN1/2/3. DAC word clock LRCLK, DAC bit clock BCLK and DAC master clock MCLK are shared between them. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode, LRCLK and BCLK are all inputs. In Master mode, LRCLK and BCLK are all outputs. Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume controls may be operated independently. In addition, a zero cross detect circuit is provided for each DAC for the digital volume controls. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and `zipper' noise as the gain values change. Control of internal functionality of the device is by 3-wire serial or pin programmable control interface. The software control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC. In Slave mode selection between clock rates is automatically controlled. In master mode, the sample rate is set by control bit DACRATE. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are allowed for the DAC, provided the appropriate master clock is input. The audio data interface supports right, left and I S interface formats along with a highly flexible DSP serial port interface.
2
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the DAC MCLK input pin(s) with no software configuration necessary. The DAC master clock for WM8766 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8766 has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The WM8766 is tolerant of phase variations or jitter on the master clock. Table 5 shows the typical master clock frequency inputs for the WM8766. The signal processing for the WM8766 typically operates at an oversampling rate of 128fs. The exception to this is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the oversampling rate is 64fs.
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WM8766
SAMPLING RATE (LRCLK) 32kHz 44.1kHz 48kHz 96kHz 192kHz System Clock Frequency (MHz) 128fs 4.096 5.6448 6.144 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 384fs 12.288 16.9340 18.432 36.864
Preliminary Technical Data
512fs 16.384 22.5792 24.576
768fs 24.576 33.8688 36.864
Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable
Table 5 System Clock Frequencies Versus Sampling Rate
HARDWARE CONTROL MODES
When the MODE pin is held high, the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, MUTE controls the selection of MUTE directly, and can be used to enable and disable the automute function. This pin becomes an output when left floating and indicates infinite ZERO detect (IZD) has been detected. DESCRIPTION 0 1 Floating Normal Operation Mute DAC channels Enable IZD, MUTE becomes an output to indicate when IZD occurs. L=IZD detected, H=IZD not detected.
Table 6 Mute and Automute Control Figure 7 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. When MUTE is de-asserted, the output will restart almost immediately from the current input sample.
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 7 Application and Release of Soft Mute
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Preliminary Technical Data
WM8766
The automute function detects a series of ZERO value audio samples of 1024 samples long being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR'ed through a 10k resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert mute. If MUTE is tied low, AUTOMUTED is overridden and will not mute unless the IZD register bit is set. If MUTE is driven from a bi-directional source, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) and can be used to drive external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-ZERO input. A diagram showing how the various Mute modes interact is shown below Figure 8.
IZD (Register Bit) AUTOMUTED (Internal Signal) 10k MUTE PIN SOFTMUTE (Internal Signal)
MUTE (Register Bit)
Figure 8 Selection Logic for MUTE Modes
INPUT FORMAT SELECTION
In hardware mode, ML/I2S and MC/IWL become input controls for selection of input data format type and input data word length for the DAC. ML/I2S 0 0 1 1 Table 7 Input Format Selection Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that the left/right clocks (LRCLK) are high for a minimum of 24 bit clocks (BCLK) and low for a minimum of 24 bit clocks. If exactly 32 bit clocks occur in one left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode. MC/IWL 0 1 0 1 INPUT DATA MODE 24-bit right justified 20-bit right justified 16-bit I2S 24-bit I2S
DE-EMPHASIS CONTROL
In hardware mode, the MD/DM pin becomes an input control for selection of de-emphasis filtering to be applied. MD/DM 0 1 Table 8 De-emphasis Control DE-EMPHASIS Off On
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WM8766
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
Preliminary Technical Data
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In both Master and Slave modes DIN1/2/3 are always inputs to the WM8766 and DOUT is always an output. The default is Slave mode. In Slave mode, LRCLK and BCLK are inputs to the WM8766 DIN1/2/3 and LRCLK are sampled by the WM8766 on the rising edge of BCLK. By setting the control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 and LRCLK are sampled on the falling edge of BCLK and DOUT changes on the rising edge of BCLK
BCLK WM8766 DAC LRCLK DIN1/2/3
3
DSP/ DECODER
Figure 9 Slave Mode In Master mode, LRCLK and BCLK are outputs from the WM8766 (Figure 10). LRCLK and BCLK are generated by the WM8766. DIN1/2/3 are sampled by the WM8766 on the rising edge of BCLK. By setting control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 are sampled on the falling edge of BCLK, and DOUT changes on the rising edge of BCLK.
BCLK WM8766 DAC LRCLK DIN1/2/3
3
DSP/ DECODER
Figure 10 Master Mode
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Preliminary Technical Data
WM8766
AUDIO INTERFACE FORMATS
Audio data is applied to the internal DAC filters via the Digital Audio Interface. 5 popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP Early mode DSP Late mode
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN1/2/3 inputs. Audio Data for each stereo channel is time multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of BCLKs per LRCLK period is 2 times the selected word length. LRCLK must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirements are met. In DSP early or DSP late mode, all 6 DAC channels are time multiplexed onto DIN1. LRCLK is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period is 6 times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the rising edge is correctly positioned.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8766 on the first rising edge of BCLK following a LRCLK transition. LRCLK is high during the left samples and low during the right samples, see Figure 11.
Figure 11 Left Justified Mode Timing Diagram
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WM8766
RIGHT JUSTIFIED MODE
Preliminary Technical Data
In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8766 on the rising edge of BCLK preceding a LRCLK transition. LRCLK are high during the left samples and low during the right samples, see Figure 12.
Figure 12 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB of DIN1/2/3 is sampled by the WM8766 on the second rising edge of BCLK following a LRCLK transition. LRCLK are low during the left samples and high during the right samples.
Figure 13 I S Mode Timing Diagram
2
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Preliminary Technical Data
WM8766
DSP EARLY MODE
In DSP early mode, the MSB of DAC channel 1 left data is sampled by the WM8766 on the second rising edge on BCLK following a LRCLK rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 14).
Figure 14 DSP Early Mode Timing Diagram - DAC Data Input
DSP LATE MODE
In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8766 on the first BCLK rising edge following a LRCLK rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 15).
Figure 15 DSP Late Mode Timing Diagram - DAC Data Input In both early and late DSP modes, DACL1 is always sent first, followed immediately by DACR1 and the data words for the other 6 channels. No BCLK edges are allowed between the data words. The word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right.
POWERDOWN MODES
The WM8766 has powerdown control bits allowing specific parts of the WM8766 to be powered off when not being used. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0] allowing individual stereo DACs to be powered off when not in use. Setting DACPD[2:0] will powerdown everything except the reference VMID may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that the DACs are powered down before setting PDWN.
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WM8766
ZERO DETECT
Preliminary Technical Data
The WM8766 has a zero detect circuit for each DAC channel that detects when 1024 consecutive zero samples have been input. The MUTE pin output may be programmed to output the zero detect signal (see Table 9) which may then be used to control external muting circuits. A `1' on MUTE indicates a zero detect. The zero detect may also be used to automatically enable DAC mute by setting IZD. DZFM[1:0] 00 01 10 11 MUTE All channels zero Channel 1 zero Channel 2 zero Channel 3 zero
Table 9 Zero Flag Output Select
SOFTWARE CONTROL INTERFACE OPERATION
The WM8766 is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. The control mode is selected by the state of the MODE pin.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is used to latch the program data. MD/DM is sampled on the rising edge of MC/IWL. The 3-wire interface protocol is shown in Figure 16.
ML/I2S
MC/IWL
MD/DM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 16 3-wire SPI Compatible Interface 1. 2. 3. B[15:9] are Control Address Bits B[8:0] are Control Data Bits ML/I2S is edge sensitive - the data is latched on the rising edge of ML/I2S.
CONTROL INTERFACE REGISTERS
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS 0000010 DAC Channel Control BIT 3 LABEL ATC DEFAULT 0 DESCRIPTION Attenuator Control Mode: 0: Right channels use right attenuations 1: Right channels use left attenuations
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Preliminary Technical Data
WM8766
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS 0000010 DAC Channel Control BIT 4 LABEL IZD DEFAULT 0 DESCRIPTION Infinite Zero Mute Enable 0 : Disable inifinite zero mute 1: Enable infinite zero mute
With IZD enabled, applying 1024 consecutive zero input samples to each stereo channel will cause that stereo channel outputs to be muted to VMID. Mute will be removed as soon as that stereo channel receives a non-zero input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS 0000010 DAC Control BIT 8:5 LABEL PL[3:0] DEFAULT 1001 PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DESCRIPTION Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS 0000011 Interface Control BIT 1:0 LABEL FMT [1:0] DEFAULT 00 DESCRIPTION Interface Format Select: 00 : Right justified mode 01: Left justified mode 10: I2S mode 11: DSP (early or late) mode
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCLK. If this bit is set high, the expected polarity of LRCLK will be the opposite of that shown in Figure 11, Figure 12 and Figure 13. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select between early and late modes.
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WM8766
REGISTER ADDRESS 0000011 Interface Control BIT 2 LABEL LRP DEFAULT 0
Preliminary Technical Data DESCRIPTION In left/right/I2S Modes: LRCLK Polarity (normal) 0 : Normal LRCLK polarity 1: Inverted LRCLK polarity In DSP Mode: 0 : Early DSP mode 1: Late DSP mode
By default, LRCLK and DIN1/2/3 are sampled on the rising edge of BCLK and should ideally change on the falling edge. Data sources that change LRCLK and DIN1/2/3 on the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figure 11, Figure 12, Figure 13, Figure 14, and Figure 15. REGISTER ADDRESS 0000011 Interface Control BIT 3 LABEL BCP DEFAULT 0 DESCRIPTION BCLK Polarity (DSP Modes): 0: Normal BCLK polarity 1: Inverted BCLK polarity
The IWL[1:0] bits are used to control the input word length. REGISTER ADDRESS 0000011 Interface Control BIT 5:4 LABEL IWL [1:0] DEFAULT 00 DESCRIPTION Input Word Length: 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data
Note: 32-bit right justified mode is not supported. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8766 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that LRCLK is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. A number of options are available to control how data from the Digital Audio Interface is applied to the DAC channels.
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Preliminary Technical Data
WM8766
DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS 0000011 DAC Phase BIT 8:6 LABEL PHASE [2:0] DEFAULT 000 Bit 0 1 2 DESCRIPTION DAC DAC1L/R DAC2L/R DAC3L/R Phase 1 = invert 1 = invert 1 = invert
DIGITAL ZERO CROSS-DETECT
The Digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN. REGISTER ADDRESS 0001001 DAC Control BIT 0 LABEL ZCD DEFAULT 0 DESCRIPTION DAC Digital Volume Zero Cross Enable: 0: Zero cross detect enabled 1: Zero cross detect disabled
MUTE FLAG OUTPUT
The DZFM control bits allow the selection of the six DAC channel zero flag bits for output on the MUTE pin. A `1' on MUTE indicates 1024 consecutive zero input samples to the DAC channels selected. REGISTER ADDRESS 0001001 Zero Flag BIT 2:1 LABEL DZFM[1:0] DEFAULT 00 DESCRIPTION Selects MUTE flag for output on the MUTE pin (A `1' indicates 1024 consecutive zero input samples on the DAC channels selected. 00: All channels zero 01: Channel 1 zero 10: Channel 2 zero 11: Channel 3 zero
DZFM[1:0] 00 01 10 11
MUTE All channels zero Channel 1 zero Channel 2 zero Channel 3 zero
DAC MUTE MODES
The WM8766 has individual mutes for each of the three DAC channels. Setting MUTE for a channel will apply a `soft' mute to the input of the digital filters of the channel muted. REGISTER ADDRESS 0001001 DAC Mute BIT 5:3 LABEL DMUTE [2:0] DEFAULT 000 DESCRIPTION DAC Soft Mute Select
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WM8766
DMUTE [2:0] 000 001 010 011 100 101 110 111 DAC CHANNEL 1 Not MUTE MUTE Not MUTE MUTE Not MUTE MUTE Not MUTE MUTE DAC CHANNEL 2 Not MUTE Not MUTE MUTE MUTE Not MUTE Not MUTE MUTE MUTE
Preliminary Technical Data
DAC CHANNEL 3 Not MUTE Not MUTE Not MUTE Not MUTE MUTE MUTE MUTE MUTE
Setting the MUTEALL register bit will apply a 'soft' mute to the input of all the DAC digital filters: REGISTER ADDRESS 0000010 DAC Mute BIT 0 LABEL MUTEALL DEFAULT 0 DESCRIPTION Soft Mute Select: 0 : Normal operation 1: Soft mute all channels
Refer to Figure 7 for the plot of application and release of soft mute.
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 17 Application and Release of Soft Mute Figure 17 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024 or more input samples the outputs will be connected directly to VMID if IZD is set. When MUTE is deasserted, the output will restart immediately from the current input sample. Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output.
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Preliminary Technical Data
WM8766
DE-EMPHASIS MODE
Each stereo DAC channel has an individual de-emphasis control bit: REGISTER ADDRESS 0001001 DAC De-Emphahsis Control BIT [8:6] LABEL DEEMPH [1:0] DEFAULT 000 DESCRIPTION De-emphasis Channel Selection Select:
DEEMPH [1:0] 000 001 010 011 100 101 110 111
DAC CHANNEL 1 Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS
DAC CHANNEL 2 Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS
DAC CHANNEL 3 Not DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS Not DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS DE-EMPHASIS
Refer to Figure 27 for details of the De-Emphasis performance at different sample rates.
REGISTER ADDRESS 0000010 DAC DEMP
BIT 1
LABEL DEEMPALL
DEFAULT 0
DESCRIPTION DEMMP Select: 0 : Normal operation 1: De-emphasis all channels
POWERDOWN MODE AND DAC DISABLE
Setting the PDWN register bit immediately powers down the DAC's on the WM8766, overriding the DACD powerdown bits control bits. All trace of the previous input samples are removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised REGISTER ADDRESS 0000010 Powerdown Control BIT 2 LABEL PDWN DEFAULT 0 DESCRIPTION Power Down all DAC's Select: 0: All DAC's enabled 1: All DAC's disabled
The DACs may also be powered down individually by setting the DACPD disable bit. Each Stereo DAC channel has a separate disable DACPD[2:0]. Setting DACPD for a channel will disable the DACs and select a low power mode. REGISTER ADDRESS 0001010 Powerdown Control BIT 3:1 LABEL DACPD[2:0] DEFAULT 000 DESCRIPTION DAC Disable
DACPD [2:0] 000 001 010 011 100 101 110 111
DAC CHANNEL 1 Active DISABLE Active DISABLE Active DISABLE Active DISABLE
DAC CHANNEL 2 Active Active DISABLE DISABLE Active Active DISABLE DISABLE
DAC CHANNEL 3 Active Active Active Active DISABLE DISABLE DISABLE DISABLE
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WM8766
MASTER POWERDOWN
Preliminary Technical Data
This control bit powers down the references for the whole chip. Therefore for complete powerdown, all DACs should be powered down first before setting this bit. REGISTER ADDRESS 0001010 Interface Control BIT 4 LABEL PWRDNALL DEFAULT 0 DESCRIPTION Master Power Down Bit: 0: Not powered down 1: Powered down
MASTER MODE SELECT
Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRCLK and BCLK are outputs and are generated by the WM8766. In Slave mode LRCLK and BCLK are inputs to WM8766. REGISTER ADDRESS 0001010 Interface Control BIT 5 LABEL MS DEFAULT 0 DESCRIPTION DAC Audio Interface Master/Slave Mode Select: 0: Slave mode 1: Master mode
MASTER MODE LRCLK FREQUENCY SELECT
In Master mode the WM8766 generates LRCLK and BCLK. These clocks are derived from the master clock and the ratio of MCLK to LRCLK is set by RATE. REGISTER ADDRESS 0001010 Interface Control BIT 8:6 LABEL RATE [2:0] DEFAULT 010 DESCRIPTION Master Mode MCLK:LRCLK Ratio Select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 101: 768fs
MUTE PIN DECODE
The MUTE pin can either be used as an output or an input. When used as an input the MUTE pins action can be controlled by setting the DZFM bit to select the corresponding DAC for applying the MUTE to. As an output its meaning is selected by the DZFM control bits. By default selecting the MUTE pin to represent if DAC1 has received more than 1024 midrail samples will cause the MUTE pin to assert a softmute on DAC1. Disabling the decode block will cause any logical high on the MUTE pin to apply a softmute to all DAC's. REGISTER ADDRESS 0001100 MUTE Control BIT 6 LABEL MPD DEFAULT 0 DESCRIPTION MUTE Pin Decode Disable: 0: MUTE pin decode enable 1: MUTE pin decode disable
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Preliminary Technical Data
WM8766
DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers
REGISTER ADDRESS 0000000 Digital Attenuation DACL1
BIT 7:0 8
LABEL LDA1[7:0] UPDATE
DEFAULT 11111111 (0dB) Not latched
DESCRIPTION Digital Attenuation data for Left channel DACL1 in 0.5dB steps. See Table 10 Controls simultaneous update of all Attenuation Latches 0: Store LDA1 in intermediate latch (no change to output) 1: Store LDA1 and update attenuation on all channels Digital Attenuation data for Right channel DACR1 in 0.5dB steps. See Table 10. Controls simultaneous update of all Attenuation Latches 0: Store RDA1 in intermediate latch (no change to output) 1: Store RDA1 and update attenuation on all channels. Digital Attenuation data for Left channel DACL2 in 0.5dB steps. See Table 10 Controls simultaneous update of all Attenuation Latches 0: Store LDA2 in intermediate latch (no change to output) 1: Store LDA2 and update attenuation on all channels. Digital Attenuation data for Right channel DACR2 in 0.5dB steps. See Table 10 Controls simultaneous update of all Attenuation Latches 0: Store RDA2 in intermediate latch (no change to output) 1: Store RDA2 and update attenuation on all channels. Digital Attenuation data for Left channel DACL3 in 0.5dB steps. See Table 10 Controls simultaneous update of all Attenuation Latches 0: Store LDA3 in intermediate latch (no change to output) 1: Store LDA3 and update attenuation on all channels. Digital Attenuation data for Right channel DACR3 in 0.5dB steps. See Table 10 Controls simultaneous update of all Attenuation Latches 0: Store RDA3 in intermediate latch (no change to output) 1: Store RDA3 and update attenuation on all channels. Digital Attenuation data for all DAC channels in 0.5dB steps. See Table 10 Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels.
0000001 Digital Attenuation DACR1
7:0 8
RDA1[6:0] UPDATE
11111111 (0dB) Not latched
0000100 Digital Attenuation DACL2
7:0 8
LDA2[7:0] UPDATE
11111111 (0dB) Not latched
0000101 Digital Attenuation DACR2
7:0 8
RDA2[7:0] UPDATE
11111111 (0dB) Not latched
0000110 Digital Attenuation DACL3
7:0 8
LDA3[7:0] UPDATE
11111111 (0dB) Not latched
0000111 Digital Attenuation DACR3
7:0 8
RDA3[7:0] UPDATE
11111111 (0dB) Not latched
0001000 Master Digital Attenuation (all channels)
7:0 8
MASTDA [7:0] UPDATE
11111111 (0dB) Not latched
L/RDAX[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex)
ATTENUATION LEVEL - dB (mute) -127dB : : : -0.5dB 0dB
Table 10 Digital Volume Control Attenuation Levels
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WM8766
SOFTWARE REGISTER RESET
Preliminary Technical Data
Writing to register 11111 will cause a register reset, resetting all register bits to their default values. The device will be held in this reset state until a subsequent register write to any address is completed.
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8766 can be configured using the Control Interface. All unused bits should be set to `0'.
REGISTER R0(00h) R1(01h) B15 0 0 B14 0 0 B13 0 0 B12 0 0 B11 0 0 B10 0 0 B9 0 1 B8 UPDATE UPDATE PL[8:5] R2(02h) 0 0 0 0 0 1 0 IZD ATC PDWN DEEMPALL MUTEALL 100100000 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 011111111 011111111
LDA1[7:0] RDA1[7:0]
R3(03h) R4(04h) R5(05h) R6(06h) R7(07h) R8(08h) R9(09h) R10(0Ah) R12(0Ch)
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1
0 1 1 1 1 0 0 0 1
1 0 0 1 1 0 0 1 0
1 0 1 0 1 0 1 0 0 0 UPDATE UPDATE UPDATE UPDATE UPDATE
PHASE[8:6]
IWL[5:4]
BCP LDA2[7:0] RDA2[7:0] LDA3[7:0] RDA3[7:0] MASTDA[7:0]
LRP
FMT[1:0]
000000000 011111111 011111111 011111111 011111111 011111111
DEEMP[8:6] DACRATE[8:6] MS MPD 0
DMUTE[5:3] PWRDNALL 0 0
DZFM[2:1] DACPD[3:1] 0 0
ZCD
000000000 010000000 000000000
0 0
0
R15(0Fh)
0
0
0
1
1
1
1
0
0
0
MPD
0 RESET
0
0
0
0
000000000 000000000
R31(1Fh)
0
0
1
1
1
1
1
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Preliminary Technical Data
WM8766
DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Passband ripple Stopband Stopband Attenuation Group Delay Table 11 Digital Filter Characteristics f > 0.555fs 0.555fs -60 21 dB fs TEST CONDITIONS DAC Filter 0.05 dB -3dB 0.487fs 0.05 dB 0.444fs MIN TYP MAX UNIT
DAC FILTER RESPONSES
0.2 0 0.15 -20 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 18 DAC Digital Filter Frequency Response - 44.1, 48 and 96KHz
Figure 19 DAC Digital Filter Ripple -44.1, 48 and 96kHz
0.2 0 0 -20
Response (dB)
-0.2
Response (dB)
-40
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 20 DAC Digital Filter Frequency Response - 192KHz
Figure 21 DAC Digital Filter Ripple - 192kHz
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WM8766
DIGITAL DE-EMPHASIS CHARACTERISTICS
0 1 0.5 -2 0
Response (dB)
Preliminary Technical Data
-4
Response (dB)
-0.5 -1 -1.5 -2
-6
-8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 22 De-Emphasis Frequency Response (32kHz)
0
Figure 23 De-Emphasis Error (32KHz)
0.4 0.3
-2 0.2
Response (dB)
-4
Response (dB)
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 24 De-Emphasis Frequency Response (44.1KHz)
0
Figure 25 De-Emphasis Error (44.1KHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 26 De-Emphasis Frequency Response (48kHz)
Figure 27 De-Emphasis Error (48kHz)
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Preliminary Technical Data
WM8766
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 and C5 C2 to C4 C6 C7 C8 C9 R1 SUGGESTED VALUE 10F 0.1F 0.1F 10F 0.1F 10F 33V De-coupling for TESTREF. Filtering for VREFP. Omit if AVDD low noise. Filtering for VREP. Use 0 if AVDD low noise. DESCRIPTION De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Reference de-coupling capacitors for VMID and TESTREF pin.
Table 12 External Components Description
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WM8766
SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS
Preliminary Technical Data
It is recommended that a lowpass filter be applied to the output from each DAC channel for Hi Fi applications. Typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta DAC structure used in WM8766 produces much less high frequency output noise than normal sigma delta DACs. This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment. Figure 28 shows a suitable post DAC filter circuit, with 2x gain. Alternative inverting filter architectures might also be used with as good results.
1.0nF 10uF 1.8k 7.5k
VOUT1L
10k 680pF 4.7k 4.7k
51
OP_FIL
VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R
OP_FIL OP_FIL OP_FIL OP_FIL OP_FIL
Figure 28 Recommended Post DAC Filter Circuit
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Preliminary Technical Data
WM8766
PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) DM007.D
b
28
e
15
E1
E
1
D
14
GAUGE PLANE
c A A2 A1
L
0.25
L1
-C0.10 C
SEATING PLANE
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 0.125 REF o 4 JEDEC.95, MO-150
MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8766 IMPORTANT NOTICE
Preliminary Technical Data
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
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ADDRESS:
Wolfson Microelectronics plc 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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