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| Ordering number : EN6067 Monolithic Digital IC LB1923M Power Brushless Motor Pre-Driver IC for OA Equipment Overview The LB1923M is a pre-driver IC that supports direct PWM drive and is appropriate for the power brushless motors used in office automation equipment. A motor drive circuit with the desired output capability (voltage and current characteristics) can be constructed by attaching a driver array at the IC output. The LB1923M includes on chip a speed control circuit that allows the motor speed to be varied using an external clock. including lock protection, current limiter, and thermal shutdown protection circuits. Package Dimensions unit: mm 3148-QFP44MA [LB1923M] 13.2 10.0 1.0 0.8 0.35 33 34 23 22 1.6 1.0 0.2 Features * * * * * * * Direct PWM drive output Speed discriminator + PLL speed control circuit FG and integrating amplifiers Forward/reverse switching circuit Braking circuit (short braking) Speed lock detection output Full complement of on-chip protection circuits, 13.2 10.0 0.8 1.0 1.6 44 1 12 11 2.8max 1.0 0.1 2.5 11.6 0.8 Specifications Absolute Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Maximum input current Output current Allowable power dissipation Operating temperature Storage temperature Symbol VCC max IREG max IO max Pd max Topr Tstg VREG pin UL, VL, and WL outputs Conditions SANYO: QIP44MA Ratings 9 10 30 0.9 -20 to +80 -55 to +150 Unit V mA mA W C C Allowable Operating Ranges at Ta = 25C Parameter Supply voltage Input current range FG Schmitt output applied voltage FG Schmitt output current Lock detection output current Symbol VCC IREG VFGS IFGS ILD VREG pin (7 V) Conditions Ratings 4.4 to 7.0 1 to 5 0 to 8 0 to 5 0 to 20 Unit V mA V mA mA Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 63099TH(OT) No. 6067-1/17 LB1923M Pd max -- Ta 1.2 Allowable power dissipation, Pdmax - W 1.0 0.9 0.8 0.6 0.504 0.4 0.2 0 -20 0 20 40 60 80 100 120 Ambient temperature, Ta - C Electrical Characteristics at Ta = 25C, VCC = 6.3 V Parameter Symbol ICC1 Current drain ICC2 ICC3 ICC4 Output saturation voltage Output current Output leakage current Output off voltage [Hall Amplifier] Input bias current Common-mode input voltage range Hall input sensitivity Hysteresis Input voltage low high Input voltage high low [CR Oscillator] Output high-level voltage VOH(CR)1 VOH(CR)2 VCC = 5 V VOL(CR)1 VOL(CR)2 f (CR) V(CR)1 V(CR)2 VOH(RK)1 VOH(RK)2 VOL(RK)1 VOL(RK)2 ICHG1 ICHG2 f (RK) V(RK)1 V(RK)2 VCC = 5 V C = 0.068 F 2.2 1.7 VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V R = 75 k, C = 1500 pF 1.4 1.1 3.1 2.4 1.5 1.1 3.4 2.7 1.8 1.4 19 1.6 1.3 1.8 1.5 3.7 3.0 2.1 1.7 V V V V kHz Vp-p Vp-p IHB(HA) VICM VIN(HA) VIN(HA) VSLH VSHL -4 1.5 60 17 8 -30 32 16 -16 60 30 -8 -1 VCC - 1.5 A V mVp-p mV mV mV VO (sat) IO IO leak VO off In stop mode VCC = 5 V VCC = 5 V, In stop mode UL, VL, WL output, IO = 20 mA UH, VH, WH output, VOUT = 1.4 V UL, VL, WL output UH, VH, WH output -20 Conditions Ratings min typ 42 10 38 8 0.2 -16 max 60 20 55 18 0.7 -12 100 0.5 Unit mA mA mA mA V mA A V Output low-level voltage Oscillator frequency Amplitude [CROCK Oscillator] 3.2 2.5 0.8 0.6 -17 9 3.5 2.8 1.1 0.9 -13 13 35 2.4 1.9 3.8 3.1 1.4 1.2 -9 17 V V V V A A Hz Output high-level voltage Output low-level voltage External capacitor charge current External capacitor discharge current Oscillator frequency Amplitude 2.6 2.1 Vp-p Vp-p Continued on next page. No. 6067-2/17 LB1923M Continued from preceding page. Parameter [VCO Oscillator] Pin C output high-level voltage VOH(C)1 VOH(C)2 VOL(C)1 VOL(C)2 f (C) V(C) VRF TSD TSD VREG VIO(FG) IB(FG) VOH(FG) VOL(FG) Gain: 100x 3 100 180 250 16 f (FG) = 2 kHz VO(FGS) IL(FGS) VOH(D) VOL(D) VOH(P)1 VOH(P)2 VOL(P)1 VOL(P)2 VOH(VCO) VOL(VCO) VOL(LD) IL(LD) ILD = 10 mA VO = VCC -6.25 VCC = 5 V VCC = 5 V 4.05 3.25 1.85 1.25 IO(FGS) = 2 mA VO = VCC VCC - 1.0 VCC - 0.7 0.4 1.1 45 51 Design target value Design target value 0.2 0.4 VCC = 5 V VCC = 5 V 4.1 3.2 3.6 2.8 4.3 3.4 3.9 3.0 4.6 3.6 4.1 3.2 1.0 0.6 V V V V MHz Vp-p Symbol Conditions Ratings min typ max Unit Pin C output low-level voltage Oscillator frequency Amplitude [Current Limiter Operation] Limiter [Thermal Shutdown Operation] Thermal shutdown operating temperature Hysteresis [VREG Pin] VREG pin voltage [FG Amplifier] Input offset voltage Input bias current Output high-level voltage Output low-level voltage FG input sensitivity Schmitt amplitude for the next stage Operating frequency range Open-loop gain [FGS Output] Output saturation voltage Output leakage current [Speed Discriminator Output] Output high-level voltage Output low-level voltage [Speed Control PLL Output] 0.47 0.52 0.57 V 150 180 30 C C 6.7 7.1 7.4 V -10 -1 VCC - 1.5 VCC - 1 1 +10 +1 mV A V 1.5 V mV mV kHz dB 0.1 0.5 10 V A V V 4.35 3.55 2.15 1.55 4.65 3.83 2.45 1.85 V V V V Output high-level voltage Output low-level voltage [VCO PLL Output] Output high-level voltage Output low-level voltage [Lock Detection] Output saturation voltage Output leakage current Lock range [Integrator] Input offset voltage Input bias current Output high-level voltage Output low-level voltage Open-loop gain Gain-bandwidth product Reference voltage [Filter Amplifier] Input bias current Output high-level voltage Output low-level voltage Reference voltage 5.3 5.6 0.4 11 V V 0.1 0.5 10 +6.25 V A % VIO(INT) IB(INT) VOH(INT) VOL(INT) -10 -0.4 VCC - 1.2 60 1.6 VCC - 0.8 0.8 +10 +0.4 mV A V 1.2 V dB MHz VB(INT) IB(FIL) VOH(FIL) VOL(FIL) VB(FIL)1 VB(FIL)2 VCC = 5 V -5% VCC/2 5% V -0.4 VCC - 1.2 -5% 1.5 VCC - 0.8 0.8 2.0 1.6 +0.4 A V 1.2 +5% 1.7 V V V Continued on next page. No. 6067-3/17 LB1923M Continued from preceding page. Parameter [S/S Pin] Output high-level voltage Output low-level voltage Hysteresis Pull-up resistance [F/R Pin] Input high-level voltage Input low-level voltage Hysteresis Pull-up resistance [BR Pin] Input high-level voltage Input low-level voltage Hysteresis Pull-up resistance [CLK Pin] Input high-level voltage Input low-level voltage Hysteresis Pull-up resistance Input frequency [N1 Pin] Input high-level voltage Input low-level voltage Hysteresis Pull-up resistance [N2 Pin] Input high-level voltage Input low-level voltage Hysteresis Pull-up resistance [Low Voltage Protection] Operating voltage Release voltage Hysteresis VSDL VSDH VSD 0.15 3.75 4.0 0.25 0.35 V V V VIH(N2) VIL(N2) VIN(N2)1 VIN(N2)2 VCC = 5 V RU(N2) 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k VIH(N1) VIL(N1) VIN(N1)1 VIN(N1)2 VCC = 5 V RU(N1) 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k VIH(CLK) VIL(CLK) Design target value Design target value 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 16 V V V V k kHz VIH(BR) VIL(BR) VIN(BR)1 VIN(BR)2 VCC = 5 V RU(BR) 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k VIH(F/R) VIL(F/R) VIN(F/R)1 VIN(F/R)2 VCC = 5 V RU(F/R) 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k VOH(S/S) VOL(S/S) VIN(S/S)1 VIN(S/S)2 VCC = 5 V RU(S/S) 4.0 0 0.35 0.24 45 0.45 0.34 63 VCC 1.5 0.55 0.44 85 V V V V k Symbol Conditions Ratings min typ max Unit VIN(CLK)1 Design target value VIN(CLK)2 VCC = 5 V, Design target value RU(CLK) f (CLK) Speed Discriminator Counts N1 High or open High or open L L N2 High or open L High or open L Number of counts 64 256 128 512 No. 6067-4/17 LB1923M Three-Phase Logic Truth Table (A high (H) input is the state where IN+ > IN-.) F/R=L Item 1 2 3 4 5 6 IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R=H IN2 H H L L L H IN3 L H H H L L Output Source VH WH WH UH UH VH Sink UL UL VL VL WL WL S/S Pin High or open L Stop Start BRK Pin High or open L Brake Released Pin Assignment VREG 33 CR 34 CROCK 35 R 36 C 37 (frame) GND 38 (frame) GND 39 (frame) GND 40 FILO 41 FILI 42 INTREF 43 TOC 44 1 INTOUT 32 31 30 29 28 27 26 25 24 IN3+ 23 22 IN2- 21 IN2+ 20 IN1- 19 IN1+ 18 GND (frame) 17 GND (frame) 16 GND (frame) 15 FGIN- 14 FGIN+ 13 FGOUT 12 FGSOUT 11 N2 Top view A11831 VCC LB1923M 2 INTIN 3 DOUT 4 POUT 5 LD 6 BR 7 F/R 8 CLK 9 S/S 10 N1 IN3- WH WL UH VH RF UL VL No. 6067-5/17 LB1923M Pin Functions Pin IN1+, IN1- IN2+, IN2- IN3+, IN3- UH VH WH UL VL WL VCC VREG GND CR CROCK R C FILI FILO DOUT ROUT LD INTREF INTIN INTOUT TOC FGIN+ FGIN- FGOUT FGSOUT RF S/S F/R BR CLK N1 N2 Pin No. 19, 20 21, 22 23, 24 27 29 31 26 28 30 32 33 16 to 18 38 to 40 34 35 36 37 42 41 3 4 5 43 2 1 44 15 14 13 12 25 9 7 6 8 10 11 Hall inputs for the phases The logic high level corresponds to the state VIN+ > VIN-. Outputs. These are fixed-current source outputs. Function The duty is controlled by the output pin PWM. These are open collector sink outputs. A capacitor must be inserted between this pin and ground to prevent noise entering the circuit. 7-V shunt regulator output Ground Used to set the PWM circuit oscillator frequency. Motor lock protection circuit. Reference signal oscillator connection. Used by the circuit that prevents incorrect operation if the clock line is disconnected. A capacitor must be inserted between this pin and ground. VCO circuit. This pin sets the charge and discharge current. A resistor must be inserted between this pin and ground. VCO oscillator connection. A capacitor must be inserted between this pin and ground. Select a value for that capacitor such that the C pin oscillator frequency does not exceed 1 MHz. Inverting input to the VCO filter amplifier. This pin is connected to the VCO PLL through an (IC internal) 10-kW resistor. VCO filter amplifier output. This pin is connected to the VCO circuit internally. Speed discriminator output. A low level is output when the motor is over speed. PLL circuit output. Outputs the result of the phase comparison between 1/2fCLK and 1/2fFG. Lock detection output. This is an open collector output. This pin outputs a low level when the motor speed is within the locked range (6.25%). Integrating amplifier noninverting input (the 1/2 VCC potential) Integrating amplifier inverting input Integrating amplifier output Torque command input. Normally, this pin is connected to the INTOUT pin. Lowering the TOC pin potential increases the torque by changing the PWM signal duty for the UL, VL, and WL outputs. FG amplifier noninverting input (the 1/2 VCC potential). A capacitor must be inserted between this pin and ground. FG amplifier inverting input FG amplifier output FG amplifier (post-Schmitt) output. This is an open collector output. Output current detection. A resistor must be inserted between this pin and ground. This resistor sets the maximum output current IOUT to be 0.5/Rf. Start/stop control input. Apply a low level for start, and either a high level or an open (high-impedance) state for start. Forward/reverse control input. Apply a low level for forward, and either a high level or an open (high-impedance) state for reverse. Braking control input (short braking operation). Apply a low level for start, and either a high level or an open (highimpedance) state to brake the motor. External clock signal input. 10 kHz max. Speed discriminator count value selection inputs No. 6067-6/17 FGO FGS DOUT LD S/S BR FR INT POUT REF VCC INT IN INT OUT FGIN- LD VCC - + Speed discriminator - - F/R FGIN+ + + FG FILTER Internal Equivalent Circuit Block Diagram FG RST BR ROCK OSC CROCK IN1+ IN1- IN2+ IN2- LOGIC IN3+ IN3- LB1923M CLK CLK Speed control system PLL 1.3VREF S/S HALL HYS AMP VREG 1/N LVSD COMP VREG VCO system PLL LOGIC TSD CR OSC N1 N2 CURR LIM PRI DRIVER FILI - + VCO FILO C R N1 N2 GND CR RF TOC UL VL WL UH VH WH A11833 No. 6067-7/17 LB1923M Sample Application Circuit 24V + + 33 34 35 36 37 38 39 40 41 42 43 44 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 LB1923M 17 16 15 14 13 12 + 2 3 4 5 6 7 8 9 10 11 LD BR F/R CLK S/S FGS A11832 No. 6067-8/17 LB1923M IC Operation Description 1. Speed Control Circuit This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The speed discriminator and the PLL circuit output (using a charge pump technique) an error signal once every two FG periods. As compared to the earlier technique in which only a speed discriminator circuit was used, the combination of a speed discriminator and a PLL circuit allows variations in motor speed to be better suppressed when a motor that has large load variations is used. The FG servo frequency is controlled to be the same frequency as the clock signal input to the CLK pin. This means that the motor speed can be changed by changing the clock frequency. 2. VCO Circuit The LB1821M includes an on-chip VCO circuit to generate the reference signal for the speed discriminator circuit. The reference signal frequency is determined by the following formula. fVCO = fCLK x number of counts fVCO: Reference signal frequency fCLK: Frequency of the externally input clock signal The range over which the reference signal can be varied is determined by the resistor and capacitor connected to the R pin (pin 36) and the C pin (pin 37) and by the VCO loop filter constants (the external constants connected to pins 41 and 42). (Reference Values) Supply voltage VCC = 5 V VCC = 6.3 V R (k) 4.7 4.7 C (pF) 390 820 The value of R must not be less than 2.7 k. Applications can handle a wider range of speed variations than would be possible if a fixed number of counts was used by changing the number of discriminator counts (which is related to the divisor in the VCO circuit). The number of counts can be switched between 64, 128, 256, and 512 by setting the N1 (pin 10) and N2 (pin 11) pins. 3. Output Drive Circuit To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with which the output is on. Since the (external) output switching is handled by the upper side output transistors, a Schottky diode or similar device must be connected between the output (OUT) and ground. This is because a through current will flows at the instant the upper side output transistors turn on if a diode with a short reverse recovery time is not used. A rectifying diode can be used between OUT and VCC. Transistors that have no parasitic diodes must be used for the lower side output transistors. If these transistors have parasitic diode components, then through currents will occur due to the reverse recovery time of the parasitic diodes despite the inclusion of the external Schottky diodes. 4. Current Limiter Circuit The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.52 V (typical), Rf: current detection resistor). The current limitation operation consists of reducing the output duty to suppress the current. 5. Speed Lock Range The speed lock range is 6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to the speed error to control the motor speed to be within the lock range. 6. Notes on the PWM Frequency The PWM frequency is determined by the resistor and capacitor connected to the CR pin. fPWM 1/(0.48 x C x R) A PWM frequency of between 15 and 25 kHz is desirable. If the PWM frequency is too low, the motor may resonate at the PWM frequency during motor control, and if that frequency is in the audible range, that resonation may result in audible noise. If the PWM frequency is too high, the output transistor switching loss will increase. The external resistor must not have a value under 30 k. No. 6067-9/17 LB1923M 7. Hall Input Signals Input signals with an amplitude greater than the hysteresis (60 mV, maximum) are required for the Hall inputs. An input amplitude of 100 mV or greater is desirable, taking noise and other considerations into account. The Hall input DC voltage must be set to fall within the common-mode input voltage range specifications. 8. Forward/Reverse (F/R) Switching The F/R pin can be used to switch the motor direction. The direction can be switched with the F/R pin even if the motor is turning. The IC circuit is designed to compensate for the through currents that occur when the direction is switched. However, caution is required with respect to increases in the VCC voltage (due to motor current returning to the power system instantaneously) during direction switching. If this is a problem, try increasing the capacitance of the capacitor connected between the power supply and ground. 9. Brake Switching The LB1923M implements a short braking technique in which the upper side transistors (the external transistors) for all phases are turned on. (The lower side transistors for all phases are turned off.) This means that the output current during braking does not pass through the Rf (the current detection resistor) and therefore that the current limiter does not function. Thus caution is required. During braking, the upper side transistors operate at a 100% duty, regardless of the motor speed. The braking function can be operated and released in the start state. Thus motor start and stop control can be performed from the brake pin with the S/S pin at the low level, i.e., with the system in the start state. If the startup time is a problem, the motor can be started with a shorter startup time by using the brake pin for motor start/stop control than it can with the S/S pin. (This is because the stop state is a power saving state, and restarting from this state requires waiting the time required for the VCO circuit to stabilize.) 10. Constraint Protection Circuit The LB1923M includes an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. If the LD output remains high (indicating the locked state) for a fixed period in the start state, the upper side (external) transistors are turned off. This time is set by the capacitance of the capacitor attached to the CROCK pin. A time of a few seconds can be set with a capacitance of under 0.1 F. No. 6067-10/17 LB1923M 15. VREG Pin If a motor drive system is formed from a single power supply, the VREG pin (pin 33) can be used to create the powersupply voltage (about 6.3 V) for this IC. The VREG pin is a shunt regulator and generates a voltage of about 7 volts by passing a current through an external resistor. A stable voltage can be generated by setting the current to value in the range 1 to 7 mA. The external transistors must have current capacities of at least 80 mA (to cover the ICC + Hall bias current + output current Integrating amplifier related external circuit Added circuit S/Ssignal - + A11834 No. 6067-11/17 LB1923M Pin Functions Pin No. Pin Functions Equivalent circuit VCC 1 INTOUT Integrating amplifier output (speed control) 1 20 k VCC 2 INTIN Integrating amplifier inverting input 30 k 200 200 43 Integrating amplifier noninverting input (a potential of 1/2 VCC) 2 30 k 43 INTREF VCC 3 DOUT Speed discriminator output Acceleration high, deceleration low 3 VCC 4 POUT Speed control system PLL output Outputs the phase comparison result for 1/2 fCLK and 1/2 fFG. 4 VCC 5 5 LD Speed lock detection output Goes low when the motor speed is within the speed lock range (6.25%). Continued on next page. No. 6067-12/17 LB1923M Continued from preceding page. Pin No. Pin Functions Equivalent circuit VCC 6 BR Brake control (short braking operation) Low: 0 to 1.5 V High: 4.0 V to VCC Goes high when left open. High or open for brake mode operation. The hysteresis is about 0.45 V. 63 k 200 6 VCC 7 F/R Forward/reverse control Low: 0 to 1.5 V High: 4.0 V to VCC An open state functions as a high-level input. Low for forward. The hysteresis is about 0.45 V. 63 k 200 7 VCC 8 CLK External clock signal input Low: 0 to 1.5 V High: 4.0 V to VCC An open state functions as a high-level input. The hysteresis is about 0.45 V. f = 10 kHz, maximum 63 k 200 8 VCC 9 S/S Start/stop control Low: 0 to 1.5 V High: 4.0 V to VREG An open state functions as a high-level input. Low for start. The hysteresis is about 0.45 V. 63 k 200 9 VCC 10 N1 Speed discriminator count switching Low: 0 to 1.5 V High: 4.0 V to VCC An open state functions as a high-level input. The hysteresis is about 0.45 V. 63 k 200 10 Continued on next page. No. 6067-13/17 LB1923M Continued from preceding page. Pin No. Pin Functions Equivalent circuit VCC 11 N2 Speed discriminator count switching Low: 0 to 1.5 V High: 4.0 V to VCC An open state functions as a high-level input. The hysteresis is about 0.45 V. 63 k 200 11 VCC 12 12 FGSOUT FG amplifier output (after the Schmitt circuit) This is an open collector output. VCC 13 FGOUT FG amplifier output This pin is connected to the FG Schmitt comparator circuit internally in the IC. 13 FG Schmitt comparator VCC 20 k 14 15 FGIN- FGIN+ FG amplifier inputs An initial reset is applied to the logic circuit block by connecting a capacitor (of about 0.1 F) between the FGIN+ pin and ground. FG reset circuit 15 200 200 14 20 k 16 to 18 38 to 40 GND Ground connections These pins are all connected internally to the frame. Continued on next page. No. 6067-14/17 LB1923M Continued from preceding page. Pin No. Pin Functions Equivalent circuit VCC 19 20 21 22 23 24 IN1+ IN1- IN2+ IN2- IN3+ IN3- Hall inputs High is defined as IN+ > IN-, and low as the opposite. An amplitude of 100 mV p-p (differential) or more is desirable in the Hall signals. Connect capacitors between the IN + and IN- pins if noise on the Hall signals causes problems. 20 22 24 200 200 19 21 23 VCC 25 RF Output current detection Connect a resistor between this pin and ground. The output limitation maximum current, IOUT, is set to be 0.52/Rf by this resistor. 200 25 VCC 26 28 30 This IC implements duty control using output signal PWM. These are open collector sink outputs. 26 28 30 UL VL WL V VCC 27 29 31 UH VH WH Outputs (Fixed current source outputs) 27 29 31 2 k 32 VCC Power-supply voltage Connect a capacitor between this pin and ground for power supply stabilization. Continued on next page. No. 6067-15/17 LB1923M Continued from preceding page. Pin No. Pin Functions Equivalent circuit 200 33 33 VREG 7-V shunt regulator output VCC 34 CR PWM oscillator frequency setting 200 1 k 34 VCC 35 CROCK Sets the operating time for the lock protection circuit. A protection operating time of about 2.1 seconds can be set by connecting a capacitor (of about 0.047 F) between this pin and ground. 200 35 VCC 36 R Setting for the charge current used for the VCO circuit C pin Connect a resistor between this pin and ground. The value of that resistor must not be lower than 2.7 k. 200 36 VCC 37 C VCO oscillator connection. This pin sets the VCO frequency. Connect a capacitor between this pin and ground. Set the value of the capacitor so that the oscillator frequency does not exceed 1 MHz. 200 37 Continued on next page. No. 6067-16/17 LB1923M Continued from preceding page. Pin No. Pin Functions Equivalent circuit VCC 200 41 FILO VCO filter amplifier output This pin is connected to the VCO circuit internally in the IC. VCO input 41 VCC 43 k 10 k 42 FILI VCO filter amplifier inverting input This pin is connected through a 10-k resistor internally in the IC to the VCO system PLL output. 20 k VCO PLL output 42 200 VCC 44 TOC Torque command input This pin is normally connected to the INT.OUT pin. When the TOC voltage falls, the PWM duty is increased. Do not apply a voltage in excess of VCC - 0.5 V. (An input from a normal operational amplifier is desirable.) CR oscillation signals 200 44 Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1999. Specifications and information herein are subject to change without notice. PS No. 6067-17/17 |
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