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EDI88512C
HI-RELIABILITY PRODUCT
512Kx8 Monolithic SRAM CMOS
FEATURES
s 512Kx8 bit CMOS Static s Random Access Memory * Access Times of 70, 85, 100ns * Data Retention Function (LP version) * TTL Compatible Inputs and Outputs * Fully Static, No Clocks s 32 lead JEDEC Approved Evolutionary Pinout * Ceramic Sidebrazed 600 mil DIP (Package 9) * Ceramic SOJ (Package 140) s Single +5V (10%) Supply Operation The EDI88512C is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. Both the DIP and CSOJ packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128C. Pins 1 and 30 become the higher order addresses. A Low Power version with Data Retention (EDI88512LP) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION PIN DESCRIPTION TOP VIEW
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AO I/OO I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 VCC 31 A15 30 A17 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
I/O0-7 A0-18 WE CS OE VCC VSS NC
Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power (+5V 10%) Ground Not Connected
BLOCK DIAGRAM
Memory Array
AO-18
Address Buffer
Address Decoder
I/O Circuits
I/OO-7
WE CS OE
February 2001 Rev. 11
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White Electronic Designs Corporation * www.whiteedc.com * (602) 437-1520
EDI88512C
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ 0 to +70 -40 to +85 -55 to +125 -65 to +150 1 20 175 C C C C W mA C -0.5 to 7.0 Unit V OE X H L X CS H L L L WE X H H L
TRUTH TABLE
Mode Standby Output Deselect Read Write Output High Z High Z Data Out Data In Power Icc2, Icc3 Icc1 Icc1 Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 -- -- Max 5.5 0 Vcc +0.5 +0.8 Unit V V V V
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C)
Parameter Address Lines Data Lines Symbol CI CO Condition VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz Max Unit 12 14 pF pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS (VCC = 5V, *TA = -55C to +125C)
Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage Symbol ILI ILO ICC1 ICC2 ICC3 VOL VOH VIN = 0V to VCC VI/O = 0V to VCC WE, CS = VIL, II/O = 0mA, Min Cycle (70-100ns) CS VIH, VIN VIL, VIN VIH CS VCC -0.2V VIN Vcc -0.2V or VIN 0.2V IOL = 2.1mA IOH = -1.0mA C LP Conditions Min -- -- -- -- -- -- -- 2.4 Typ* -- -- 45 3 -- -- -- -- Max 10 10 75 10 5 2 0.4 -- Units A A mA mA mA mA V V
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480
480
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
VSS to 3.0V 5ns 1.5V Figure 1
Q 255 30pF
Q 255 5pF
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
2
EDI88512C
AC CHARACTERISTICS - READ CYCLE (VCC = 5.0V, VSS = 0V, TA = 0C to +70C)
Symbol JEDEC Alt. tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ 5 0 25 10 35 5 0 30 10 25 10 45 5 0 30 70ns Min 70 70 70 10 30 10 50 Max Min 85 85 85 10 30 85ns Max Min 100 100 100 100ns Max Units ns ns ns ns ns ns ns ns ns
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1)
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS - WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = 0C to +70C)
Symbol Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) JEDEC tAVAV tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tWLEH tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX Alt. tWC tCW tCW tAS tAS tAW tAW tWP tWP tWR tWR tDH tDH tWHZ tDW tDW tWLZ Min 70 60 60 0 0 65 65 50 50 0 0 0 0 0 40 30 5 25 70ns Max Min 85 70 70 0 0 70 70 55 55 0 0 0 0 0 40 35 5 30 85ns Max Min 100 80 80 0 0 80 80 60 60 0 0 0 0 0 40 40 5 30 100ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested.
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White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
EDI88512C
FIG. 2
TIMING WAVEFORM - READ CYCLE
ADDRESS
tAVAV tAVQV
tAVAV
ADDRESS
ADDRESS 1 ADDRESS 2
CS
tELQV tELQX
OE
tEHQZ
tAVQV
DATA I/O
tAVQX
DATA 1 DATA 2
tGLQV tGLQX
DATA OUT
tGHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3
WRITE CYCLE - WE CONTROLLED
tAVAV
ADDRESS
tAVWH tELWH
CS
tWHAX
tAVWL
WE
tWLWH tDVWH tWHDX
DATA IN
DATA VALID
tWLQZ
DATA OUT
HIGH Z
tWHQX
WRITE CYCLE 1, WE CONTROLLED
FIG. 4
WRITE CYCLE - CS CONTROLLED
ADDRESS
tAVAV
WS32K32-XHX
tAVEH tELEH tEHAX tAVEL tWLEH tDVEH tEHDX
CS
WE
DATA IN DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
4
EDI88512C
DATA RETENTION CHARACTERISTICS (EDI88512LP ONLY) (TA = -55C to +125C)
Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time Operation Recovery Time Sym VDD ICCDR TCDR TR Conditions VDD = 2.0V CS VDD -0.2V VIN VDD -0.2V or VIN 0.2V Min 2 - 0 TAVAV Typ - - - - Max - 185 - - Units V A ns ns
FIG. 5
DATA RETENTION - CS CONTROLLED
Data Retention Mode
Vcc
4.5V VDD
WS32K32-XHX
4.5V
tCDR
CS
CS = VDD -0.2V
tR
DATA RETENTION, CS CONTROLLED
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White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
EDI88512C
PACKAGE 9:
32 LEAD SIDEBRAZED CERAMIC DIP
1.616 1.584
Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500
0.060 0.040
0.620 0.600
0.100 TYP
0.155 0.115
0.600 NOM
ALL DIMENSIONS ARE IN INCHES
PACKAGE 140:
32 LEAD CERAMIC SOJ
0.010 0.006 0.019 0.015
0.840 0.820
0.444 0.430
0.379 0.155 0.106
0.050 TYP
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
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EDI88512C
ORDERING INFORMATION EDI 8 8 512 C X X X
WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 512Kx8 TECHNOLOGY: C = CMOS Standard Power LP = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) N = 32 lead Ceramic SOJ (Package 140) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55C to +125C I = Industrial -40C to +85C C = Commercial 0C to +70C
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White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520

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