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| SPICE Device Model SUP/SUB70N03-09BP Vishay Siliconix N-Channel 30-V (D-S), 175C MOSFET PWM Optimized CHARACTERISTICS * N- and P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. SUBCIRCUIT MODEL SCHEMATIC A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71701 02-Oct-01 www.vishay.com 1 SPICE Device Model SUP/SUB70N03-09BP Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbo l VGS(th) ID(on) Test Condition Simulate d Data 1.5 604 0.007 0.010 0.0085 0.0095 45 0.92 1484 465 153 15 5 6 10 13 26 34 20 Measured Data Unit VDS = VGS, ID = 250A VDS = 5 V, VGS = 10V VGS = 10V, ID = 30A VGS = 4.5V, ID = 20A V A 0.007 0.010 Drain-Source On-State a Resistance rDS(on) VGS = 10V, ID = 30A, TJ = 125C VGS = 10V, ID = 30A, TJ = 175C Forward Transconductance Forward Voltage Dynamic b a a gfs VSD Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf trr VDS = 15V, ID = 30A IS = 70A, VGS = 0 V 45 1.1 1500 530 240 15.5 5 6 10 8 25 9 30 S V Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge c c VGS = 0V, VDS = 25V, f = 1 MHz VDS = 15V, VGS = 5V, ID = 70A pf Gate-Source Charge Gate-Drain Charge Rise Time Fall Time c c c nC Turn-On Delay Time Turn-Off Delay Time c c VDD = 15V, RL = 0.21 ID 70A, VGEN = 10V, RG = 2.5 IF = 70A, di/dt = 100 A/s ns Reverse Recovery Time Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 71701 02-Oct-01 SPICE Device Model SUP/SUB70N03-09BP Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 71701 02-Oct-01 www.vishay.com 3 |
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