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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
D
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CMOS/EEPROM/EPROM Technologies on a Single Device - Mask-ROM Devices for High-Volume Production - One-Time-Programmable (OTP) EPROM Devices for Low-Volume Production - Reprogrammable EPROM Devices for Prototyping Purposes Internal System Memory Configurations - On-Chip Program Memory Versions - ROM: 4K to 48K Bytes - EPROM: 16K to 48K Bytes - ROM-less - Data EEPROM: 256 or 512 Bytes - Static RAM: 256 to 3.5K Bytes - External Memory / Peripheral Wait States - Precoded External Chip-Select Outputs in Microcomputer Mode Flexible Operating Features - Low-Power Modes: STANDBY and HALT - Commercial, Industrial, and Automotive Temperature Ranges - Clock Options - Divide-by-4 (0.5 MHz - 5 MHz SYSCLK) - Divide-by-1 (2 MHz - 5 MHz SYSCLK) Phase-Locked Loop (PLL) - Supply Voltage (VCC): 5 V 10% Eight-Channel 8-Bit Analog-to-Digital Converter 1 (ADC1) Two 16-Bit General-Purpose Timers On-Chip 24-Bit Watchdog Timer Two Communication Modules - Serial Communications Interface 1 (SCI1) - Serial Peripheral Interface (SPI) Flexible Interrupt Handling TMS370 Series Compatibility CMOS/Package /TTL-Compatible I / O Pins - 64-Pin Plastic and Ceramic Shrink Dual-In-Line Packages / 44 Bidirectional, 9 Input Pins - 68-Pin Plastic and Ceramic Leaded Chip Carrier Packages / 46 Bidirectional, 9 Input Pins - All Peripheral Function Pins Are Software Configurable for Digital I / O
C3 C4 C5 C6 C7 VCC2 VSS2 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2/PWM
10 11 12 13 14 15 16
VSS1 C2 C1 MC C0 B7 B6 B5 B4 B3 B2 B1 B0 D0 / CSE2 / OCF VCC2 VSS2 VCC1 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 T2AIC1/CR SCICLK SCIRXD SCITXD XTAL2/CLKIN XTAL1 V CC1 V CC3 V SS3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 D1 / CSH3 D2 / CSH2 D3 / SYSCLK D4 / R / W D5 / CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC/CR T1PWM T1EVT
FN / FZ PACKAGE ( TOP VIEW )
JN / NM PACKAGE ( TOP VIEW )
B5 B6 B7 C0 MC C1 C2 VSS1 C3 C4 C5 C6 C7 AN0 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2 / PWM T2AIC1 / CR SCICLK SCIRXD SCITXD XTAL2 / CLKIN XTAL1 VCC1 VCC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 B4 B3 B2 B1 B0 D0 / CSE2 / OCF VSS1 VCC1 D1 / CSH3 D3 / SYSCLK D4 / R / W D6 / CSH1 / EDS D7 / CSE1 / WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC / CR T1PWM AN7 T1EVT VSS1 AN6 AN5 AN4 AN3 AN2 AN1 VSS3
D
Workstation/PC-Based Development System - C Compiler and C Source Debugger - Real-Time In-Circuit Emulation - Extensive Breakpoint / Trace Capability - Software Performance Analysis - Multi-Window User Interface - Microcontroller Programmer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
Pin Descriptions
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PIN NAME ALTERNATE FUNCTION DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 SDIP (64) 15 16 17 18 19 20 21 22 60 61 62 63 64 1 2 3 LCC (68) 17 18 19 20 21 22 23 24 65 66 67 68 1 2 3 4 I/O DESCRIPTION A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 I/O Single-chip mode: Port A is a general-purpose bidirectional I/O port. Expansion mode: Port A can be individually programmed as the external bidirectional data bus (DATA0 - DATA7). ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 I/O Single-chip mode: Port B is a general-purpose bidirectional I/O port. Expansion mode: Port B can be individually programmed as the low-order address output bus (ADDR0 - ADDR7). C0 C1 C2 C3 C4 C5 C6 C7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 NMI -- -- E0 E1 E2 E3 E4 E5 E6 E7 4 6 7 9 10 11 12 13 5 7 8 10 11 12 13 14 I/O Single-chip mode: Port C is a general-purpose bidirectional I/O port. Expansion mode: Port C can be individually programmed as the high-order address output bus (ADDR8 - ADDR15). INT1 INT2 INT3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 50 49 48 14 34 35 36 37 38 39 42 32 33 51 52 51 50 36 37 38 39 40 41 42 43 34 35 53 I I/O I/O External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin I ADC1 analog input (AN0 - AN7) or positive reference pins (AN1 - AN7) Port E can be individually programmed as general-purpose input pins if not used as ADC1 analog input or positive reference input. VCC3 VSS3 ADC1 positive-supply voltage and optional positive-reference input pin ADC1 ground reference pin RESET I/O System reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit. Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, also EPROM VPP. Internal oscillator crystal input / external clock source input Internal oscillator output for crystal Positive supply voltage MC 5 6 I XTAL2/CLKIN XTAL1 VCC1 29 30 31 32 I O 31, 57 33, 61 VCC2 -- 15,63 Positive supply voltage I = input, O = output Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK. 2
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
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PIN NAME VSS1 VSS2 ALTERNATE FUNCTION SDIP (64) LCC (68) 9 I/O DESCRIPTION 8, 58,40 -- Ground reference for digital logic 16,62 Ground reference for digital I / O logic FUNCTION A B Single-chip mode: Port D is a general-purpose bidirectional I / O port. Each of the port D pins can be individually configured as a general-purpose I / O pin, A) primary memory control signal (function A), or secondary memory control signal (function B). All chip selects are independent and can be used for memory bank switching. Refer to Table 1 for function A memory accesses. I / O pin A: Chip select eighth output 2 goes low during memory accesses I / O pin B: Opcode fetch goes low during the opcode fetch memory cycle. I / O pin A: Chip select half output 3 goes low during memory accesses. I / O pin B: Reserved I / O pin A: Chip select half output 2 goes low during memory accesses. I / O pin B: Reserved D0 D1 D2 D3 D4 D5 CSE2 OCF -- -- 59 56 -- 64 60 59 58 57 56 CSH3 CSH2 SYSCLK R/W SYSCLK R/W -- 55 54 -- I / O pin A, B: Internal clock signal is 1 / 1 (PLL) or 1 / 4 XTAL2 / CLKIN frequency. I / O pin A, B: Read / write output pin I / O pin A: Chip select peripheral output for peripheral file goes low during memory accesses. I / O pin B: Reserved I/O CSPF D6 CSH1 EDS 53 55 I / O pin A: Chip select half output 1 goes low during memory accesses. I / O pin B: External data strobe output goes low during memory accesses from external memory and has the same timings as the five chip selects. I / O pin A: Chip select eighth output goes low during memory accesses. I / O pin B: Wait input pin extends bus signals. D7 CSE1 WAIT 52 28 27 26 44 43 41 54 30 29 28 46 45 44 SCITXD SCIRXD SCICLK SCIIO1 SCIIO2 SCIIO3 T1IO1 T1IO2 T1IO3 I/O SCI transmit data output pin / general-purpose bidirectional pin (see Note 1) SCI receive data input pin / general-purpose bidirectional pin SCI bidirectional serial clock pin / general-purpose bidirectional pin Timer1 input capture / counter reset input pin / general-purpose bidirectional pin Timer1 pulse-width-modulation (PWM) output pin / general-purpose bidirectional pin Timer1 external event input pin / general-purpose bidirectional pin T1IC / CR T1PWM T1EVT I/O T2AIC1 / CR T2AIC2 / PWM T2AEVT T2AIO1 T2AIO2 T2AIO3 25 24 23 27 26 25 I/O Timer2A input capture 1 / counter reset input pin / general-purpose bidirectional pin Timer2A input capture 2 / PWM output pin / general-purpose bidirectional pin Timer2A external event input pin / general-purpose bidirectional pin SPISOMI SPIIO1 47 49 SPI slave output pin, master input pin / general-purpose bidirectional pin SPISIMO SPIIO2 46 48 I / O SPI slave input pin, master output pin / general-purpose bidirectional pin SPICLK SPIIO3 45 47 SPI bidirectional serial clock pin / general-purpose bidirectional pin I = input, O = output Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK. NOTE 1: The three-pin configuration SCI is referred to as SCI1.
Pin Descriptions (Continued)
Table 1. Function A: Memory Accesses Locations for `x5x Devices
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FUNCTION A `X50, `X52, `X53, AND `X56 `X58 `X59 CSEx 2000h - 3FFFh (8K bytes) 10C0h - 10FFh (64 bytes) A000h - BFFFh (8K bytes) 10C0h - 10FFh (64 bytes) E000h - EFFFh (4K bytes) F000h - FFFFh (4K bytes) 10C0h - 10FFh (64 bytes) CSHx 8000h - FFFFh (32K bytes) C000h - FFFFh (16K bytes) CSPF
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
functional block diagram
E0 - E7 or AN0 - AN7
INT1
INT2
INT3 XTAL1 XTAL2/ CLKIN
MC
RESET
Interrupts
Clock Options: System Control Divide-by-4 or Divide-by-1(PLL)
Analog-to-Digital Converter 1
VCC3 VSS3
CPU Program Memory ROM: 4K, 8K, 12K, 16K, 32K, or 48K Bytes EPROM: 16K, 32K, or 48K Bytes
RAM 256, 512, 1K, 1.5K, or 3.5K Bytes Data EEPROM 0, 256, or 512 Bytes
Serial Peripheral Interface Serial Communications Interface 1 Timer 2A
SPISOMI SPISIMO SPICLK SCIRXD SCITXD SCICLK T2AIC1 / CR T2AEVT T2AIC2 / PWM T1IC / CR T1EVT T1PWM
Timer 1 Memory Expansion Address MSbyte Address LSbyte Watchdog Control Port D 8/6 VSS2 For the 64-pin devices, there are only six pins for port D. VCC2
Port A 8
Data
Port B 8
Port C 8
VCC1 VSS1
description
The TMS370Cx5x family of single-chip 8-bit microcontrollers provides cost-effective real-time system control through integration of advanced peripheral function modules and various on-chip memory configurations. The TMS370Cx5x family presently consists of twenty-one devices which are grouped into seven main sub-families: the TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and SE370C75x. The TMS370Cx5x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of CMOS technology, coupled with the high performance and extensive on-chip peripheral functions, make the TMS370Cx5x devices attractive in system designs for automotive electronics, industrial motor control, computer peripheral control, telecommunications, and consumer application. Table 2 provides a memory configuration overview of the TMS370Cx5x devices.
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AAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A A A A A A AAA AA A AA AAA AA A AA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A A A A A A A AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAA A A A A A A A AAAAAAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAA A A A A A A A AAAAAAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA
SE370C756A SE370C758A, SE370C758B TMS370C059A TMS370C759A TMS370C758A, TMS370C758B TMS370C358A TMS370C058A TMS370C756A TMS370C356A TMS370C456A TMS370C256A TMS370C156A TMS370C056A TMS370C353A TMS370C352A TMS370C452A TMS370C052A TMS370C350A TMS370C250A TMS370C150A TMS370C050A DEVICE TMS370Cx56: TMS370C056, TMS370C156, TMS370C256, TMS370C356, TMS370C456, AND TMS370C756 TMS370Cx50: TMS370C050, TMS370C150, TMS370C250, AND TMS370C350 ROM 48K 32K 32K 16K 16K 16K 12K 8K 8K 8K 4K 4K -- -- -- -- -- -- -- -- -- PROGRAM MEMORY (BYTES) TMS370Cx58: TMS370C058, TMS370C358, AND TMS370C758 TMS370Cx52: TMS370C052, TMS370C352, AND TMS370C452 EPROM DEVICE: SE370C756, SE370C758, and SE370C759 EPROM 32K 16K 48K 32K 16K -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TMS370Cx59: TMS370C059 AND TMS370C759
SE370C759A -- 48K 20K 3.5K 256 FZ - CLCC C - Microcomputer mode P - Microprocessor mode TMS370C45x support ROM memory security. Refer to the program ROM section. Only operate up to 3 MHz SYSCLK System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.
description (continued)
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Table 2. Memory Configurations
OFF-CHIP MEMORY EXP. EXP (BYTES)
TMS370Cx53: TMS370C353
112K
112K
112K
112K
112K
112K
112K
112K
112K
112K
112K
64K
20K
20K
64K
64K
64K
56K
56K
56K
56K
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RAM 3.5K 3.5K 1.5K DATA MEMORY (BYTES) 512 512 512 512 512 512 512 256 256 256 256 256 256 256 1K 1K 1K 1K EEPROM 256 512 256 256 256 256 512 512 512 512 256 256 256 256 -- -- -- -- -- -- -- OPERATING MODES C -- -- -- -- P FN - PLCC / NM -PSDIP FN - PLCC / NM -PSDIP FN - PLCC / NM -PSDIP FN - PLCC / NM -PSDIP FN - PLCC / NM -PSDIP FN - PLCC / NM -PSDIP FN - PLCC / NM -PSDIP FN - PLCC / NM -PSDIP FN - PLCC / NM -PSDIP FN - PLCC / NM -PSDIP PACKAGES 68 PIN PLCC/CLCC, OR 64 PIN PSDIP/CSDIP FZ - CLCC / JN -CSDIP FZ - CLCC / JN -CSDIP FN - PLCC FN - PLCC FN - PLCC FN - PLCC FN - PLCC FN - PLCC FN - PLCC FN - PLCC FN - PLCC
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
description (continued)
The suffix letter (A or B) appended to the device names shown in the device column of Table 2 indicates the configuration of the device. ROM or an EPROM devices have different configurations as indicated in Table 3. ROM devices with the suffix letter A are configured through a programmable contact during manufacture. Table 3. Suffix Letter Configuration
DEVICE EPROM A EPROM B ROM A ROM-less A WATCHDOG TIMER Standard Hard Standard Hard Simple Standard Divide-by-4 Enabled Refer to the "device numbering conventions" section for device nomenclature and the "device part numbers" section for ordering. Divide-by-4 or Divide-by-1 (PLL) Enabled or disabled CLOCK Divide-by-4 (Standard oscillator) Divide-by-1 (PLL) LOW-POWER MODE Enabled Enabled
Unless otherwise noted, the terms TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and SE370C75x refer to the individual devices listed in Table 2 and described in this data sheet. All TMS370Cx5x devices contain the following on-chip peripheral modules:
D D D D D
Eight-channel, 8-bit analog-to-digital converter 1 (ADC1) Serial communications interface 1 (SCI1) Serial peripheral interface (SPI) One 24-bit general-purpose watchdog timer Two 16-bit general-purpose timers (one with an 8-bit prescaler)
TMS370C756, TMS370C758, and TMS370C759 are one-time programmable (OTP) devices that are available in plastic packages. This microcomputer is effective to use for immediate production updates for other members of the TMS370Cx5x family or for low-volume production runs when the mask charge or cycle time for low-cost mask ROM devices is not practical. The SE370C756, SE370C758, and SE370C759 have windowed ceramic packages to allow reprogramming of the program EPROM memory during the development / prototyping phase of design. The SE370C75x devices allow quick updates to breadboards and prototype systems while iterating initial designs. The TMS370Cx5x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (that is, no instructions are executed). In the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes. The TMS370Cx5x features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx5x family is fully instruction-set-compatible, allowing easy transition between members of the TMS370 8-bit microcontroller family. The SPI and the two operational modes of the SCI1 give three methods of serial communications. The SCI1 allows standard RS-232-C communications interface between other common data transmission equipment, while the SPI gives high-speed communications between simpler shift-register type devices, such as display drivers, ADC1 converter, phase-locked loop (PLL), I/O expansion, or other microcontrollers in the system.
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
description (continued)
For large memory applications, the TMS370Cx5x family provides an external bus with non-multiplexed address and data. Precoded memory chip-select outputs can be enabled, which allows minimum-chip-count system implementations. Wait-state support facilitates performance matching among the CPU, external memory, and the peripherals. All pins associated with memory expansion interface are individually software configurable for general purpose digital input/output (I / O) pins when operating in the microcomputer mode. The TMS370Cx5x family provides the system designer with very economical, efficient solution to real-time control applications. The TMS370 family extended development system (XDSTM) and compact development tool (CDTTM) solve the challenge of efficiently developing the software and hardware required to design the TMS370Cx5x into an ever-increasing number of complex applications. The application source code can be written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family XDS development tools communicate through a standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family XDS emphasizes ease-of-use through extensive use of menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reduced time-to-market cycle. The TMS370Cx5x family together with the TMS370 family XDS/22, CDT370, design kit, starter kit, software tools, the SE370C75x reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer.
modes
The TMS370Cx5x has four operating modes, two basic modes with each mode having two memory configurations. The basic operating modes are the microcomputer and microprocessor modes, which are selected by the voltage level applied to the dedicated MC pin two cycles before RESET goes inactive. The two memory configurations then are selected through software programming of the internal system configuration registers. The four operating modes are the microcomputer single chip, microcomputer with external expansion, microprocessor without internal program memory, and microprocessor with internal program memory. These modes are described in the following list.
D D
Microcomputer single chip mode: - - - - Operates as a self-contained microcomputer with all memory and peripherals on-chip. Maximizes the general-purpose I/O capability for real-time control applications. Supports bus expansion to external memory or peripherals, while all on-chip memory (RAM, ROM, EPROM, and data EEPROM) remains active. Configures digital I/O ports (ports A, B, C, and D) through software, under control of the associated port control, to become external memory as follows: - - - - - Port A: 8-bit data memory Port B and C: 16-bit address memory Port D: 8-bit control memory (pin not used as function A or B can be configured as I/O)
Microcomputer with external expansion mode:
Utilizes the pins available (not used for address, data, or control memory) as general-purpose input/output by programming them individually. Lowers the system cost by not requiring an external address/data latch (address memory and data memory are nonmultiplexed).
XDS and CDT are trademarks of Texas Instruments Incorporated.
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7
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
modes (continued)
- - - Reduces external interface decode logic by using the precoded chip select outputs that provide direct memory/peripheral chip select or chip enable functions. Function A maps up to 112K bytes of external memory into the address space by using CSE1, CSE2, CSH1, CSH2, and CSH3 as memory-bank selects under software control. Function B maps up to 40K bytes of external memory into the address space by using EDS under software control.
D
Microprocessor without internal program memory mode: - - - Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses for interface to external memory and peripherals. On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled. Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations.
D
Microprocessor with internal program memory mode: - - Configured as the microprocessor without internal program memory mode with respect to the external bus interface. Application program in external memory enables the internal program ROM or EPROM to be active in the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control register accomplishes this.)
memory/peripheral wait operation
The TMS370Cx5x enhances interface flexibility by providing WAIT-state support, decoupling the cycle time of the CPU from the read/write access of the external memory or peripherals. External devices can extend the read/write accesses indefinitely by placing an active low on the WAIT-input pin. The CPU continues to wait as long as WAIT remains active. Programmable automatic wait-state generation also is provided by the TMS370Cx5x on-chip bus controller. Following a hardware reset, the TMS370Cx5x is configured to add one wait state to all external bus transactions and memory and peripheral accesses automatically, thus making every external access a minimum of three system-clock cycles. The designer can disable the automatic wait-state generation if the AUTOWAIT DISABLE bit in SCCR1 is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended independently to four system clock cycles if the PF AUTO WAIT bit in SCCR0 is set to one. Programmable wait states can be used in conjunction with the external WAIT pin. In applications where the external device read/write access can interface with the TMS370Cx5x CPU using one wait state, the automatic wait-state generation can eliminate external WAIT interface logic, lowering system cost.
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
CPU
The CPU used on TMS370Cx5x devices is the high-performance 8-bit TMS370 CPU module. The 'x5x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete 'x5x instruction set is summarized in Table 23. Figure 1 illustrates the CPU registers and memory blocks.
15 Program Counter Legend: C=Carry N=Negative Z=Zero V=Overflow IE2=Level2 interrupts Enable IE1=Level1 interrupts Enable 256-Byte RAM (0000h - 00FFh) 512-Byte RAM (0000h - 01FFh) 1K-Byte RAM (0000h - 03FFh) 1.5K-Byte RAM (0000h - 05FFh) 3.5K-Byte RAM (0000h - 0DFFh) Reserved Peripheral File Peripheral Exp RAM (Includes 256-Byte Registers File) 0000h 0001h 0002h 0003h R0(A) R1(B) R2 R3 16K-Byte ROM / EPROM (4000h - 7FFFh) 12K-Byte ROM (5000h - 7FFFh) 8K-Byte ROM (6000h - 7FFFh) 007Fh R127 4K-Byte ROM (7000h - 7FFFh) Interrupts and Reset Vectors; Trap Vectors 32K-Byte ROM / EPROM (2000h - 9FFFh) 48K-Byte ROM / EPROM (2000h - DFFFh) R255 00FFh Reserved means the address space is reserved for future expansion. Memory Expansion Reserved 512-Byte (1E00h - 1FFFh) Data EEPROM 256-Byte (1F00h - 1FFFh) 2000h 4000h 5000h 6000h 7000h 7FC0h 8000h A000h E000h FFFFh 0000h 0100h 0200h 0400h 0600h 0E00h 1000h 10C0h 1100h 1E00h 1F00h 0
7
Stack Pointer (SP)
0
Status Register (ST) C 7 N 6 Z 5 V 4 IE2 IE1 3 2 1 0
Figure 1. Programmer's Model
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
CPU (continued)
The 'x5x CPU architecture provides the following components:
D
CPU registers: - - - A stack pointer that points to the last entry in the memory stack A status register that monitors the operation of the instructions and contains the global-interrupt-enable bits A program counter (PC) that points to the memory location of the next instruction to be executed
D
A memory map that includes : - - - - 256-, 512-, 1K-, 1.5K-, or 3.5K-byte general-purpose RAM that can be used for data-memory storage, program instructions, general-purpose register, or the stack (can be located only in the first 256 bytes) A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and EEPROM/EPROM programming control 256- or 512-byte EEPROM module that provides in-circuit programmability and data retention in power-off conditions 4K-, 8K-, 12K-, 16K-, 32K-, or 48K-byte ROM or 16K-, 32K-, or 48K-byte EPROM program memory
stack pointer (SP) The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory. Typically the stack is used to store the return address on subroutine calls as well as the status-register contents during interrupt sequences. The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed onto the stack and decrements after data is popped from the stack. The stack can be located only in the first 256 bytes of the on-chip RAM memory. status register (ST) The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits:
D D
The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use these status bits to determine program flow. The two interrupt-enable bits control the two interrupt levels.
The ST register, status bit notation, and status bit definitions are shown in Table 4. Table 4. Status Registers
AAAAA A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA AAAAA A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA
7 6 5 4 3 2 1 0 C N Z V IE2 IE1 Reserved Reserved RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R = read, W = write, 0 = value after reset 10
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SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
CPU (continued)
program counter (PC) The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address. The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).
Program Counter (PC) Memory 0000h PCH 60 PCL 00
7FFEh 7FFFh
60 00
Figure 2. Program Counter After Reset memory map The TMS370Cx5x architecture is based on the Von Neuman architecture, where the program memory and data memory share a common address space. All peripheral input/output is memory mapped in this same common address space. In the expansion mode, external memory peripherals are also memory-mapped into this common address. As shown in Figure 3, the TMS370Cx5x provides a 16 bit-address range to access internal or external RAM, ROM, data EEPROM, EPROM input/output pins, peripheral functions, and system-interrupt vectors. The peripheral file contains all input/output port control, on- and off-chip peripheral status and control, EPROM, EEPROM programming, and system-wide control functions. The peripheral file consists of 256 contiguous addresses located from 1000h to 10FFh. The 256 contiguous addresses are divided logically into 16 peripheral file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed. The TMS370Cx5x has its on-chip peripherals and system control assigned to peripheral file frames 1 through 7, addresses 1010h through 107Fh.
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
memory map (continued)
'X59 'X56 'X52 'X50 'X58 'X53 'X59 'X56 'X52 'X50 'X58 'X53 'X59 'X56 'X52 'X50 'X58 'X53 'X59 'X56 'X52 'X50 'X58 'X53
0100h 0200h 0400h
0600h
0E00h 1000h
10C0h
1100h
1E00h
1F00h
2000h 4000h
5000h 6000h 7000h
8000h
A000h
E000h
FFFFh
On-Chip For TMS370Cx59 Devices On-Chip For TMS370Cx58 Devices
On-Chip For TMS370Cx56 Devices On-Chip For TMS370Cx53 Devices
Reserved = the address space is reserved for future expansion. Not available (N /A) = address space unavailable in the mode illustrated. Precoded chip select outputs available on external expansion bus. Microprocessor mode is designed for ROM-less devices ('x50 and 'x56). ROM and EPROM devices can also be used in this mode but all on-chip memory is ignored.
Figure 3. TMS370Cx5x Memory Map
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OO SS
SUUUOUUUOUUUOSUUU OSUU OUUUOUUUOUUU U SU S U S SUUU OUUUS UU S U OSUU SUU U U UOUUUOUUUOSUUU UOUUUOUUU UUU UUUUUUUU U U UUU UUUUUUUU U U UUU UUUUUUUU UUU UU UU U U UUU UUUUUUUU UUU UU UU UU UU UUU U SUUUOUUUOUUUOSUUU OSUU OUUUSUUUOSUU U SU O U U SUUUOUUUOUUUOSUUU OSUU OUUUSUUUOSUU U SU O U U
Reserved Reserved Reserved Reserved Not Available (N / A) External External External Reserved Reserved Reserved Reserved
0000h
0000h 0100h 0200h 0400h 0600h
Peripheral File Control Registers 256-Byte RAM (0000h-00FFh) (Register File/Stack) 512-Byte RAM (0000h-01FFh) 1K-Byte RAM (0000h-03FFh) 1.5K-Byte RAM (0000h-05FFh) 3.5K-Byte RAM (0000h-0DFFh) Reserved Peripheral File Reserved System Control Digital Port Control SPI Peripheral Control Timer 1 Peripheral Control SCI1 Peripheral Control 1000h-100Fh 1010h-101Fh 1020h-102Fh 1030h-103Fh 1040h-104Fh 1050h-105Fh
0E00h 1000h
Timer 2A Peripheral 1060h-106Fh Control ADC1 Peripheral Control 1070h-107Fh
10C0h 1100h
Peripheral Expansion
Reserved 1E00h
Reserved
1080h-108Fh
UU UU U UU UU U UU UU U UUU UU UU UU U SU O U U OUUUUUUUU UUU OUU SUU SUU U SU SUUOSUUOOUUU OUUUOUUUOSUUU OU UO UU S U SU S U OS OUUUOUUUOSUUU OUUUOUUU UUU SUU SUU OSU OUUUUUUUUSUUU OU SU OO UOO OUUUU UUU UUU OUU U UUU U UUU S UUUOSUUOSUUU SUUUO UUO UU UU UUU SUU UU UUUUSUUUSUUU U U UUU U U UUUU UU UU UU U UUUUUUU UUU U UU UU UU SUU U SSUUOOUUOOUUOSUUU O UU SUUUSUUUOUUU SSUUOOUUOOUUUOUUU O UU SUUUS U U UOSSUU SSUU SU UU UU OU UUOOUUOOUUOSUUU UUUS UUOSUU U U UU UU
External External N / A N / A N / A External Not Available External External Microcomputer Single Chip Mode Microcomputer Mode With External Expansion Microprocessor With Internal Program Memory Microprocessor Mode
512K-Byte Data EEPROM (1E00h-1FFFh) 256-Byte Data EEPROM (1F00h-1FFFh)
1F00h Vectors
2000h Trap 15-0 4000h 5000h 6000h 7000h 7FC0h Interrupts and Reset Vectors; Trap Vectors 8000h 32K-Byte ROM (2000h-9FFFh) A000h 48K-Byte ROM (2000h-DFFFh) E000h Memory Expansion FFFFh Reset 7FFEh-7FFFh Serial Peripheral I/F 7FF6h-7FF7h Interrupt 3 Interrupt 2 Interrupt 1 7FF8h-7FF9h 7FFAh-7FFBh 7FFCh-7FFDh Serial Comm I/F RX 7FF2h-7FF3h Timer 1 7FF4h-7FF5h 16K-Byte ROM (4000h-7FFFh) 12K-Byte ROM (5000h-7FFFh) 8K-Byte ROM (6000h-7FFFh) 4K-Byte ROM (7000h-7FFFh) 7FC0h-7FDFh
Reserved ADC1 Timer 2A Serial Comm I/F TX
7FE0h-7FFBh 7FECh-7FEDh 7FEEh-7FEFh 7FF0h-7FF1h
UU UU
UU UU
On-Chip For TMS370Cx52 Devices On-Chip For TMS370Cx50 Devices
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
RAM/register file (RF)
Locations within RAM address space can serve as either register file or general-purpose read/write memory, program memory, or stack instructions. The TMS370Cx50 and TMS370Cx52 devices contain 256 bytes of internal RAM, mapped beginning at location 0000h and continuing through location 00FFh which is shown in Table 5 along with other 'x5x devices. Table 5. RAM Memory Map
AAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A
AAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A
`x50 and `x52 256 Bytes `x56 `x58 `x53 `x59 RAM Size 512 Bytes 1K Bytes 1.5K Bytes 3.5K Bytes Memory Mapped 0000h - 00FFh 0000h - 01FFh 0000h - 03FFh 0000h - 05FFh 0000h - 0DFFh
The first 256 bytes of RAM (0000h - 00FFh) are register files, R0 through R255 (see Figure 1). The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.
peripheral file (PF) The TMS370Cx5x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or by P for a decimal designator. For example, the system control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 6 shows the TMS370Cx5x peripheral files. Table 6. TMS370Cx5x Peripheral File Address map
DESCRIPTION
ADDRESS RANGE 1000h - 100Fh 1010h - 101Fh 1020h - 102Fh 1030h - 103Fh 1040h - 104Fh 1050h - 105Fh 1060h - 106Fh 1070h - 107Fh
PERIPHERAL FILE DESIGNATOR P000 - P00F P010 - P01F P020 - P02F P030 - P03F P040 - P04F P050 - P05F P060 - P06F P070 - P07F
Reserved for factory test
System and EEPROM/EPROM control registers Digital I/O port control registers Timer 1 registers Serial peripheral interface registers
Serial communication interface 1 registers Timer 2A registers Reserved Analog-to-digital converter 1 registers External peripheral control
1080h - 10BFh
P080 - P0BF
10C0h - 10FFh
P0C0 - P0FF
data EEPROM
The TMS370Cx56 devices contain 512 bytes of data EEPROM, which are memory mapped beginning at location 1E00h and continuing through location 1FFFh as shown in Table 7 along with other `x5x devices. Table 7. Data-EEPROM Memory Map
`x50, `x52, `x58, and `x59 256 Bytes 1F00h - 1FFFh `x56 `X53
Data-EEPROM Size Memory Mapped
512 Bytes
None None
1E00h - 1FFFh
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
data EEPROM (continued) Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the TMS370 Family User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). The data EEPROM features include the following:
D
Programming: - - - - Bit, byte, and block write/erase modes Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. Control register: Data EEPROM programming is controlled by the data EEPROM control register (DEECTL) located in the PF frame beginning at location P01A. In-circuit programming capability: There is no need to remove the device to program it.
D
Write-protection: Writes to the data EEPROM are disabled during the following conditions: - - - Reset: All programming of the data EEPROM module is halted. Write protection active: There is one write-protect bit per 32-byte EEPROM block. Low-power mode operation
D
Write protection can be overridden by applying 12 V to MC.
Table 8 shows the memory map of the control registers.
AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA
ADDRESS P014 P017 P018 P019 SYMBOL EPCTLH INT1 INT2 INT3 NAME Program EPROM control register - high array Reserved External interrupt 1 control register External interrupt 2 control register External interrupt 3 control register Data EEPROM control register Reserved Reserved P015 - P016 P01A P01B DEECTL P01C P01D P01E EPCTLM EPCTLL Program EPROM control register - middle array Program EPROM control register - low array
Table 8. Data EEPROM and Program EPROM Control Registers Memory Map
For the 16K-byte EPROM device, program memory is controlled by P01C; for the 32K-byte EPROM device, the program memory is controlled by P01C and P01E; for the 48K-byte EPROM device, the program memory is controlled by P014, P01C, and P01E.
program EPROM The `370C756 consists of a 16K-byte array of EPROM at address locations 4000h through 7FFFh. The `370C758 consists of 32K bytes made up of two 16K-byte arrays of EPROM; the first 16K-bytes array is located at address locations 2000h through 5FFFh, and the second 16K byte array is located at address locations 6000h through 9FFFh. The '370C759 consists of 48K bytes that is made up of three 16K byte arrays of EPROM; the first 16K bytes array is located at address locations 2000h through 5FFFh, the second 16K-byte array is located at address locations 6000h through 9FFFh, the third 16K-byte array is located at address locations A000h through DFFFh (see Figure 3).
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SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
program EPROM (continued)
The EPROM memory map in Table 9 expresses the following:
D D D
The programming control register for program EPROM (EPCTLM) for 16K-byte EPROM is located at address 101Ch (P01C). For the 32K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C). For the 48K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C); the third 16K-byte array is controlled by EPCTLH, located at 1014h (P014). Table 9. EPROM Memory Map
AAAAAAAAAA A A A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A AAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A A
'756 '758 '759 EPROM size 16K Bytes 32K Bytes 48K Bytes Memory Mapped Contol Registers 16K 4000h - 7FFFh EPCTLM P01C First 16K 2000h - 5FFFh EPCTLL P01E Second 16K 6000h - 9FFFh EPCTLM P01C First 16K 2000h - 5FFFh EPCTLL P01E Second 16K 6000h - 9FFFh EPCTLM P01C Third 16K A000h - DFFFh EPCTLH P014
Reading the program-EPROM modules is identical to reading other internal memory. During programming, the EPROM is controlled by the EPCTL. The program EPROM modules' features include:
D
Programming - - - In-circuit programming capability if VPP is applied to MC Control register: Program EPROM programming is controlled by the program EPROM control registers (EPCTLL, EPCTLM, and EPCTLH) located in the PF frame as shown in Table 8. Programming one EPROM module while executing the other
D
Write protection: Writes to the program EPROM are disabled under the following conditions: - - - Reset: All programming to the EPROM module is halted. Low-power modes 13 V not applied to MC
program ROM The program ROM consists of 4K to 48K bytes of mask-programmable ROM. The program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication. ROM security is a feature of the `45x devices, which inhibits reading of the data using the programmer. Table 10. ROM Memory Map
AAAAA A AA A AA AAAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA
`x50 `x52 `x53 `x56 `x58 `x59 ROM Size 4K Bytes 8K Bytes 12K Bytes 16K Bytes 32K Bytes 48K Bytes Memory Mapped 7000h - 7FFFh 6000h - 7FFFh 5000h - 7FFFh 4000h - 7FFFh 3000h - 9FFFh 2000h - DFFFh Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TITM), and addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh. TI is a trademark of Texas Instruments Incorporated.
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
system reset The system-reset operation ensures an orderly start-up sequence for the TMS370Cx5x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are internally generated, while one (RESET) is controlled externally. These actions are as follows:
D D D
Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370 User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B) for more information. Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See the TMS370 User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B) for more information. External RESET Pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the TMS370 User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B) for more information.
Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the 'x5x device to reset external system components. Additionally, if a cold-start condition (VCC is off for several hundred milliseconds) occurs, oscillator failure occurs, or RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active. After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag (COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 11 lists the reset sources. Table 11. Reset Sources
AAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAA AAAAAAAAA A A AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAA
REGISTER SCCR0 SCCR0 ADDRESS 1010h 1010h PF BIT NO. 7 4 5 CONTROL BIT COLD START SOURCE OF RESET Cold (power-up) P010 P010 OSC FLT FLAG Oscillator out of range T1CTL2 104Ah P04A WD OVRFL INT FLAG Watchdog timer timeout
Once a reset is activated, the following sequence of events occurs: 1. The CPU registers initialize: ST = 00h, SP = 01h (reset state).
2. Registers A and B initialize to 00h (no other RAM is changed). 3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL. 4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH. 5. Program execution begins with an opcode fetch from the address pointed to by the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state. During RESET, the two basic operating modes which are the microcomputer and microprocessor modes can be selected by applying the desired voltage level to the dedicated MC pin two cycles before RESET goes inactive (refer to page 7 for operating modes description).
16
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interrupts
The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of the status register. Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is configured selectively on either the high- or low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions. The TMS370Cx5x has nine hardware system interrupts (plus RESET) as shown in Table 12. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXINT has two interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the associated PF. Each interrupt source FLAG bit is individually readable for software polling or determining which interrupt source generated the associated system interrupt. Interrupt control block diagram is illustrated in Figure 4.
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
interrupts (continued)
EXT INT 3
INT 3 EXT INT 2
TIMER 2A Overflow Compare1 Ext Edge Compare2 Input Capture 1 Input Capture 2
TIMER 1 INT3 PRI Overflow Compare1
INT 2
INT2 PRI Ext Edge EXT INT1 Compare2 INT1 Input Capture 1 Watchdog NMI CPU
T2A PRI
T1 PRI
INT1 PRI STATUS REG IE1
Priority Logic
Level 1 INT IE2 Level 2 INT AD INT AD PRI TX SCI INT RX SPI INT SPI PRI Enable
TXPRI TXRDY A/D
RXPRI BRKDT RXRDY SPI
Figure 4. Interrupt Control On-chip peripheral functions generate six of the system interrupts. Three external interrupts also are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in PF frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as nonmaskable, it cannot be masked by the individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts INT2 and INT3 can be software configured as general purpose input/output pins if the interrupt function is not required (INT1 can be similarly configured as an input pin). Table 12 shows the interrupt vector sources, corresponding addresses, and hardware priorities.
18
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TMS370Cx5x 8-BIT MICROCONTROLLER
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interrupts (continued)
AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT RESET INT1 INT2 INT3 VECTOR ADDRESS PRIORITY External RESET Watchdog overflow Oscillator fault detect External INT1 External INT2 External INT3 COLD START WD OVRFL INT FLAG OSC FLT FLAG INT1 FLAG INT2 FLAG INT3 FLAG 7FFEh, 7FFFh 1 2 3 4 5 7FFCh, 7FFDh 7FFAh, 7FFBh 7FF8h, 7FF9h 7FF6h, 7FF7h SPI RX/TX complete SPI INT FLAG SPIINT Timer 1 overflow Timer 1 compare 1 Timer 1 compare 2 Timer 1 external edge Timer 1 input capture 1 Watchdog overflow T1 OVRFL INT FLAG T1C1 INT FLAG T1C2 INT FLAG T1EDGE INT FLAG T1IC1 INT FLAG WD OVRFL INT FLAG RXRDY FLAG BRKDT FLAG TXRDY FLAG T1INT 7FF4h, 7FF5h 6 SCI RX data register full SCI RX break detect RXINT TXINT 7FF2h,7FF3h 7 8 SCI TX data register empty Timer 2A overflow Timer 2A compare 1 Timer 2A compare 2 Timer 2A external edge Timer 2A input capture 1 Timer 2A input capture 2 7FF0h, 7FF1h T2A OVRFL INT FLAG T2AC1 INT FLAG T2AC2 INT FLAG T2AEDGE INT FLAG T2AIC1 INT FLAG T2AIC2 INT FLAG T2AINT 7FEEh, 7FEFh 9 A/D conversion complete AD INT FLAG Relative priority within an interrupt level Releases microcontroller from STANDBY and HALT low-power modes. Releases microcontroller from STANDBY low-power mode. ADINT 7FECh, 7FEDh 10
Table 12. Hardware System Interrupts
privileged operation and EEPROM write-protection override The TMS370Cx5x family has significant flexibility to enable the designer to software-configure the system and peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the TMS370Cx5x operates in the privileged mode, where all peripheral file registers have unrestricted read/write access, and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set to 1 to enter the nonprivileged mode; disabling write operations to specific configuration control bits within the peripheral file. Table 13 displays the system configuration bits that are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode.
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
privileged operation and EEPROM write-protection override (continued)
The write-protect override (WPO) mode provides an external hardware method for overriding the write-protection registers of data EEPROM on the TMS370Cx5x. The WPO mode is entered by applying a 12-V input to MC after RESET input goes high (logic 1). The high voltage on MC during the WPO mode is not the programming voltage for the data EEPROM or Program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware system-level capability to modify the content of the data EEPROM while the device remains in the application, but only while requiring a 12-V external input on the MC pin (normally not available in the end application except in a service or diagnostic environment). low-power and IDLE modes The TMS370Cx5x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the time when the mask is manufactured. The STANDBY and HALT low power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT / STANDBY bit in SCCR2 controls which low-power mode is entered. In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped; however, the oscillator, internal clocks, timer 1, and the receive start-bit detection circuit of the serial communications interface remain active. System processing is suspended until a qualified interrupt (hardware RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the serial communications interface 1) is detected.
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AAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAA A AAAA AA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAA AA AAAAAAAAAAAAAAAAAA AA AAAAAAAAAAA AA AAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAA AAAAAAAA
REGISTER NAME LOCATION P010.5 P010.6 P011.2 P011.4 CONTROL BIT SCCRO SCCR1 PF AUTOWAIT OSC POWER MEMORY DISABLE AUTOWAIT DISABLE SCCR2 P012.0 P012.1 P012.3 P012.4 P012.6 P012.7 P03F.5 P03F.6 P03F.7 P05F.4 P05F.5 P05F.6 P05F.7 P04F.6 P04F.7 P06F.6 P06F.7 P07F.5 P07F.6 P07F.7 PRIVILEGE DISABLE INT1 NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY SPI ESPEN SPI PRIORITY SPI STEST SPIPRI SCIPRI SCI ESPEN SCIRX PRIORITY SCITX PRIORITY SCI STEST T1 PRIORITY T1 STEST T1PRI T2APRI T2A PRIORITY T2A STEST AD ESPEN AD PRIORITY AD STEST ADPRI The privileged bits are shown in a bold typeface in Table 15.
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Table 13. Privileged Bits
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
low-power and IDLE modes (continued) In the HALT mode (HALT/STANDBY = 1), the TMS370Cx5x is placed in its lowest power consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, INT3, or low level on the receive pin of the serial communications interface 1) is detected. The low-power mode selection bits are summarized in Table 14.
When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the SCCR2.6-7 bits is ignored. In addition, if an idle instruction is executed when low-power modes are disabled through a programmable contact, the device always enters the IDLE mode. To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This means that the NMI is generated always, regardless of the interrupt enable flags. The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file), CPU registers (stack pointer, program counter, and status register), I/O pin direction and output data, and status registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking of the watchdog timer is inhibited. clock modules The `x5x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. The `x5x ROM-masked devices offer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. The `75xA EPROM has only the standard divide-by-4, while the `75xB EPROM has the divide-by-1. The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost. The divide-by-1 provides a 1-to-1 match of the external resonator frequency to the internal system clock (SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four. The clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows Divide-by-4 option : SYSCLK Divide-by-1 option : SYSCLK
The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper decay of emissions produced by the oscillator.
A A A AAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAA AAAAAAAA A A AAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAA AAAAAAAAAA
POWER-DOWN CONTROL BITS PWRDWN/IDLE (SCCR2.6) 1 1 0 HALT/STANDBY (SCCR2.7) 0 1 MODE SELECTED STANDBY HALT IDLE X X = don't care
Table 14. Low-Power/Idle Control Bits
+ external resonator frequency + CLKIN 4 4 + external resonator frequency 4
4
+ CLKIN
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AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A AAA A AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAA A A A A A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A AAA AA A A A A A A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AA A A AAAA A A A A A A A A A A AA AAA AA A A AA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A A A AAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA AAAA A AAAAA A AAAAA A AAA AAA A A A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAA AAAAA AAA AAAA A A AAA A AAAAAAAAAAA AAAA AAAAAAAAAAAAAA AAA A A A A A A AA A A A AAAA A AAAAA A AAAAA AAAAAAA A AA AAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAA AAAAAAAAAAAAAA AAA A A A A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAA AA A AAAAAAAAAAAAAAAAAA A AAAAAAA AA AAA AA
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
22
system configuration registers
P01D
P01C
P01E
P01B
P01A
P01F
P019
P018
P017
P015 to P016
P014
P013
P012
P010
P011
PF
Table 15 contains system configuration and control functions and registers for controlling EEPROM programming. The privileged bits are shown in a bold typeface and shaded.
HALT/ STANDBY
COLD START
BUSY
BUSY
BUSY
BUSY
INT3 FLAG
INT2 FLAG
INT1 FLAG
BIT 7
--
PWRDWN/ IDLE
INT3 PIN DATA
INT2 PIN DATA
INT1 PIN DATA
OSC POWER
Table 15. Peripheral File Frame 1: System Configuration Registers
VPPS
VPPS
VPPS
BIT 6
--
--
PF AUTO WAIT
BIT 5
--
--
--
--
--
--
--
--
--
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AUTOWAIT DISABLE
INT3 DATA DIR
INT2 DATA DIR
OSC FLT FLAG
BUS STEST
BIT 4
--
--
--
--
--
Reserved
Reserved
Reserved
Reserved
Reserved
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INT3 DATA OUT INT2 DATA OUT MC PIN WPO CPU STEST BIT 3 -- -- -- -- -- -- INT3 POLARITY INT2 POLARITY INT1 POLARITY MEMORY DISABLE MC PIN DATA BIT 2 AP -- -- -- -- INT3 PRIORITY INT2 PRIORITY INT1 PRIORITY W1W0 BIT 1 INT1 NMI W0 W0 W0 -- -- PRIVILEGE DISABLE INT3 ENABLE INT2 ENABLE INT1 ENABLE P/C MODE BIT 0 EXE EXE EXE EXE -- EPCTLL INT3 INT2 INT1 SCCR2 SCCR1 SCCR0 REG EPCTLM DEECTL EPCTLH
AAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA A AAA AAA AA
digital port control registers
P02D P02C P02E P02B P02A P02F P029 P028 P027 P026 P025 P024 P023 P022 P021 P020 PF
Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 16 lists the specific addresses, registers, and control bits within this peripheral file frame.
To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
BIT 7
Table 16. Peripheral File Frame 2: Digital Port Control Registers
BIT 6
BIT 5
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Port D Control Register 1 Port D Control Register 2
Port C Control Register 2
Port B Control Register 2
Port A Control Register 2
BIT 4
Port D Direction
Port C Direction
Port B Direction
Port A Direction
Port D Data
Port C Data
Port B Data
Port A Data
Reserved
Reserved
Reserved
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BIT 3 BIT 2 BIT 1 BIT 0 DDIR DDATA DPORT2 DPORT1 CDIR CDATA CPORT2 CPORT1 BDIR BDATA BPORT2 BPORT1 ADIR ADATA APORT2 APORT1 REG
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
23
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
digital port control registers (continued) Table 17. Port Configuration Register Setup
INPUT PORT PIN XPORT1 = 0 XPORT2 = 0 XDATA = y XDIR = 0 Data In y Data In y Data In y OUTPUT XPORT1 = 0 XPORT2 = 0 XDATA = q XDIR = 1 Data Out q Data Out q Data Out q FUNCTION A XPORT1 = 0 XPORT2 = 1 XDATA = x XDIR = x Data Bus Low ADDR Hi ADDR CSE2 CSH3 CSH2 SYSCLK R/W CSPF CSH1 CSE1 FUNCTION B (P MODE) XPORT1 = 1 XPORT2 = 1 XDATA = x XDIR = x Reserved Reserved Reserved OCF -- -- SYSCLK R/W -- EDS WAIT
A B C
0-7 0-7 0-7 0 1 2 3 4 5 6 7
D
Data In y
Data Out q
XPORT1 = 1 XPORT2 =0 Not defined XDATA = x XDIR = x DPORT only
timer 1 module
The programmable timer 1 (T1) module of the TMS370Cx5x provides the designer with the enhanced timer resources required to perform realtime system control. The T1 module contains the general-purpose timer and the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock sources (real-time, external event, or pulse-accumulate) with multiple 16-bit registers (input capture and compare) for special timer function control. The T1 module includes three external device pins that can be used for multiple counter functions (operation mode dependent) or used as general-purpose I/O pins. T1 module is shown in Figure 5.
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
timer 1 module (continued)
T1IC/CR
Edge Select
16-Bit Capt/Comp Register
MUX
16-Bit Counter
16
PWM Toggle
T1PWM
T1EVT
8-Bit Prescaler
16-Bit Compare Register
Interrupt Logic
MUX
16-Bit WatchdogCounter (Aux. Timer)
Interrupt Logic
Figure 5. Timer 1 Block Diagram
D
Three T1 I/O pins: - - - T1IC/CR: T1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin
D D D D D D D
Two operation modes: - - Dual-compare mode: Provides PWM signal Capture/compare mode: Provides input capture pin
One 16-bit general-purpose resettable counter One 16-bit compare register with associated compare logic One 16-bit capture / compare register, which, depending on the mode of operation, operates as either a capture or compare register One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if watchdog feature is not needed. Prescaler/ clock sources that determine one of eight clock sources for general-purpose timer Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T1IC/CR)
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AAAAAAAAAAAAAAAAAAAAAAAA A A AAA AA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAA AAA AA A AAA AAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AAAA A A A A A A A A A AAA AAA AA A AAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAA AAA AA A AAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A A AAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AAAA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA
P04D P04C P04C P04E P04B P04B P04A P04F P049 P048 Bit 15 P047 Bit 7 P046 Bit 15 P045 Bit 7 P044 Bit 15 P043 Bit 7 P042 Bit 15 P041 Bit 7 P040 Bit 15 PF
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
26
timer 1 module (continued)
Table 18 shows the T1 module control register.
D
D
Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored.
Modes: Dual-Compare and Capture/Compare
Mode: Capture/Compare
Mode: Dual-Compare
Modes: Dual-Compare and Capture/Compare
WD OVRFL RST ENA
WD OVRFL TAP SEL
Sixteen T1 module control registers located in the PF frame, beginning at address P040
-
-
-
-
Interrupts that can be generated on the occurrence of:
T1 MODE = 1
T1 MODE = 0
T1 STEST
T1EDGE INT FLAG
T1EDGE INT FLAG
T1PWM DATA IN
BIT 7
--
An external edge detection
A counter overflow
A compare equal
A capture
WD OVRFL INT ENA
WD INPUT SELECT2
T1PWM DATA OUT
T1 PRIORITY
T1C2 INT FLAG
T1C1 OUT ENA
T1C1 OUT ENA
BIT 6
--
--
WD OVRFL INT FLAG
T1PWM FUNCTION
WD INPUT SELECT1
T1C1 INT FLAG
T1C1 INT FLAG
T1C2 OUT ENA
Table 18. T1 Module Register Memory Map
BIT 5
--
--
--
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Capture/Compare Register MSbyte
Capture/Compare Register LSbyte
Watchdog Counter MSbyte
Compare Register MSbyte
Watchdog Counter LSbyte
WD INPUT SELECT0
Compare Register LSbyte
T1 OVRFL INT ENA
T1PWM DATA DIR
T1C1 RST ENA
T1C1 RST ENA
Watchdog Reset Key
BIT 4
T1 Counter MSbyte
T1 Counter LSbyte
--
--
--
--
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T1 OVRFL INT FLAG T1CR OUT ENA T1IC/CR DATA IN T1EVT DATA IN BIT 3 -- -- -- -- -- T1EDGE POLARITY T1EDGE POLARITY T1EVT DATA OUT T1IC/CR DATA OUT T1 INPUT SELECT2 T1EDGE INT ENA T1EDGE INT ENA BIT 2 -- -- T1EVT FUNCTION T1IC/CR FUNCTION T1 INPUT SELECT1 T1CR RST ENA T1C2 INT ENA BIT 1 -- -- -- -- T1EVT DATA DIR T1IC/CR DATA DIR T1 INPUT SELECT0 T1EDGE DET ENA T1EDGE DET ENA T1C1 INT ENA T1C1 INT ENA T1 SW RESET BIT 0 -- Bit 0 WDRST Bit 0 Bit 8 WDCNTR Bit 0 Bit 8 T1CC Bit 0 Bit 8 T1C Bit 0 Bit 8 T1CNTR T1PRI REG T1PC2 T1PC1 T1CTL4 T1CTL3 T1CTL4 T1CTL3 T1CTL2 T1CTL1
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
timer 1 module (continued)
The T1 capture/compare mode block diagram is illustrated in Figure 6. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.
T1CC.15-0
16-Bit LSB Capt/Comp MSB Register T1C1 OUT ENA
T1CTL4.6
Toggle
Prescale Clock Source
T1PC2.7-4
T1PWM
T1CNTR.15-0
LSB 16-Bit MSB Counter 16 T1 PRIORITY Compare= Reset
T1CTL3.5 T1CTL3.0
T1 SW RESET
T1C.15-0
T1C1 RST ENA 16-Bit LSB Compare Register MSB
T1C1 INT ENA
T1CTL2.0
T1CTL4.4
T1 OVRFL INT FLAG T1CTL2.3
T1CTL2.4
T1 OVRFL INT ENA
T1PC2.3-0
T1EDGE DET ENA T1IC/CR Edge Select T1EDGE INT FLAG
T1CTL3.7 T1CTL4.0 T1CTL3.2 T1CTL4.2
T1EDGE POLARITY T1EDGE INT ENA
Figure 6. Capture/Compare Mode
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IIII
T1PRI.6
T1C1 INT FLAG
0 1
Level 1 Int Level 2 Int
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
timer 1 module (continued)
The T1 dual-compare mode block diagram is illustrated in Figure 7. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.
T1CC.15-0
16-Bit LSB Capt/Comp Register MSB T1C2 INT FLAG
Prescaler Clock Source
T1CTL3.6 T1CTL3.1 T1C2 INT ENA
Output Enable
T1CNTR.15-0
LSB MSB 16-Bit Counter Reset T1 SW RESET T1C1 RST ENA
Compare=
T1CTL4.5 T1PC2.7-4
T1C2 OUT ENA
16 Compare=
Toggle
T1C1 INT FLAG T1CTL3.5
T1CTL4.6
T1C1 OUT ENA
T1PWM
T1C.15-0
16-Bit LSB Compare Register MSB
T1CTL3.0
T1C1 INT ENA
T1CTL4.3
T1CR OUT ENA
T1CTL2.0
T1CTL4.4
T1 OVRFL INT FLAG
T1PC2.3-0
T1IC/CR
T1CTL4.1 T1CR RST ENA
Edge Select
T1CTL2.3 T1CTL2.4
T1 OVRFL INT ENA T1 PRIORITY
T1CTL4.0 T1EDGE DET ENA T1CTL4.2 T1EDGE POLARITY
T1EDGE INT FLAG
T1PRI.6
0 1
Level 1 Int Level 2 Int
T1CTL3.7 T1CTL3.2
T1EDGE INT ENA
Figure 7. Dual-Compare Mode
28
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
timer 1 module (continued)
The TMS370Cx5x device includes a 24-bit watchdog (WD) timer, contained in the T1 module, which can be software-programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not desired. The WD function is to monitor software and hardware operation and to implement a system reset when the WD counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect value). The WD can be configured as one of the three mask options: standard watchdog, hard watchdog, or simple counter.
D
Standard watchdog configuration (see Figure 8) - for 'C75xA EPROM and mask-ROM devices - Watchdog mode - - - - - Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct value is written. Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter overflows A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system reset
Non-watchdog mode - Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer
WDCNTR.15-0
16-Bit Watchdog Counter WD OVRFL INT FLAG
T1CTL2.6
Interrupt WD OVRFL INT ENA
T1CTL2.5
Reset
Clock Prescaler
T1CTL1.7
WD OVRFL TAP SEL Watchdog Reset Key
T1CTL2.7
System Reset WD OVRFL RST ENA
WDRST.7-0
Figure 8. Standard Watchdog
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29
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
timer 1 module (continued)
D
Hard watchdog configuration (see Figure 9) - for `C75xB EPROM and mask-ROM devices - - - - - - Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK. A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct value is written. Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter overflows Automatic activation of the WD timer upon power-up reset INT1 is enabled as nonmaskable interrupt during low-power modes A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system reset
WDCNTR.15-0
16-Bit Watchdog Counter WD OVRFL INT FLAG
T1CTL2.5
Reset
Clock Prescaler
T1CTL1.7
WD OVRFL TAP SEL Watchdog Reset Key System Reset
WDRST.7-0
Figure 9. Hard Watchdog
30
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
timer 1 module (continued)
D
Simple-counter configuration (see Figure 10) - for mask-ROM devices only - The simple counter can be configured as an event counter, pulse accumulator, or an interval timer
WDCNTR.15-0
16-Bit Watchdog Counter WD OVFL INT FLAG
T1CTL2.6
Interrupt WD OVRFL INT ENA
T1CTL2.5
Reset
Clock Prescaler
T1CTL1.7
WD OVRFL TAP SEL Watchdog Reset Key
WDRST.7-0
Figure 10. Simple Counter timer 2A module The 16-bit general-purpose timer 2A (T2A) module is composed of a 16-bit resettable counter, 16-bit compare register with associated compare logic, 16-bit capture register, and a 16-bit register that functions as a capture register in one mode and as a compare register in the other mode. The T2A module adds an additional timer that provides an event count, input capture, and compare functions. The T2A module includes three external device pins that can be dedicated as timer functions or used as general-purpose I/O pins. The T2A module is shown in Figure 11.
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31
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
timer 2A module (continued)
T2AIC1/CR
Edge Detect Edge Detect 16-Bit Capt/Comp Register
T2AIC2/PWM (Dual-Capture Mode)
16-Bit Capture Register
INT Logic
PWM Toggle
T2AIC2/PWM (Dual-Compare Mode)
16
T2AEVT
Clock Select
16-Bit Counter
16-Bit Compare Register
Figure 11. Timer 2A Block Diagram The T2A module features include the following:
D
Three T2A I/O pins: - - - T2AIC1/CR: T2A input-capture 1 / counter-reset input pin, or general-purpose bidirectional I/O pin T2AIC2/PWM: T2A input-capture 2 / pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin T2AEVT: Timer 2A event-input pin, or general-purpose bidirectional I/O pin
D D D D D D
Two operational modes: - - Dual-compare mode: Provides PWM signal Dual-capture mode: Provides input-capture pin
One 16-bit general-purpose resettable counter One 16-bit compare register with associated compare logic One 16-bit capture register with associated capture logic One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a capture or compare register T2A clock sources can be any of the following: - - - - System clock No clock (the counter is stopped) External clock synchronized to the system clock (event counter) System clock while external input is high (pulse accumulation)
32
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AAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A A A AAAA A A A AAAA A AAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A A A A A A A A AAAA A A AA A AAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A A A AAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AA A AAAA A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AA A AAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AA
P06D P06C P06C P06E P06B P06B P06A P06F P067 P066 P065 P064 P063 P062 P061 P060 PF
timer 2A module (continued)
The T2A module-control registers are illustrated in Table 19.
D
D
D
Modes: Dual-Compare and Dual-Capture
Mode: Dual-Capture
Mode: Dual-Compare
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Modes: Dual-Compare and Dual-Capture
T2AIC2 / PWM DATA IN
T2A STEST
T2AEDGE1 INT FLAG
T2AEDGE1 INT FLAG
T2A MODE = 1
T2A MODE = 0
Fourteen T2A module-control registers: Located in the PF frame beginning at address P060
-
-
-
-
-
Interrupts that can be generated on the occurrence of:
Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T2AIC1/CR)
BIT 7
--
--
A compare equal to dedicated compare register
An external edge 2 detection
An external edge 1 detection
A counter overflow
A compare equal to capture-compare register
T2AIC2 / PWM DATA OUT
T2AEDGE2 INT FLAG
T2A PRIORITY
T2AC2 INT FLAG
T2AC1 OUT ENA
BIT 6
--
--
--
Table 19. Timer 2A Module Register Memory Map
T2AIC2 / PWM FUNCTION
T2AC1 INT FLAG
T2AC1 INT FLAG
T2AC2 OUT ENA
BIT 5
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--
--
--
--
Capture/Compare Register MSbyte
Capture/Compare Register LSbyte
Capture Register 2 MSbyte
Capture Register 2 LSbyte
Compare Register MSbyte
Compare Register LSbyte
T2AIC2 / PWM DATA DIR
T2A OVRFL INT ENA
T2A Counter MSbyte
T2AC1 RST ENA
T2AC1 RST ENA
T2A Counter LSbyte
BIT 4
--
--
--
--
* HOUSTON, TEXAS 77251-1443
T2AEDGE2 POLARITY T2AEDGE1 OUT ENA T2A OVRFL INT FLAG T2AIC1/CR DATA IN T2AEVT DATA IN BIT 3 -- -- -- T2AEDGE1 POLARITY T2AEDGE1 INT ENA T2AEDGE1 POLARITY T2AEDGE1 INT ENA T2AIC1/CR DATA OUT T2AEVT DATA OUT T2A INPUT SELECT1 BIT 2 -- T2AEDGE2 DET ENA T2AEDGE2 INT ENA T2AEDGE1 RST ENA T2AEVT FUNCTION T2AIC1/CR FUNCTION T2A INPUT SELECT0 T2AC2 INT ENA BIT 1 -- T2AEDGE1 DET ENA T2AEDGE1 DET ENA T2AIC1/CR DATA DIR T2AEVT DATA DIR T2AC1 INT ENA T2AC1 INT ENA T2A SW RESET BIT 0 -- Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 T2APRI T2APC2 T2APC1 T2ACTL3 T2ACTL2 T2ACTL3 T2ACTL2 T2ACTL1 T2AIC T2ACC T2AC REG
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
T2ACNTR
33
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
timer 2A module (continued)
The T2A dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh, bit 0, in the T2ACTL2 register.
T2ACC.15-0
16-Bit Capt/Comp LSB Register MSB
Clock Source
T2AC2 INT FLAG T2ACTL2.6
Output Enable
T2ACNTR.15-0
LSB MSB 16-Bit Counter Reset T2A SW RESET
Compare=
T2ACTL2.1
T2AC2 INT ENA
T2ACTL3.5
T2AC2 OUT ENA T2ACTL3.6 T2AC1 OUT ENA
T2APC2.7-4
Toggle 0 1 T2AIC2/PWM
16 Compare=
T2AC1 INT FLAG T2ACTL2.5
T2ACTL2.0
T2AC1 INT ENA
T2ACTL1.0
T2AC.15-0 T2AC1 RST ENA 16-Bit LSB T2ACTL3.4 Compare Register MSB
T2ACTL3.3
T2AEDGE1 OUT ENA
T2APC2.3-0
T2AIC1/CR
T2ACTL3.1 T2AEDGE1 RST ENA
Edge 1 Select
T2A OVRFL INT FLAG T2ACTL1.3
T2ACTL1.4 T2A OVRFL INT ENA
T2A PRIORITY
T2ACTL3.0 T2AEDGE1 DET ENA T2ACTL3.2 T2AEDGE1 POLARITY
T2AEDGE1 INT FLAG
T2APRI.6
Level 1 Int Level 2 Int
T2ACTL2.7 T2ACTL2.2
T2AEDGE1 INT ENA
Figure 12. Dual-Compare Mode
34
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
timer 2A module (continued)
The T2A dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh, bit 0, in the T2ACTL2 register.
T2ACC.15-0
16-Bit Capt/Comp Register 1 LSB MSB
T2AIC.15-0
16-Bit Capture Register 2 LSB MSB
Clock Source
T2ACNTR.15-0
LSB MSB 16-Bit Counter 16 T2A PRIORITY Compare = Reset T2AC1 INT FLAG T2ACTL2.5
T2APRI.6
0 Level 1 Int 1 Level 2 Int
T2AC.15-0
T2A SW RESET 16-Bit Compare Register LSB MSB
T2ACTL2.0 T2AC1 INT ENA
T2A OVRFL INT FLAG
T2ACTL1.0
T2AC1 RST ENA
T2ACTL1.3 T2ACTL1.4 T2A OVRFL INT ENA
T2ACTL3.4 T2ACTL3.0 T2AEDGE1 DET ENA T2APC2.3-0
T2AIC1/CR Edge1 Select T2AEDGE1 INT FLAG
T2ACTL2.7 T2ACTL2.2 T2AEDGE1 INT ENA
T2ACTL3.2
T2AEDGE1 POLARITY
T2ACTL3.1
T2AEDGE2 DET ENA
T2APC2.7-4
T2AIC2/PWM Edge 2 Select
T2AEDGE2 INT FLAG
T2ACTL2.6 T2ACTL3.3
T2AEDGE2 POLARITY
T2ACTL2.1
T2AEDGE2 INT ENA
Figure 13. Dual-Capture Mode
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35
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
serial peripheral interface (SPI) module
The SPI is a high-speed, synchronous, serial I/O port that allows a serial bit stream of programmed length (1 to 8 bits) to be shifted into, and out of, the device at a programmable bit-transfer rate.The SPI is used normally for communications between the microcontroller and external peripherals or another microcontroller. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and analog-to-digital converters. The master/slave operation of the SPI supports multi-device communications. The SPI module features include the following:
D
Three external pins: - - - SPISOMI: SPI slave output/master input pin or general purpose bidirectional I/O pin SPISIMO: SPI slave input/master output pin or general purpose bidirectional I/O pin SPICLK: SPI serial clock pin or general purpose bidirectional I/O pin
D D
Two operational modes: master and slave Baud rate: Eight different programmable rates - Maximum baud rate in master mode: 2.5M bps at 5-MHz SYSCLK SPI BAUD RATE -
+ SYSCLK 22
b
Maximum baud rate in slave mode: 625K bps at 5-MHz SYSCLK. For maximum slave SPI BAUD RATE < SYSCLK/8
where b = bit rate in SPICCR.5-3 (range 0-7)
D D D D
Data word format: one to eight data bits Simultaneous receive and transmit operation (transmit function can be disabled in software) Transmitter and receiver operations are accomplished through either interrupt driven or polled algorithms. Seven SPI module control registers located in control register frame beginning at address P030h
36
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AA A A A A A AAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAA A A AAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AAA A AA AA AA AA A AA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AA AAA A A A A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AA A AAA A A A A A A A AAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A A A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AAA A A AAA A A A A A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A A A A A A A AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA
serial peripheral interface (SPI) module (continued)
P03D P03A to P03C P03E P03F P039 P038 P037 P032 to P036 P031 P030 PF
The SPI module control registers are illustrated in Table 20.
RECEIVER OVERRUN
SPISIMO DATA IN
SPI SW RESET
RCVD7
SPI STEST
SDAT7
BIT 7
--
CLOCK POLARITY
SPISIMO DATA OUT
SPI PRIORITY
SPI INT FLAG
RCVD6
SDAT6
BIT 6
--
Table 20. SPI Module Control Register Memory Map
SPISIMO FUNCTION
SPI BIT RATE2
RCVD5
SPI ESPEN
SDAT5
BIT 5
--
--
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SPISIMO DATA DIR
SPI BIT RATE1
RCVD4
SDAT4
BIT 4
--
--
--
Reserved
Reserved
Reserved
* HOUSTON, TEXAS 77251-1443
SPISOMI DATA IN SPICLK DATA IN SPI BIT RATE0 RCVD3 SDAT3 BIT 3 -- -- SPICLK DATA OUT SPISOMI DATA OUT MASTER/ SLAVE SPI CHAR2 RCVD2 SDAT2 BIT 2 -- SPISOMI FUNCTION SPICLK FUNCTION RCVD1 SPI CHAR1 SDAT1 BIT 1 TALK -- SPISOMI DATA DIR SPICLK DATA DIR SPI INT ENA SPI CHAR0 RCVD0 SDAT0 BIT 0 -- SPIPRI SPIPC2 SPIPC1 SPIDAT SPIBUF SPICTL SPICCR REG
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
37
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
serial peripheral interface (SPI) module (continued)
The SPI block diagram is illustrated in Figure 14.
SPIBUF.7-0
SPIBUF Buffer Register RECEIVER OVERRUN
SPICTL.7
8 SPI INT FLAG
SPIPRI.6 SPICTL.0
0 1 SPIINT ENA
Level 1 INT Level 2 INT
SPICTL.6
SPIDAT Data Register
SPIPC2.7-4
SPISIMO
SPIDAT.7-0
SPICTL.1 SPIPC2.3-0
TALK SPISOMI
State Control
MASTER/SLAVE SPI CHAR
SPICCR.2-0
2 1 0
SPICTL.2 SPIPC1.3-0
System Clock
SPICCR.5-3
5 4 3
SPICCR.6
CLOCK POLARITY
SPICLK
SPI BIT RATE The diagram is shown in slave mode.
Figure 14. SPI Block Diagram
serial communications interface 1 (SCI1) module
The TMS370x5x devices include a serial communications interface (SCI1) module. The SCI1 module supports digital communications between the TMS370 devices and other asynchronous peripherals and uses the standard non-return-zero format (NRZ) format. The SCI1's receiver and transmitter are double buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity, overrun, and framing errors. The speed of bit rate (baud) is programmable to over 65,000 different speeds through a 16-bit baud-select register.
38
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
serial communications interface 1 (SCI1) module (continued)
Features of the SCI1 module include:
D
Three external pins: - - - SCITXD: SCI transmit output pin or general-purpose bidirectional I/O pin SCIRXD: SCI receive input pin or general-purpose bidirectional I/O pin SCICLK: SCI bidirectional serial clock pin, or general-purpose bidirectional I/O pin
D D
Two communications modes: asynchronous and isosynchronous Baud rate: 64K different programmable rates - Asynchronous mode: 3 bps to 156K bps at 5-MHz SYSCLK ASYNCHRONOUS BAUD -
+ (BAUD SYSCLK1) REG ) + (BAUDSYSCLK 1) REG )
32
Isosynchronous mode: 39 bps to 2.5M bps at 5-MHz SYSCLK ISOSYNCHRONOUS BAUD 2
D
Data-word format - - - - One start bit Data-word length programmable from 1 to 8 bits Optional even/odd/no parity bit One or two stop bits
D D D D D
Four error-detection flags: parity, overrun, framing, and break detection Two wake-up multiprocessor modes: Idle-line and address bit Half or full-duplex operation Double-buffered receive and transmit functions Interrupt driven or polled algorithms with status flags accomplish transmitter (TX) and receiver (RX) operations. - - - - Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX EMPTY flag (transmitter shift register is empty) Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR monitoring four interrupt conditions Separate enable bits for transmitter and receiver interrupts NRZ (non return-to-zero) format
D
Eleven SCI1 module control registers are located in control register frame beginning at address P050h.
Isosynchronous = Isochronous
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39
AA AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A AAA A A A A A A A A A AA A AA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAA AA A A AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAA AAAA AAA AAAAAA A A AA AAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A A AA AAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AA AAA AA A A AA AAA AA A AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAA AA A A AA AAA AA A AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAA AA A A AA AAA AA A AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AA AAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
40 P05A P05B P05C P05D
serial communications interface 1 (SCI1) module (continued)
P059
P058
P056
P05E
P05F
P057
P055
P054
P053
P052
P051
P050
PF
The SCI1 module block diagram is illustrated in Figure 15.
The SCI1 module control registers are illustrated in Table 21.
STOP BITS
SCI STEST
SCITXD DATA IN
RX ERROR
TXRDY
BAUDF (MSB)
BAUD7
RXDT7
TXDT7
BIT 7
--
--
EVEN/ODD PARITY
TX EMPTY
SCITXD DATA OUT
SCITX PRIORITY
RXRDY
BAUDE
BAUD6
RXDT6
TXDT6
BIT 6
--
--
Table 21. SCI1 Module Control Register Memory Map
SCITXD FUNCTION
SCIRX PRIORITY
PARITY ENABLE
SCI SW RESET
BAUDD
BRKDT
BAUD5
RXDT5
TXDT5
BIT 5
--
--
POST OFFICE BOX 1443
SCITXD DATA DIR
ASYNC/ ISOSYNC
BAUDC
CLOCK
SCI ESPEN
BAUD4
RXDT4
TXDT4
BIT 4
FE
--
--
Reserved
Reserved
Reserved
* HOUSTON, TEXAS 77251-1443
ADDRESS/ IDLE WUP TXWAKE SCIRXD DATA IN SCICLK DATA IN BAUDB BAUD3 RXDT3 TXDT3 BIT 3 OE -- -- SCI CHAR2 SCICLK DATA OUT SCIRXD DATA OUT BAUDA BAUD2 RXDT2 SLEEP TXDT2 BIT 2 PE -- -- SCI CHAR1 SCIRXD FUNCTION RXWAKE BAUD1 BAUD9 TXENA RXDT1 TXDT1 BIT 1 -- SCICLK FUNCTION -- SCI CHAR0 SCIRXD DATA DIR SCI RX INT ENA SCI TX INT ENA RXENA BAUD0 (LSB) BAUD8 RXDT0 TXDT0 BIT 0 SCICLK DATA DIR -- SCIPRI TXBUF RXCTL TXCTL REG SCIPC2 SCIPC1 RXBUF SCICTL BAUD LSB SCICCR BAUD MSB
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
serial communications interface 1 (SCI1) module (continued)
Frame Format and Mode PARITY EVEN / ODD ENABLE TXWAKE SCICTL.3 1 WUT 8 TX EMPTY TXCTL.6 TXENA
TXBUF.7 - 0
SCICCR.6 SCICCR.5
TXRDY TXCTL.7
SCI TX INT ENA
TXCTL.0
BAUD MSB. 7 - 0
Baud Rate MSbyte Reg. SYSCLK
TXSHF Reg.
SCITXD
SCICTL.1
CLOCK
BAUD LSB. 7 - 0
Baud Rate LSbyte Reg.
SCICTL.4
RXSHF Reg. RXWAKE
SCIRXD
RXCTL.1
RXENA RX ERROR
SCI RX Interrupt RXRDY RXCTL.6 SCI RX INT ENA
SCICTL.0
8 Receive Data Buffer Reg.
RXCTL.7
ERR
RXCTL.4 - 2
FE OE PE BRKDT RXCTL.5
RXCTL.0
RXBUF.7 - 0
Figure 15. SCI1 Block Diagram
analog-to-digital converter 1 (ADC1) module
The analog-to-digital converter 1 (ADC1) module is an 8-bit, successive approximation converter with internal sample-and-hold circuitry. The module has eight multiplexed analog input channels that allow the processor to convert the voltage levels from up to eight different sources. The ADC1 module features include the following:
D D
Minimum conversion time: 32.8 s at 5-MHz SYSCLK Ten external pins: - - - - Eight analog input channels (AN0 - AN7), any of which can be software configured as digital inputs (E0- E7) if not needed as analog channels AN1- AN7 can also be configured as positive-input voltage reference. VCC3: A/D module high-voltage reference input VSS3: A/D module low-voltage reference input
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IIII IIII
III III
SCIPRI.6 SCIPRI.5
Transmit Data Buffer Reg.
SCI TX Interrupt
SCITX PRIORITY 0 1 Level 1 INT Level 2 INT
SCIPC2.7 - 4
SCITXD
SCIPC1.3 - 0
SCICLK
SCIPC2.3 - 0
SCIRXD
SCIRX PRIORITY 0 1 Level 1 INT Level 2 INT
41
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
analog-to-digital converter 1 (ADC1) module (continued)
D D D
The ADDATA register, which contains the digital result of the last ADC1 conversion ADC1 operations can be accomplished through either interrupt driven or polled algorithms. Six ADC1 module control registers are located in the control-register frame beginning at address 1070h.
The ADC1 module control registers are illustrated in Table 22. Table 22. ADC1 Module Control Register Memory Map
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AAA AA AA AA AA AA A A AAAAAAAAAAAAAAAAAAAAA A AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAA A A AAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAA AAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AAA AA AA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A AA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAA
PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG P070 P071 CONVERT START -- SAMPLE START -- REF VOLT SELECT2 -- REF VOLT SELECT1 -- REF VOLT SELECT0 -- AD INPUT SELECT2 AD INPUT SELECT1 AD INT FLAG AD INPUT SELECT0 AD INT ENA ADCTL AD READY ADSTAT
P072
A-to-D Conversion Data Register Reserved
ADDATA
P073 to P07C P07E
P07D
Port E Data Input Register
ADIN
Port E Input Enable Register
-- --
ADENA
ADPRI
P07F
AD STEST
AD PRIORITY
AD ESPEN
--
--
--
42
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
analog-to-digital converter 1 (ADC1) module (continued)
The ADC1 module block diagram is illustrated in Figure 16.
Port E Input ENA 0 Port E Data AN 0
ADENA.0 AN0
Port E Input ENA 1
ADIN.0
2
1
0
SAMPLE START
CONVERT START
ADCTL.2 - 0
Port E Data AN 1 AD INPUT SELECT
ADCTL.6
ADCTL.7
ADENA.1 AN1
Port E Input ENA 2
ADIN.1
Port E Data AN 2
ADENA.2 AN2
Port E Input ENA 3
ADIN.2
Port E Data AN 3
ADENA.3 AN3
Port E Input ENA 4
ADIN.3
ADC1 Port E Data AN 4
ADENA.4 AN4
Port E Input ENA 5
ADIN.4 ADDATA.7 - 0
Port E Data AN 5 A-to-D Conversion Data Register AD READY
ADENA.5 AN5
Port E Input ENA 6
ADIN.5
Port E Data AN 6
ADENA.6 AN6
Port E Input ENA 7
ADSTAT.2
5 4 3 AD PRIORITY
ADIN.6
ADCTL.5 - 3
Port E Data AN 7 REF VOLTS SELECT
ADPRI.6
0 Level 1 INT 1 Level 2 INT
ADENA.7 AN7
ADIN.7
VCC3 VSS3
AD INT FLAG
ADSTAT.1 ADSTAT.0
AD INT ENA
Figure 16. ADC1 Block Diagram
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43
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
instruction set overview
Table 23 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the `370Cx5x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode while the numbers at the left side of the table represent the least significant nibble. The instruction of these two opcode nibbles contains the mnemonic, operands, and byte / cycle particular to that opcode. For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles.
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Table 23. TMS370 Family Opcode/Instruction Map
MSN 0 0 JMP #ra 2/7 JN ra 2/5 JZ ra 2/5 JC ra 2/5 JP ra 2/5 JPZ ra 2/5 JNZ ra 2/5 JNC ra 2/5 JV ra 2/5 JL ra 2/5 JLE ra 2/5 JHS ra 2/5 MOV Rs,A 2/7 AND Rs,A 2/7 OR Rs,A 2/7 XOR Rs,A 2/7 BTJO Rs,A,ra 3/9 BTJZ Rs.,A,ra 3/9 ADD Rs,A 2/7 ADC Rs,A 2/7 SUB Rs,A 2/7 SBB Rs,A 2/7 MOV A,Pd 2/8 MOV #n,A 2/6 AND #n,A 2/6 OR #n,A 2/6 XOR #n,A 2/6 BTJO #n,A,ra 3/8 BTJZ #n,A,ra 3/8 ADD #n,A 2/6 ADC #n,A 2/6 SUB #n,A 2/6 SBB #n,A 2/6 MOV Rs,B 2/7 AND Rs,B 2/7 OR Rs,B 2/7 XOR Rs,B 2/7 BTJO Rs,B,ra 3/9 BTJZ Rs,B,ra 3/9 ADD Rs,B 2/7 ADC Rs,B 2/7 SUB Rs,B 2/7 SBB Rs,B 2/7 MOV Rs,Rd 3/9 AND Rs,Rd 3/9 OR Rs,Rd 3/9 XOR Rs,Rd 3/9 BTJO Rs,Rd,ra 4/11 BTJZ Rs,Rd,ra 4/11 ADD Rs,Rd 3/9 ADC Rs,Rd 3/9 SUB Rs,Rd 3/9 SBB Rs,Rd 3/9 MOV B,Pd 2/8 MOV #n,B 2/6 AND #n,B 2/6 OR #n,B 2/6 XOR #n,B 2/6 BTJO #n,B,ra 3/8 BTJZ #n,B,ra 3/8 ADD #n,B 2/6 ADC #n,B 2/6 SUB #n,B 2/6 SBB #n,B 2/6 MOV B,A 1/8 AND B,A 1/8 OR B,A 1/8 XOR B,A 1/8 BTJO B,A,ra 2/10 BTJZ B,A,ra 2/10 ADD B,A 1/8 ADC B,A 1/8 SUB B,A 1/8 SBB B,A 1/8 1 2 3 4 5 6 7 INCW #ra,Rd 3/11 MOV Rs,Pd 3/10 MOV #n,Rd 3/8 AND #n,Rd 3/8 OR #n,Rd 3/8 XOR #n,Rd 3/8 BTJO #n,Rd,ra 4/10 BTJZ #n,Rd,ra 4/10 ADD #n,Rd 3/8 ADC #n,Rd 3/8 SUB #n,Rd 3/8 SBB #n,Rd 3/8 AND A,Pd 2/9 OR A,Pd 2/9 XOR A,Pd 2/9 BTJO A,Pd,ra 3/11 BTJZ A,Pd,ra 3/10 MOVW #16,Rd 4/13 JMPL lab 3/9 MOV & lab,A 3/10 MOV A, & lab 3/10 AND B,Pd 2/9 OR B,Pd 2/9 XOR B,Pd 2/9 BTJO B,Pd,ra 3/10 BTJZ B,Pd,ra 3/10 MOVW Rs,Rd 3/12 JMPL *Rp 2/8 MOV *Rp,A 2/9 MOV A, *Rp 2/9 8 MOV Ps,A 2/8 MOV Ps,B 2/7 MOV Ps,Rd 3/10 AND #n,Pd 3/10 OR #n,Pd 3/10 XOR #n,Pd 3/10 BTJO #n,Pd,ra 4/11 BTJZ #n,Pd,ra 4/11 MOVW #16[B],Rpd 4/15 JMPL *lab[B] 3/11 MOV *lab[B],A 3/12 MOV A,*lab[B] 3/12 DEC A 1/8 INC A 1/8 INV A 1/8 CLR A 1/8 XCHB A 1/10 SWAP A 1/11 PUSH A 1/9 POP A 1/9 DJNZ A,#ra 2/10 COMPL A 1/8 DEC B 1/8 INC B 1/8 INV B 1/8 CLR B 1/8 XCHB A / TST B 1/10 SWAP B 1/11 PUSH B 1/9 POP B 1/9 DJNZ B,#ra 2/10 COMPL B 1/8 9 A B CLRC / TST A 1/9 C MOV A,B 1/9 D MOV A,Rd 2/7 MOV B,Rd 2/7 DEC Rd 2/6 INC Rd 2/6 INV Rd 2/6 CLR Rn 2/6 XCHB Rn 2/8 SWAP Rn 2/9 PUSH Rd 2/7 POP Rd 2/7 DJNZ Rd,#ra 3/8 COMPL Rd 2/6 E TRAP 15 1/14 TRAP 14 1/14 TRAP 13 1/14 TRAP 12 1/14 TRAP 11 1/14 TRAP 10 1/14 TRAP 9 1/14 TRAP 8 1/14 TRAP 7 1/14 TRAP 6 1/14 TRAP 5 1/14 TRAP 4 1/14 IDLE 1/6 MOV #n,Pd 3/10 SETC 1/7 RTS 1/9 RTI 1/12 PUSH ST 1/8 F LDST n 2/6 MOV #ra[SP],A 2/7 MOV A,*ra[SP] 2/7 CMP *n[SP],A 2/8 extend inst,2 opcodes
1
2
3
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L S N
5
6
7
8
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SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
A
B
TMS370Cx5x 8-BIT MICROCONTROLLER
All conditional jumps (opcodes 01 - 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand.
45
Table 23. TMS370 Family Opcode/Instruction Map (Continued)
MSN 0 C JNV ra 2/5 JGE ra 2/5 JG ra 2/5 JLO ra 2/5 1 MPY Rs,A 2/46 CMP Rs,A 2/7 DAC Rs,A 2/9 DSB Rs,A 2/9 2 MPY #n,A 2/45 CMP #n,A 2/6 DAC #n,A 2/8 DSB #n,A 2/8 3 MPY Rs,B 2/46 CMP Rs,B 2/7 DAC Rs,B 2/9 DSB Rs,B 2/9 4 MPY Rs,Rd 3/48 CMP Rs,Rd 3/9 DAC Rs,Rd 3/11 DSB Rs,Rd 3/11 5 MPY #n,B 2/45 CMP #n,B 2/6 DAC #n,B 2/8 DSB #n,B 2/8 6 MPY B,A 1/47 CMP B,A 1/8 DAC B,A 1/10 DSB B,A 1/10 7 MPY #n,Rs 3/47 CMP #n,Rd 3/8 DAC #n,Rd 3/10 DSB #n,Rd 3/10 8 BR lab 3/9 CMP & lab,A 3/11 CALL lab 3/13 CALLR lab 3/15 9 BR *Rp 2/8 CMP *Rp,A 2/10 CALL *Rp 2/12 CALLR *Rp 2/14 A BR *lab[B] 3/11 CMP *lab[B],A 3/13 CALL *lab[B] 3/15 CALLR *lab[B] 3/17 B RR A 1/8 RRC A 1/8 RL A 1/8 RLC A 1/8 C RR B 1/8 RRC B 1/8 RL B 1/8 RLC B 1/8 D RR Rd 2/6 RRC Rd 2/6 RL Rd 2/6 RLC Rd 2/6 E TRAP 3 1/14 TRAP 2 1/14 TRAP 1 1/14 TRAP 0 1/14 F POP ST 1/8 LDSP 1/7 STSP 1/8 NOP 1/7
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
46
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Template Release Date: 7-11-94
Second byte of two-byte instructions (F4xx):
F4
8
MOVW *n[Rn] 4/15 JMPL *n[Rn] 4/16 MOV *n[Rn],A 4/17 MOV A,*n[Rn] 4/16 BR *n[Rn] 4/16 CMP *n[Rn],A 4/18 CALL *n[Rn] 4/20 CALLR *n[Rn] 4/22
DIV Rn.A 3/14-63
F4 Legend: * = Indirect addressing operand prefix & = Direct addressing operand prefix # = immediate operand #16 = immediate 16-bit number lab = 16-label n = immediate 8-bit number i di t 8 bit b Pd = Peripheral register containing destination type Pn = Peripheral register Ps = Peripheral register containing source byte Peri heral ra = Relative address Rd = Register containing destination type Rn = Register file Rp = Register pair Rpd = Destination register pair Rps = Source Register pair Rs = Register containing source byte
9
F4
A
F4
B
F4
C
F4
D
F4
E
F4
F
All conditional jumps (opcodes 01 - 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand.
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
development system support
The TMS370 family development support tools include an assembler, a C compiler, a linker, an in-circuit emulator (XDS/22), CDT, and an EEPROM / UVEPROM programmer.
D
Assembler/ linker (Part No. TMDS3740850-02 for PC) - - - Includes extensive macro capability Features high-speed operation Includes format conversion utilities for popular formats
D
ANSI C-Compiler (Part No. TMDS3740855-02 for PC, Part No. TMDS3740555-09 for HP700TM, Sun-3TM or Sun-4TM) - - - - - - Generates assembly code for the TMS370 that can be inspected easily Improves code execution speed and reduces code size with optional optimizer pass Enables direct reference of the TMS370's port registers by using a naming convention Provides flexibility in specifying the storage for data objects Interfaces C functions and assembly functions easily Includes assembler and linker
D
CDT370 (compact development tool) real-time in-circuit emulation - Base (Part Number EDSCDT370 - for PC, requires cable) - - - - - - - - - Cable for 68-pin PLCC (Part No. EDSTRG68PLCC) Cable for 64-pin SDIP (Part No. EDSTRG64SDIL)
Provides EEPROM and EPROM programming support Allows inspection and modification of memory locations Allows uploading / downloading of program and data memory Provides capability to execute programs and software routines Includes 1 024 samples trace buffer Includes single-step executable instructions Allows use of software breakpoints to halt program execution at selected address
D
XDS/ 22 (extended development support) in-circuit emulator - - - - - - Base (Part Number TMDS3762210 for PC, requires cable) Cable for 68-pin PLCC / 64-Pin SDIP (Part No. TMDS3788868) Contains all of the features of the CDT370 described above but does not have the capability to program the data EEPROM and program EPROM Contains sophisticated breakpoint trace and timing hardware that provides up to 2 047 qualified trace samples with symbolic disassembly Allows breakpoints to be qualified by address and / or data on any type of memory acquisition. Up to four levels of events can be combined to cause a breakpoint Provides timers for analyzing total and average time in routines
HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
development system support (continued)
- Contains an eight-line logic probe for adding visibility of external signals to the breakpoint qualifier and for tracing display
D
Microcontroller programmer - Base (Part No. TMDS3760500A - for PC, requires programmer head) - - - Single unit head for 68-pin PLCC (Part No. TMDS3780510A) Single unit head for 64-pin SDIP (Part No. TMDS3780511A)
Personal computer-based, window / function-key oriented user interface for ease of use and rapid learning environment
D
Design kit (Part No. TMDS3770110 - for PC) - - - - - - - Includes TMS370 Application Board and TMS370 Assembler diskette and documentation. Supports quick evaluation of TMS370 functionality Provides capability to upload and download code Provides capability to execute programs and software routines, and to single-step executable instructions Allows software breakpoints to halt program execution at selected addresses Includes wire-wrap prototype area Includes reverse assembler
D
Starter Kit (Part No. TMDS37000 - For PC) - - - - Includes TMS370 Assembler diskette and documentation Includes TMS370 Simulator Includes programming adapter board and programming software Does not include - (to be supplied by the user): - - - + 5 V power supply ZIF sockets 9-pin RS232 cable
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
device numbering conventions
Figure 17 illustrates the numbering and symbol nomenclature for the TMS370Cx5x family.
TMS 370 C 7 5 2 A FN T Prefix: TMS = Standard prefix for fully qualified devices SE = System evaluator (window EPROM) that is used for prototyping purpose. Family: Technology: Program Memory Types: 370 = TMS370 8-Bit Microcontroller Family C = CMOS 0 1 2 3 4 7 = = = = = = Mask ROM ROM-less, No Data EEPROM ROM-less Mask ROM, No Data EEPROM ROM memory with security EPROM
Device Type:
5 = 'x5x device containing the following modules: - Timer 1 - Timer 2A - Serial Peripheral Interface - Serial Communications Interface 1 - Analog-to-Digital Converter 1 0 2 3 6 8 9 = = = = = = 4K bytes 8K bytes 12K bytes 16K bytes 32K Bytes 48K Bytes
Memory Size:
Temperature Ranges:
A = - 40C to 85C L= 0C to 70C T = - 40C to 105C FN FZ NM JN = = = = Plastic Leaded Chip Carrier Ceramic Leaded Chip Carrier Plastic Shrink Dual-In-Line Ceramic Shrink Dual-in-Line
Packages:
ROM and EPROM Option:
A = For ROM device, the watchdog timer can be configured as one of the three different mask options: - A standard watchdog - A hard watchdog - A simple watchdog The clock can be either: - Divide-by-4 clock - Divide-by-1 (PLL) clock The low-power modes can be either: - Enabled - Disabled A = For ROM-less device, a standard watchdog, a divide-by-4 clock, and low-power modes are enabled. A = For EPROM device, a standard watchdog, a divide-by-4 clock, and low-power modes are enabled. B = For EPROM device, a hard watchdog, a divide-by-1 (PLL) clock, and low-power modes are enabled.
Figure 17. TMS370Cx5x Family Nomenclature
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
device part numbers
Table 24 provides a list of all the `x5x devices available. The device part number nomenclature is designed to assist ordering. Upon ordering, the customer must specify not only the device part number but also the clock and watchdog timer options desired. Remember that each device can have only one of the three possible watchdog timer options and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices. Table 24. Device Part Numbers
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DEVICE PART NUMBERS FOR 68 PINS TMS370C050AFNA TMS370C050AFNL TMS370C050AFNT TMS370C150AFNT TMS370C250AFNT DEVICE PART NUMBERS FOR 64 PINS TMS370C050ANMA TMS370C050ANML TMS370C050ANMT -- -- DEVICE PART NUMBERS FOR 68 PINS TMS370C356AFNA TMS370C356AFNL TMS370C356AFNT TMS370C456AFNA TMS370C456AFNL TMS370C456AFNT TMS370C756AFNT DEVICE PART NUMBERS FOR 64 PINS TMS370C356ANMA TMS370C356ANML TMS370C356ANMT -- TMS370C756ANMT TMS370C350AFNA TMS370C350AFNL TMS370C350AFNT TMS370C052AFNA TMS370C052AFNL TMS370C052AFNT TMS370C352AFNA TMS370C352AFNL TMS370C352AFNT TMS370C452AFNA TMS370C452AFNL TMS370C452AFNT TMS370C353AFNA TMS370C353AFNL TMS370C353AFNT TMS370C056AFNA TMS370C056AFNL TMS370C056AFNT TMS370C156AFNT TMS370C256AFNT TMS370C350ANMA TMS370C350ANML TMS370C350ANMT TMS370C052ANMA TMS370C052ANML TMS370C052ANMT TMS370C352ANMA TMS370C352ANML TMS370C352ANMT -- TMS370C058AFNA TMS370C058AFNL TMS370C058AFNT TMS370C358AFNA TMS370C358AFNL TMS370C358AFNT TMS370C758AFNT TMS370C058ANMA TMS370C058ANML TMS370C058ANMT TMS370C358ANMA TMS370C358ANML TMS370C358ANMT TMS370C758ANMT TMS370C758BFNT TMS370C758BNMT -- TMS370C059AFNA TMS370C059AFNL TMS370C059AFNT TMS370C759AFNT SE370C756AFZT SE370C758AFZT SE370C758BFZT SE370C759AFZT -- TMS370C056ANMA TMS370C056ANML TMS370C056ANMT -- -- -- SE370C756AJNT SE370C758AJNT SE370C758BJNT Only operate up to 3 MHz SYSCLK System evaluators are for use only in prototype environment, and their reliability has not been characterized. 50
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
new code release form
Figure 18 shows a sample of the new code release form.
NEW CODE RELEASE FORM TEXAS INSTRUMENTS TMS370 MICROCONTROLLER PRODUCTS
DATE:
To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:
1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media) 2. An attached specification if not using TI standard specification as incorporated in TI's applicable device data book.
Company Name: Street Address: Street Address: City: Customer Part Number: Customer Application:
Contact Mr./Ms.: Phone: ( State Zip
)
Ext.:
Customer Purchase Order Number: Customer Print Number *Yes: # No: (Std. spec to be followed) *If Yes: Customer must provide "print" to TI w/NCRF for approval before ROM code processing starts.
TMS370 Device: TI Customer ROM Number: (provided by Texas Instruments) OSCILLATOR FREQUENCY MIN [] External Drive (CLKIN) [] Crystal [] Ceramic Resonator TYP MAX
CONTACT OPTIONS FOR THE 'A' VERSION TMS370 MICROCONTROLLERS
Low Power Modes [] Enabled [] Disabled
Watchdog counter [] Standard [] Hard Enabled [] Simple Counter
Clock Type [] Standard (/4) [] PLL (/1)
[] Supply Voltage MIN: (std range: 4.5V to 5.5V)
MAX:
NOTE: Non 'A' version ROM devices of the TMS370 microcontrollers will have the "Low-power modes Enabled", "Divide-by-4" Clock, and "Standard" Watchdog options. See the TMS370 Family User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). PACKAGE TYPE [] 'N' 28-pin PDIP [] "FN" 44-pin PLCC [] "FN" 28-pin PLCC [] "FN" 68-pin PLCC [] "N" 40-pin PDIP [] "NM" 64-pin PSDIP [] "NJ" 40-pin PSDIP (formerly known as N2) BUS EXPANSION [] YES [] NO
TEMPERATURE RANGE [] 'L': 0 to 70C (standard) [] 'A': -40 to 85C [] 'T': -40 to 105C SYMBOLIZATION [] TI standard symbolization [] TI standard w/customer part number [] Customer symbolization (per attached spec, subject to approval)
NON-STANDARD SPECIFICATIONS: ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material (i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a 'P' in the symbolization preceding the TI part number.
RELEASE AUTHORIZATION: This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification code is approved by the customer.
1. Customer:
Date:
2. TI: Field Sales: Marketing: Prod. Eng.: Proto. Release:
Figure 18. Sample New Code Release Form
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SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
52
P02D P02C P01D P01C P02E P02B P02A P01E P01B P01A P02F P01F P029 P028 P027 P026 P025 P024 P023 P022 P021 P020 P019 P018 P017 P015 to P016 P014 P013 P012 P010 P011 PF HALT/ STANDBY COLD START BUSY BUSY BUSY BUSY INT3 FLAG INT2 FLAG INT1 FLAG BIT 7 PWRDWN/ IDLE INT3 PIN DATA INT2 PIN DATA INT1 PIN DATA OSC POWER VPPS VPPS VPPS BIT 6 -- --
Table 25 is a listing of all the peripheral file frames using the 'Cx5x (provided for a quick reference).
To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
PF AUTO WAIT
Table 25. Peripheral File Frame Compilation
BIT 5
--
--
--
--
--
--
--
--
--
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SYSTEM CONFIGURATION REGISTERS
DIGITAL PORT CONTROL REGISTERS
AUTOWAIT DISABLE
INT3 DATA DIR
INT2 DATA DIR
OSC FLT FLAG
Port D Control Register 2
BUS STEST
Port D Control Register 1
Port C Control Register 2
Port B Control Register 2
Port A Control Register 2
BIT 4
--
--
--
--
--
Port D Direction
Port C Direction
Port B Direction
Port A Direction
Port D Data
Port C Data
Port B Data
Port A Data
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
* HOUSTON, TEXAS 77251-1443
INT3 DATA OUT INT2 DATA OUT MC PIN WPO CPU STEST BIT 3 -- -- -- -- -- -- INT3 POLARITY INT2 POLARITY INT1 POLARITY MEMORY DISABLE MC PIN DATA BIT 2 AP -- -- -- -- INT3 PRIORITY INT2 PRIORITY INT1 PRIORITY W1W0 BIT 1 INT1 NMI W0 W0 W0 -- -- PRIVILEGE DISABLE INT3 ENABLE INT2 ENABLE INT1 ENABLE P/C MODE BIT 0 EXE EXE EXE EXE -- DDIR CDIR BDIR ADIR INT3 INT2 INT1 REG DDATA CDATA BDATA ADATA DPORT2 DPORT1 CPORT2 CPORT1 BPORT2 BPORT1 APORT2 APORT1 EPCTLL SCCR2 SCCR1 SCCR0 DEECTL EPCTLH EPCTLM
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P03A to P03C P03D P03E P03F P039 P038 P037 P032 to P036 P031 P030 P04C P04B P04B P04A P049 P048 P047 P046 P045 P044 P043 P042 P041AAAA Bit 7 P040 PF
Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored.
Mode: Capture/Compare
Mode: Dual-Compare
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 15
Modes: Dual-Compare and Capture / Compare
WD OVRFL RST ENA
WD OVRFL TAP SEL
RECEIVER OVERRUN
T1 MODE = 0
T1EDGE INT FLAG
T1EDGE INT FLAG
SPISIMO DATA IN
SPI SW RESET
RCVD7
SPI STEST
SDAT7
BIT 7
--
WD OVRFL INT ENA
CLOCK POLARITY
SPISIMO DATA OUT
WD INPUT SELECT2
SPI PRIORITY
T1C2 INT FLAG
T1C1 OUT ENA
SPI INT FLAG
RCVD6
SDAT6
BIT 6
--
--
Table 25. Peripheral File Frame Compilation (Continued)
WD OVRFL INT FLAG
SPISIMO FUNCTION
WD INPUT SELECT1
T1C1 INT FLAG
T1C1 INT FLAG
T1C2 OUT ENA
SPI BIT RATE2
SPI ESPEN
RCVD5
SDAT5
BIT 5
--
--
POST OFFICE BOX 1443
SPI MODULE CONTROL REGISTER
Capture/Compare Register MSbyte
Capture/Compare Register LSbyte
TIMER 1 MODULE REGISTER
Watchdog Counter MSbyte
WD INPUT SELECT0
T1 OVRFL INT ENA
Compare Register MSbyte
Watchdog Counter LSbyte
SPISIMO DATA DIR
Compare Register LSbyte
T1C1 RST ENA
SPI BIT RATE1
RCVD4
SDAT4
BIT 4
Watchdog Reset Key
T1 Counter MSbyte
T1 Counter LSbyte
--
--
--
--
--
Reserved
Reserved
Reserved
* HOUSTON, TEXAS 77251-1443
T1 OVRFL INT FLAG T1CR OUT ENA SPISOMI DATA IN SPICLK DATA IN SPI BIT RATE0 RCVD3 SDAT3 BIT 3 -- -- -- -- -- T1EDGE POLARITY SPICLK DATA OUT SPISOMI DATA OUT MASTER/ SLAVE T1 INPUT SELECT2 T1EDGE INT ENA T1EDGE INT ENA SPI CHAR2 RCVD2 SDAT2 BIT 2 -- -- SPISOMI FUNCTION SPICLK FUNCTION T1 INPUT SELECT1 T1CR RST ENA T1C2 INT ENA SPI CHAR1 RCVD1 SDAT1 BIT 1 TALK -- -- -- SPISOMI DATA DIR SPICLK DATA DIR T1 INPUT SELECT0 T1EDGE DET ENA T1C1 INT ENA T1C1 INT ENA SPI INT ENA SPI CHAR0 RCVD0 T1 SW RESET SDAT0 BIT 0 -- Bit 0 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 T1CTL3 T1CTL4 T1CTL3 T1CTL2 T1CTL1 WDRST WDCNTR T1CC T1C T1CNTR SPIPRI SPIPC2 SPIPC1 SPIDAT SPIBUF SPICTL SPICCR REG
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
53
AAAA A AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A AAA AA AA AA AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAA AAAA AAA AAAAAA AA A AA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A A AA AA AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A AA AA AA AA A AA AA AA AA A A AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A AA AA AA AA A AA AA AA AA A A AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A AAA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A AA AA AA AA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AA AA AA AA A
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
54
P05A P05B P05C P05D P04D P04C P05E P04E P05F P04F P067 P066 P065 P064 P063 P062 P061 P060 P059 P058 P057 P056 P055 P054 P053 P052 P051 P050 PF Bit 7 Bit 15 Bit 7 Bit 15 Bit 7
Bit 15
Bit 7
Bit 15
Modes: Dual-Compare and Dual-Capture
Modes: Dual-Compare and Capture / Compare
Mode: Capture/Compare (Continued)
STOP BITS
SCI STEST
T1 MODE = 1
T1 STEST
T1PWM DATA IN
SCITXD DATA IN
RX ERROR
TXRDY
BAUDF (MSB)
BAUD7
RXDT7
TXDT7
BIT 7
--
--
--
EVEN/ODD PARITY
TX EMPTY
T1PWM DATA OUT
SCITXD DATA OUT
SCITX PRIORITY
T1 PRIORITY
T1C1 OUT ENA
RXRDY
BAUDE
BAUD6
RXDT6
TXDT6
BIT 6
--
--
--
Table 25. Peripheral File Frame Compilation (Continued)
T1PWM FUNCTION
SCITXD FUNCTION
SCIRX PRIORITY
PARITY ENABLE
SCI SW RESET
BAUDD
BRKDT
BAUD5
RXDT5
TXDT5
BIT 5
--
--
--
--
--
POST OFFICE BOX 1443
SCI1 MODULE CONTROL REGISTER
Capture/Compare Register MSbyte
Capture/Compare Register LSbyte
Capture Register 2 MSbyte
T2A MODULE REGISTER
Capture Register 2 LSbyte
Compare Register MSbyte
SCITXD DATA DIR
T1PWM DATA DIR
ASYNC/ ISOSYNC
Compare Register LSbyte
T1C1 RST ENA
BAUDC
CLOCK
SCI ESPEN
BAUD4
RXDT4
TXDT4
BIT 4
T2A Counter MSbyte
T2A Counter LSbyte
FE
--
--
--
--
Reserved
Reserved
Reserved
* HOUSTON, TEXAS 77251-1443
T1EVT DATA IN ADDRESS/ IDLE WUP TXWAKE T1IC/CR DATA IN SCIRXD DATA IN SCICLK DATA IN BAUDB BAUD3 RXDT3 TXDT3 BIT 3 OE -- -- -- -- T1EVT DATA OUT SCI CHAR2 T1EDGE POLARITY SCICLK DATA OUT T1IC/CR DATA OUT SCIRXD DATA OUT BAUDA BAUD2 RXDT2 SLEEP TXDT2 BIT 2 PE -- -- -- SCI CHAR1 SCIRXD FUNCTION SCICLK FUNCTION T1EVT FUNCTION T1IC/CR FUNCTION RXWAKE TXENA BAUD1 BAUD9 RXDT1 TXDT1 BIT 1 -- -- -- -- T1EVT DATA DIR SCI CHAR0 SCICLK DATA DIR T1IC/CR DATA DIR SCIRXD DATA DIR T1EDGE DET ENA SCI RX INT ENA SCI TX INT ENA RXENA BAUD0 (LSB) BAUD8 RXDT0 TXDT0 BIT 0 -- -- Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 T2AIC T2AC BAUD LSB BAUD MSB T1PRI REG T2ACC TXBUF RXCTL TXCTL T1PC2 T1PC1 T2ACNTR SCIPRI SCIPC2 SCIPC1 RXBUF SCICTL T1CTL4 SCICCR
AAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AAAAAAAAAAAAAAAAAAAA A A AAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A A A AAA AA A AA A AAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA A AA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AAA AA A A A A A A A A AAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA A AAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A A A AAA AA A AA A AAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA A AAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA A AA A AAA AA A AA
P073 to P07C P07D P06D P06C P06C P07E P06E P06B P06B P06A P07F P06F P072 P071 P070 PF Modes: Dual-Compare and Dual-Capture Mode: Dual-Capture Mode: Dual-Compare Modes: Dual-Compare and Dual-Capture (Continued) T2AIC2 / PWM DATA IN T2A STEST T2AEDGE1 INT FLAG T2AEDGE1 INT FLAG AD STEST CONVERT START T2A MODE = 1 T2A MODE = 0 BIT 7 -- -- -- T2AIC2 / PWM DATA OUT T2AEDGE2 INT FLAG AD PRIORITY T2A PRIORITY T2AC2 INT FLAG T2AC1 OUT ENA SAMPLE START BIT 6 -- -- -- --
Table 25. Peripheral File Frame Compilation (Continued)
T2AIC2 / PWM FUNCTION
AD ESPEN
REF VOLT SELECT2
T2AC1 INT FLAG
T2AC1 INT FLAG
T2AC2 OUT ENA
BIT 5
--
--
--
--
--
POST OFFICE BOX 1443
ADC1 MODULE CONTROL REGISTER
A-to-D Conversion Data Register
Port E Input Enable Register
Port E Data Input Register
T2AIC2 / PWM DATA DIR
T2A OVRFLINT ENA
REF VOLT SELECT1
T2AC1 RST ENA
T2AC1 RST ENA
BIT 4
--
--
--
--
--
--
Reserved
* HOUSTON, TEXAS 77251-1443
T2A OVRFL INT FLAG T2AEDGE2 POLARITY T2AEDGE1 OUT ENA T2AIC1/CR DATA IN REF VOLT SELECT0 T2AEVT DATA IN BIT 3 -- -- -- -- -- T2AEDGE1 POLARITY T2AEDGE1 INT ENA T2AEDGE1 POLARITY T2AEDGE1 INT ENA AD READY T2AIC1/CR DATA OUT T2AEVT DATA OUT AD INPUT SELECT2 T2A INPUT SELECT1 BIT 2 -- -- T2AEDGE2 DET ENA T2AEDGE2 INT ENA T2AEDGE1 RST ENA T2AIC1/CR FUNCTION T2AEVT FUNCTION T2A INPUT SELECT0 AD INPUT SELECT1 T2AC2 INT ENA AD INT FLAG BIT 1 -- -- AD INT ENA T2AEDGE1 DET ENA T2AEDGE1 DET ENA T2AIC1/CR DATA DIR AD INPUT SELECT0 T2AEVT DATA DIR T2AC1 INT ENA T2AC1 INT ENA T2A SW RESET BIT 0 -- -- ADPRI ADENA ADIN ADDATA ADSTAT ADCTL T2APRI T2APC2 T2APC1 T2ACTL3 T2ACTL2 T2ACTL3 T2ACTL2 T2ACTL1 REG
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
TMS370Cx5x 8-BIT MICROCONTROLLER
55
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range,VCC1, VCC2, VCC3 (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 14 V Input clamp current, IIK (VI < 0 or VI > VCC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current per buffer, IO (VO = 0 to VCC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Maximum ICC current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA Maximum ISS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 170 mA Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature range, TA: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 105C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. VCC1 = VCC Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers. NOTE 2: Unless otherwise noted, all voltage values are with respect to VSS1.
recommended operating conditions
MIN VCC1 VCC2 VCC3 VSS2 VSS3 VIL Supply voltage (see Note 2) RAM data-retention supply voltage (see Note 3) Digital I/O supply voltage (see Note 2) Analog supply voltage (see Note 2) Digital I/O supply ground Analog supply ground Low-level Low level input voltage All pins except MC MC, normal operation All pins except MC, XTAL2 / CLKIN, and RESET VIH High-level input voltage g g MC (non-WPO mode) XTAL2 / CLKIN RESET EEPROM write protect override (WPO) VMC MC ( (mode control) voltage ) g (see Note 4) EPROM programming voltage (VPP) Microprocessor Microcomputer L version TA Operating free-air temperature A version T version 4.5 3 4.5 4.5 - 0.3 - 0.3 VSS1 VSS1 2 VCC1 - 0.3 0.8 VCC1 0.7 VCC1 11.7 13 VCC1 - 0.3 VSS1 0 - 40 - 40 12 13.2 5 5 0 0 NOM 5 MAX 5.5 5.5 5.5 5.5 0.3 0.3 0.8 0.3 VCC1 VCC1 + 0.3 VCC1 VCC1 13 13.5 VCC1 + 0.3 0.3 70 85 105 C V V UNIT V V V V V V
NOTES: 2. Unless otherwise noted, all voltage values are with respect to VSS1. 3. RESET must be externally activated when VCC1 or SYSCLK is not within the recommended operating range. 4. The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin two system-clock cycles (tc) before RESET goes inactive (high). The WPO mode can be selected anytime a sufficient voltage is present on MC.
electrical characteristics over recommended operating free-air temperature range (unless
56
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
otherwise noted)
PARAMETER VOL VOH Low-level output voltage (see Note 5) High level output voltage High-level TEST CONDITIONS IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA 0 V < VI 0.3 V 0.3 V < VI < VCC1-0.3 V II Input current MC VCC1-0.3 V VI VCC 1+ 0.3 V VCC1 + 0.3 V < VI 13 V 12 V VI 13 V I / O pins IOL IOH Low-level output current (see Note 5) High-level High level output current TMS370Cx50A TMS370Cx52A TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B TMS370Cx50A TMS370Cx52A TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B TMS370Cx59A ICC S l t Supply current (operating mode) OSC POWER bit = 0 (see Note 9) TMS370Cx50A TMS370Cx52A TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B TMS370Cx59A SYSCLK = 0.5 MHz See Notes 7 and 8 SYSCLK = 3 MHz See Notes 7 and 8 SYSCLK = 5 MHz See Notes 7 and 8 35 56 0 V VI VCC1 VOL = 0.4 V VOH = 0.9 VCC1 VOH = 2.4 V 1.4 - 50 -2 30 45 See Note 6 MIN 0.9 VCC1 2.4 10 50 10 650 50 10 mA A mA A mA A TYP MAX 0.4 UNIT V V
Supply current (operating mode) ( i d) OSC POWER bit = 0 (see Note 9)
20
30
mA
25
36
46 5
55 11
13
18
mA
22 SYSCLK = 5 MHz, See Notes 7 and 8 See Notes 7 and 8 See Notes 7 and 8 See Notes 7 and 8 See Notes 7 and 8 12 8 2.5 6 2 SYSCLK = 3 MHz, SYSCLK = 0.5 MHz, SYSCLK = 3 MHz, SYSCLK = 0.5 MHz,
28 17 11 3.5 8.6 3 mA mA
Supply current (STANDBY mode) S l t d) OSC POWER bit = 0 (see Note 10) Supply current (STANDBY mode) y ( ) OSC POWER bit = 1 (see Note 11)
Supply current (HALT mode) XTAL2 / CLKIN < 0.2 V, See Note 7 2 30 A TMS370Cx59 only operate up to 3 MHz SYSCLK NOTES: 5. In prior versions of the TMS370 family, the IOL current was equal to 2 mA for ports A, B, C, and D and the RESET pin. 6. Input current IPP is a maximum of 50 mA only when the EPROM is being programmed. 7. Single chip mode, ports configured as inputs or outputs with no load. All inputs 0.2 V or VCC - 0.2V. 8. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 9. Maximum operating current for TMS370Cx50A and TMS370Cx52A = 7.6 (SYSCLK) + 7 mA. Maximum operating current for TMS370Cx53A, TMS370Cx56A, TMS370Cx58A, and TMS370Cx58B = 10 (SYSCLK) + 5.8 mA. 10. Maximum standby current for TMS370Cx5xA = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0). 11. Maximum standby current for TMS370Cx5xA and TMS370Cx5xB = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, valid only up to 3 MHz of SYSCLK.)
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
57
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
XTAL2/CLKIN
XTAL1
XTAL2/CLKIN
XTAL1 C3 (see Note B)
C1 (see Note B)
Crystal/Ceramic Resonator (see Note A)
C2 (see Note B)
External Clock Signal
NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period. B. The values of C1 and C2 are typically 15 pF and C3 is typically 50 pF. See the manufacturer's recommendations for ceramic resonators.
Figure 19. Recommended Crystal/Clock Connections
Load Voltage 1.2 k VO 20 pF
Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.
Figure 20. Typical Output Load Circuit (see Note A)
VCC VCC
300 30 I/O 20
Pin Data Output Enable
6 k INT1 20
GND
GND
Figure 21. Typlcal Buffer Circuitry
58
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: A AR B CI D E FE IE M PGM R Address Array Byte XTAL2/CLKIN Data EDS Final Initial Master mode Program Read RXD S SC SCC SIMO SOMI SPC TXD W WT SCIRXD Slave mode SYSCLK SCICLK SPISIMO SPISOMI SPICLK SCITXD Write WAIT
Lowercase subscripts and their meanings are: c d f h cycle time (period) delay time fall time hold time r su v w rise time setup time valid time pulse duration (width)
The following additional letters are defined as follows: H L V Z High Low Valid High impedance
All timings are measured between high and low measurement points as indicated in Figure 22 and Figure 23.
0.8 VCC V (High) 0.8 V (Low)
2 V (High) 0.8 V (Low)
Figure 22. XTAL2/CLKIN Measurement Points
Figure 23. General Measurement Points
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
59
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
external clocking requirements for clock divided by 4
NO. 1 2 3 4 tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency System clock 2 PARAMETER Pulse duration, XTAL2/CLKIN (see Note 12) MIN 20 30 30 100 20 MAX UNIT ns ns ns ns MHz
SYSCLK 0.5 5 MHz For VIL and VIH, refer to recommended operating conditions. 'x59A operates up to 12 MHz CLKIN 'x59A operates up to 3 MHz SYSCLK SYSCLK = CLKIN/4 NOTE 12: This pulse can be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 1 XTAL2/CLKIN 2 3 4 SYSCLK
Figure 24. External Clock Timing for Divide-by-4
external clocking requirements for clock divided by 1 (PLL)
NO. 1 2 3 4 tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN# SYSCLK Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency System clock|| 2 2 PARAMETER Pulse duration, XTAL2/CLKIN (see Note 12) MIN 20 30 30 100 5 5 MAX UNIT ns ns ns ns MHz
MHz For VIL and VIH, refer to recommended operating conditions. 'x59A operates up to 3 MHz SYSCLK # 'x59A operates up to 3 MHz CLKIN (for divide-by-1 clock option) || SYSCLK = CLKIN/1 NOTE 12: This pulse can be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 1 XTAL2/CLKIN 2 3 4 SYSCLK
Figure 25. External Clock Timing for Divide-by-1
60
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
general purpose output signal-switching time requirements
MIN tr tf Rise time Fall time NOM 30 30 MAX UNIT ns ns
tr tf
Figure 26. Signal-Switching Timing
recommended EEPROM timing requirements for programming
MIN tw(PGM)B tw(PGM)AR Pulse duration, programming signal to ensure valid data is stored (byte mode) Pulse duration, programming signal to ensure valid data is stored (array mode) 10 20 MAX UNIT ms ms
recommended EPROM operating conditions for programming
MIN VCC1 VPP IPP SYSCLK Supply voltage Supply voltage at MC pin Supply current at MC pin during programming (VPP = 13 V) System clock Divide-by-4 Divide-by-1 0.5 2 4.75 13 NOM 5.5 13.2 30 MAX 6 13.5 50 5 5 UNIT V V mA MHz
recommended EPROM timing requirements for programming
MIN tw(EPGM) Pulse duration, programming signal (see Note 13) NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set. 0.40 NOM 0.50 MAX 3 UNIT ms
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
61
TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
switching characteristics and timing requirements for external read and write (see Figure 27 and Figure 28)
NO. 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 tc tw(SCL) tw(SCH) td(SCL-A) tv(A) tsu(D) th(EH-A) th(EH-D)W td(DZ-EL) td(EH-D) td(EL-DV)R th(EH-D)R tsu(WT-SCH) th(SCH-WT) td(EL-WTV) tw td(AV-DV)R td(AV-WTV) PARAMETER Cycle time, SYSCLK (system clock) time Pulse duration, SYSCLK low Pulse duration, SYSCLK high Delay time, SYSCLK low to address R / W and OCF valid Valid time, address to EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF low Setup time, write data time to EDS high Hold time, address, R / W and OCF from EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF high Hold time, write data time from EDS high Delay time, data bus high impedance to EDS low (read cycle) Delay time, EDS high to data bus enable (read cycle) Delay time, EDS low to read data valid Hold time, read time from EDS high Setup time, WAIT time to SYSCLK high Hold time, WAIT time from SYSCLK high Delay time, EDS low to WAIT valid Pulse duration, EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF low Delay time, address valid to read data valid Delay time, address valid to WAIT valid 1.5tc-85 tc-80 0 0.25tc+70 0 0.5tc-60 tc+40 1.5tc-115 tc-115 0.5tc-90 0.75tc-80 0.5tc-60 0.75tc+15 0.25tc-35 1.25tc-40 tc-95 Divide-by-4 clock Divide-by-1 PLL MIN 200 200 0.5tc-25 0.5tc MAX 2 000 500 0.5tc 0.5tc+20 0.25tc+75 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
23 td(AV-EH) Delay time, address valid to EDS high (end of write) ns tc = system-clock cycle time = 1 / SYSCLK If wait states, PFWait, or the autowait feature is used, add tc to this value for each wait state invoked. If the autowait feature is enabled, the WAIT input can assume a "don't care" condition until the third cycle of the access. The WAIT signal must be synchronized with the high pulse of the SYSCLK signal while still conforming to the minimum setup time.
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
7 5 6 SYSCLK
8
ADDRESS
11 EDS, CSE1, CSE2, CSH1, CSH2, CSH3, CSPF 9 21 13 15 Read Data Valid Read Data Disable 370 Drives Data 20 14
16
DATA
370 Drives Data
Read Data Drive 19 22
17 18
WAIT
R/W
OCF
Figure 27. Switching Characteristics and Timing Requirements for External-Read
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
7 5 6 SYSCLK
8
ADDRESS
11 20 EDS, CSE1, CSE2, CSH1, CSH2, CSH3, CSPF 9 10 23 12 DATA 19 22 17 18 WAIT
R/W
Figure 28. Switching Characteristics and Timing Requirements for External-Write
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
SCI1 isosynchronous mode timing characteristics and requirements for internal clock (see Note 14 and Figure 29)
NO. 24 25 26 27 28 29 30 tc(SCC) tw(SCCL) tw(SCCH) td(SCCL-TXDV) tv(SCCH-TXD) tsu(RXD-SCCH) Cycle time, SCICLK Pulse duration, SCICLK low Pulse duration, SCICLK high Delay time, SCITXD valid after SCICLK low Valid time, SCITXD data valid after SCICLK high Setup time, SCIRXD to SCICLK high MIN 2tc tc - 45 tc - 45 - 50 tw(SCCH) - 50 0.25 tc + 145 0 MAX 131 072tc 0.5tc(SCC)+45 0.5tc(SCC)+45 60 UNIT ns ns ns ns ns ns ns
tv(SCCH-RXD) Valid time, SCIRXD data valid after SCICLK high NOTE 14: tc = system-clock cycle time = 1 / SYSCLK 24 26 25 SCICLK 28 27 SCITXD 29 30 SCIRXD Data Valid Data Valid
Figure 29. SCI1 Isosynchronous Mode Timing for Internal Clock
Isosynchronous = Isochronous
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
SCI1 isosynchronous mode timing characteristics and requirements for external clock (see Note 14 and Figure 30)
NO. 31 32 33 34 35 36 37 tc(SCC) tw(SCCL) tw(SCCH) td(SCCL-TXDV) tv(SCCH-TXD) tsu(RXD-SCCH) Cycle time, SCICLK Pulse duration, SCICLK low Pulse duration, SCICLK high Delay time, SCITXD valid after SCICLK low Valid time, SCITXD data valid after SCICLK high Setup time, SCIRXD to SCICLK high tw(SCCH) 40 2tc MIN 10tc 4.25tc + 120 tc + 120 4.25tc + 145 MAX UNIT ns ns ns ns ns ns ns
tv(SCCH-RXD) Valid time, SCIRXD data after SCICLK high NOTE 14: tc = system-clock cycle time = 1 / SYSCLK 31 33 32 SCICLK 35 34 SCITXD 36 37 SCIRXD Data Valid Data Valid
Figure 30. SCI1 Isosynchronous Timing for External Clock
Isosynchronous = Isochronous
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
SPI master mode external timing characteristics and requirements (see Note 14 and Figure 31)
NO. 38 39 40 41 42 43 44 tc(SPC)M tw(SPCL)M tw(SPCH)M td(SPCL-SIMOV)M tv(SPCH-SIMO)M tsu(SOMI-SPCH)M tv(SPCH-SOMI)M Cycle time, SPICLK Pulse duration, SPICLK low Pulse duration, SPICLK high Delay time, SPISIMO valid after SPICLK low (polarity = 1) Valid time, SPISIMO data valid after SPICLK high (polarity =1) Setup time, SPISOMI to SPICLK high (polarity = 1) Valid time, SPISOMI data valid after SPICLK high (polarity = 1) MIN 2tc tc - 45 tc - 55 - 65 tw(SPCH) - 50 0.25 tc + 150 0 MAX 256tc 0.5tc(SPC)+45 0.5tc(SPC)+45 50 UNIT ns ns ns ns ns ns ns
NOTE 14: tc = system-clock cycle time = 1 / SYSCLK
38 40 39 SPICLK 41 SPISIMO 43 44 SPISOMI Data Valid Data Valid 42
NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0.
Figure 31. SPI Master External Timing
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SPI slave mode external timing characteristics and requirements (see Note 14 and Figure 32)
NO. 45 46 47 48 49 50 tc(SPC)S tw(SPCL)S tw(SPCH)S td(SPCL-SOMIV)S tv(SPCH-SOMI)S tsu(SIMO-SPCH)S Cycle time, SPICLK Pulse duration, SPICLK low Pulse duration, SPICLK high Delay time, SPISOMI valid after SPICLK low (polarity = 1) Valid time, SPISOMI data valid after SPICLK high (polarity =1) Setup time, SPISIMO to SPICLK high (polarity = 1) tw(SPCH)S 0 3tc + 100 MIN 8tc 4tc - 45 4tc - 45 MAX 0.5tc(SPC)S+45 0.5tc(SPC)S+45 3.25tc + 130 UNIT ns ns ns ns ns ns ns
51 tv(SPCH-SIMO)S Valid time, SPISIMO data after SPICLK high (polarity = 1) NOTE 14: tc = system-clock cycle time = 1 / SYSCLK
45 47 46 SPICLK 48 SPISIMO 50 51 SPISOMI Data Valid Data Valid 49
NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0.
Figure 32. SPI-Slave External Timing
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
The ADC1 has a separate power bus for its analog circuitry. These pins are referred to as VCC3 and VSS3 . The purpose is to enhance ADC1 performance by preventing digital switching noise of the logic circuitry that can be present on VSS1 and VCC1 from coupling into the ADC1 analog stage. All ADC1 specifications are given with respect to VSS3 unless otherwise noted. Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bits (256 values) Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yes Output conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00h to FFh (00 for VI VSS3 ; FF for VI Vref) Conversion time (excluding sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 tc
recommended operating conditions
MIN VCC3 VSS3 Vref Analog supply voltage Analog ground Non-VCC3 reference Analog input for conversion 4.5 VCC1-0.3 VSS1-0.3 2.5 VCC3 NOM 5 MAX 5.5 VCC1 + 0.3 VSS1+0.3 VCC3 + 0.1 Vref UNIT V V V V
VSS3 Vref must be stable, within 1/2 LSB of the required resolution, during the entire conversion time.
operating characteristics over recommended ranges operating conditions
PARAMETER Absolute accuracy Differential/integral linearity error ICC3 II Zref f Analog supply current Input current, AN0 - AN7 Iref input charge current Source impedance of Vref f SYSCLK 3 MHz 3 MHz < SYSCLK 5 MHz VCC3 = 5.5 V VCC3 = 5.5 V Converting Nonconverting 0 V VI 5.5 V Vref = 5.1 V Vref = 5.1 V MIN MAX 1.5 0.9 2 5 2 1 24 10 UNIT LSB LSB mA A A mA k
k Absolute resolution = 20 mV. At Vref = 5 V, this is one LSB. As Vref decreases, LSB size decreases; therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase. Excluding quantization error of 1/2 LSB
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TMS370Cx5x 8-BIT MICROCONTROLLER
SPNS010F - DECEMBER 1986 - REVISED FEBRUARY 1997
The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the sample time is user-defined so that the high-impedance can be accommodated without penalty to the low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC1 control register (ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START, ADCTL.7) is set to 1. After a hold time, the converter will reset the SAMPLE START and CONVERT START bits, signaling that a conversion has started and that the analog signal can be removed.
analog timing requirements
MIN tsu(S) th(AN) Setup time, analog to sample command 0 MAX UNIT ns
Hold time, analog input from start of conversion 18tc ns tw(S) Pulse duration, sample time per kilohm of source impedance 1 s/k The value given is valid for a signal with a source impedance > 1 k. If the source impedance is < 1 k, use a minimum sampling time of 1s.
Analog Stable
Analog In
tsu(S)
Sample Start th(AN) tw(S) Convert Start
Figure 33. Analog Timing
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TMS370Cx5x 8-BIT MICROCONTROLLER
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Table 26 is designed to aid the user in referencing a device part number to a mechanical drawing. The table shows a cross-reference of the device part number to the TMS370 generic package name and the associated mechanical drawing by drawing number and name. Table 26. TMS370Cx5x Family Package Type and Mechanical Cross-Reference
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PKG TYPE (mil pin spacing) TMS370 GENERIC NAME PKG TYPE NO. AND MECHANICAL NAME DEVICE PART NUMBERS FN - 68 pin (50-mil pin spacing) PLASTIC LEADED CHIP CARRIER (PLCC) FN(S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER TMS370C050AFNA TMS370C050AFNL TMS370C050AFNT TMS370C150AFNT TMS370C250AFNT TMS370C350AFNA TMS370C350AFNL TMS370C350AFNT TMS370C052AFNA TMS370C052AFNL TMS370C052AFNT TMS370C352AFNA TMS370C352AFNL TMS370C352AFNT TMS370C452AFNA TMS370C452AFNL TMS370C452AFNT TMS370C353AFNA TMS370C353AFNL TMS370C353AFNT TMS370C056AFNA TMS370C056AFNL TMS370C056AFNT TMS370C156AFNT TMS370C256AFNT TMS370C356AFNA TMS370C356AFNL TMS370C356AFNT TMS370C456AFNA TMS370C456AFNL TMS370C456AFNT TMS370C756AFNT TMS370C058AFNA TMS370C058AFNL TMS370C058AFNT TMS370C358AFNA TMS370C358AFNL TMS370C358AFNT TMS370C758AFNT TMS370C758BFNT TMS370C059AFNA TMS370C059AFNL TMS370C059AFNT TMS370C759AFNT SE370C756AFZT SE370C758AFZT SE370C758BFZT SE370C759AFZT SE370C756AJNT SE370C758AJNT SE370C758BJNT FZ - 68 pin (50-mil pin spacing) CERAMIC LEADED CHIP CARRIER (CLCC) FZ(S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER JN - 64 pin (70-mil pin spacing) CERAMIC SHRINK DUAL-IN-LINE PACKAGE (CSDIP) JN(R-CDIP-T64) CERAMIC DUAL-IN-LINE PACKAGE
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Table 26. TMS370Cx5x Family Package Type and Mechanical Cross-Reference (Continued)
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PKG TYPE (mil pin spacing) TMS370 GENERIC NAME PKG TYPE NO. AND MECHANICAL NAME DEVICE PART NUMBERS NM - 64 pin (70-mil pin spacing) PLASTIC SHRINK DUAL-IN-LINE PACKAGE (PSDIP) NM(R-PDIP-T64) PLASTIC SHRINK DUAL-IN-LINE PACKAGE TMS370C050ANMA TMS370C050ANML TMS370C050ANMT TMS370C350ANMA TMS370C350ANML TMS370C350ANMT TMS370C052ANMA TMS370C052ANML TMS370C052ANMT TMS370C352ANMA TMS370C352ANML TMS370C352ANMT TMS370C056ANMA TMS370C056ANML TMS370C056ANMT TMS370C356ANMA TMS370C356ANML TMS370C356ANMT TMS370C756ANMT TMS370C058ANMA TMS370C058ANML TMS370C058ANMT TMS370C358ANMA TMS370C358ANML TMS370C358ANMT TMS370C758ANMT TMS370C758BNMT 72
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MECHANICAL DATA
FN (S-PQCC-J**)
20 PIN SHOWN Seating Plane 0.004 (0,10) D D1 3 1 19 0.032 (0,81) 0.026 (0,66) 4 18 D2 / E2 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) 0.020 (0,51) MIN
PLASTIC J-LEADED CHIP CARRIER
E
E1 D2 / E2 8 14
0.050 (1,27) 9 13 0.008 (0,20) NOM
0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M
NO. OF PINS ** 20 28 44 52 68 84
D/E MIN 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 0.785 (19,94) 0.985 (25,02) 1.185 (30,10) MAX 0.395 (10,03) 0.495 (12,57) 0.695 (17,65) 0.795 (20,19) 0.995 (25,27) 1.195 (30,35) MIN
D1 / E1 MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.756 (19,20) 0.958 (24,33) 1.158 (29,41) MIN
D2 / E2 MAX 0.169 (4,29) 0.219 (5,56) 0.319 (8,10) 0.369 (9,37) 0.469 (11,91) 0.569 (14,45) 4040005 / B 03/95
0.350 (8,89) 0.450 (11,43) 0.650 (16,51) 0.750 (19,05) 0.950 (24,13) 1.150 (29,21)
0.141 (3,58) 0.191 (4,85) 0.291 (7,39) 0.341 (8,66) 0.441 (11,20) 0.541 (13,74)
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018
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MECHANICAL DATA
FZ (S-CQCC-J**)
28 LEAD SHOWN 0.040 (1,02)
J-LEADED CERAMIC CHIP CARRIER
45
A B 4 1 26 0.180 (4,57) 0.155 (3,94) 0.140 (3,55) 0.120 (3,05)
Seating Plane
5
25
0.050 (1,27)
A
B
0.032 (0,81) 0.026 (0,66)
C (at Seating Plane) 0.020 (0,51) 0.014 (0,36)
11
19
12
18 0.025 (0,64) R TYP 0.040 (1,02) MIN 0.120 (3,05) 0.090 (2,29) A MIN 0.485 (12,32) 0.685 (17,40) 0.785 (19,94) 0.985 (25,02) MAX 0.495 (12,57) 0.695 (17,65) 0.795 (20,19) 0.995 (25,27) MIN 0.430 (10,92) 0.630 (16,00) 0.730 (18,54) 0.930 (23,62) B MAX 0.455 (11,56) 0.655 (16,64) 0.765 (19,43) 0.955 (24,26) MIN 0.410 (10,41) 0.610 (15,49) 0.680 (17,28) 0.910 (23,11) C MAX 0.430 (10,92) 0.630 (16,00) 0.740 (18,79) 0.930 (23,62)
JEDEC OUTLINE MO-087AA MO-087AB MO-087AC MO-087AD
NO. OF PINS** 28 44 52 68
4040219 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit.
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MECHANICAL DATA
JN (R-CDIP-T64)
2.424 (61,57) 2.376 (60,35) 64 33
CERAMIC DUAL-IN-LINE PACKAGE
0.750 (19,05) 0.730 (18,54)
1 0.040 (1,02) TYP
32
0.094 (2,39) 0.078 (1,98) 0.060 (1,52) 0.040 (1,02) 0.760 (19,30) 0.740 (18,80)
Seating Plane 0.088 (2,24) 0.072 (1,83) 0.020 (0,51) 0.016 (0,41) 0.070 (1,78) See Note C 2.178 (55,32) 2.162 (54,91) 4040224/A 09/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Each pin centerline located within 0.010 (0,26) of it true longitudinal position. 0.175 (4,45) TYP 0.012 (0,31) 0.009 (0,23)
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MECHANICAL DATA
NM (R-PDIP-T64)
2.280 (57,91) MAX 64 33
PLASTIC SHRINK DUAL-IN-LINE PACKAGE
0.680 (17,27) 0.670 (17,02)
1 0.048 (1,216) 0.032 (0,816)
32
0.222 (5,64) MAX 0.020 (0,51) MIN 0.760 (19,30) 0.740 (18,80)
Seating Plane
0.070 (1,78) 0.022 (0,56) 0.014 (0,36) 0.010 (0,25) M
0.125 (3,18) MIN
0- 15 0.010 (0,25) NOM 4040056 / B 05/95
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
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