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| User's Manual PD789860, 789861 Subseries 8-Bit Single-Chip Microcontrollers PD789860 PD78E9860A PD789861 PD78E9861A Document No. U14826EJ4V0UD00 (4th edition) Date Published September 2003 N CP(K) (c) Printed in Japan 2000, 2003 [MEMO] 2 User's Manual U14826EJ4V0UD NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. FIP and EEPROM are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. User's Manual U14826EJ4V0UD 3 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of March, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U14826EJ4V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 J03.4 User's Manual U14826EJ4V0UD 5 Major Revisions in This Edition Pages pp. 23, 30 Description CHAPTER 1 GENERAL (PD789860 SUBSERIES) CHAPTER 2 GENERAL (PD789861 SUBSERIES) * Update of 1.5 78K/0S Series Lineup and 2.5 78K/0S Series Lineup to latest version p. 37 CHAPTER 3 PIN FUNCTIONS * Modification of description of 3.2.9 VPP (PD78E9860A, 78E9861A only) CHAPTER 9 8-BIT TIMERS 30 AND 40 * Addition of description of timer input of P21 to 9.3 (4) Port mode register 2 (PM2) CHAPTER 11 POWER-ON-CLEAR CIRCUITS * Modification of Figure 11-1 Block Diagram of Power-on-Clear Circuit and Figure 11-2 Block Diagram of Low-Voltage Detection Circuit * Addition of Caution to 11.4.2 Operation of low-voltage detection (LVI) circuit * Modification of Figure 11-9 LVI Circuit Operation Timing p. 133 CHAPTER 12 BIT SEQUENTIAL BUFFER * Addition of 12.3 (2) Port mode register 2 (PM2) CHAPTER 17 PD78E9860A, 78E9861A * Addition of description of power supply voltage and OSTS oscillation stabilization time to Table 17-1 Differences Between PD78E9860A, 78E9861A and Mask ROM Versions p. 180 p. 195 Addition of CHAPTER 20 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 21 EXAMPLE OF RC OSCILLATION FREQUENCY CHARACTERISTICS (REFERENCE VALUES) p. 196 p. 197 p. 205 Addition of CHAPTER 22 PACKAGE DRAWING Addition of CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN p. 92 pp. 125, 130, 131 p. 159 The mark shows major revised points. 6 User's Manual U14826EJ4V0UD INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the PD789860, 789861 Subseries in order to design and develop its application systems and programs. The target devices are the following subseries products. * PD789860 Subseries: PD789860, 78E9860A * PD789861 Subseries: PD789861, 78E9861A The system clock oscillation frequency of the ceramic/crystal oscillation (PD789860 Subseries) is described as fX and the system clock oscillation frequency of the RC oscillation (PD789861 Subseries) is described as fCC. Purpose This manual is intended to give users on understanding of the functions described in the Organization below. Organization Two manuals are available for the PD789860, 789861 Subseries: this manual and the Instruction Manual (common to the 78K/0S Series). PD789860, 789861 Subseries User's Manual * Pin functions * Internal block functions * Interrupts * Other internal peripheral functions * Electrical specifications How to Use This Manual 78K/0S Series Instructions User's Manual * CPU function * Instruction set * Instruction description It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of the PD789860, 789861 Subseries Read this manual in the order of the CONTENTS. How to read register formats The name of a bit whose number is enclosed with <> is reserved in the assembler and is defined in the C compiler by the header file sfrbit.h. To learn the detailed functions of a register whose register name is known See APPENDIX C REGISTER INDEX. To learn the details of the instruction functions of the 78K/0S Series Refer to 78K/0S Series Instructions User's Manual (U11047E) separately available. To learn the electrical specifications of the PD789860, 789861 Subseries See CHAPTER 20 ELECTRICAL SPECIFICATIONS. User's Manual U14826EJ4V0UD 7 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Caution: Footnote for item marked with Note in the text Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. This manual U11047E PD789860, 789861 Subseries User's Manual 78K/0S Series Instructions User's Manual Documents Related to Development Software Tools (User's Manuals) Document Name RA78K0S Assembler Package Operation Language Structured Assembly Language CC78K0S C Compiler Operation Language SM78K Series System Simulator Ver. 2.30 or Later Operation (Windows TM Document No. U14876E U14877E U11623E U14871E U14872E Based) U15373E U15802E U15185E U14610E External Part User Open Interface Specification ID78K Series Integrated Debugger Ver. 2.30 or Later Project Manager Ver. 3.12 or Later (Windows Based) Operation (Windows Based) Documents Related to Development Hardware Tools (User's Manuals) Document Name IE-78K0S-NS In-Circuit Emulator IE-78K0S-NS-A In-Circuit Emulator IE-789860-NS-EM1 Emulation Board Document No. U13549E U15207E U16499E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 8 User's Manual U14826EJ4V0UD Documents Related to EEPROM (Program Memory) Writing Document Name PG-FP3 Flash Memory Programmer User's Manual PG-FP4 Flash Memory Programmer User's Manual Document No. U13502E U15260E Other Related Documents Document Name SEMICONDUCTOR SELECTION GUIDE - Products and Packages Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X Note C11531E C10983E C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. User's Manual U14826EJ4V0UD 9 CONTENTS CHAPTER 1 GENERAL (PD789860 SUBSERIES)............................................................................21 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features ......................................................................................................................................21 Applications................................................................................................................................21 Ordering Information .................................................................................................................21 Pin Configuration (Top View)....................................................................................................22 78K/0S Series Lineup.................................................................................................................23 Block Diagram ............................................................................................................................26 Overview of Functions...............................................................................................................27 CHAPTER 2 GENERAL (PD789861 SUBSERIES)............................................................................28 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Features ......................................................................................................................................28 Applications................................................................................................................................28 Ordering Information .................................................................................................................28 Pin Configuration (Top View)....................................................................................................29 78K/0S Series Lineup.................................................................................................................30 Block Diagram ............................................................................................................................33 Overview of Functions...............................................................................................................34 CHAPTER 3 PIN FUNCTIONS ...............................................................................................................35 3.1 3.2 Pin Function List ........................................................................................................................35 Description of Pin Functions ....................................................................................................36 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 P00 to P07 (Port 0)......................................................................................................................36 P20, P21 (Port 2).........................................................................................................................36 P40 to P43 (Port 4)......................................................................................................................36 RESET ........................................................................................................................................36 X1, X2 (PD789860 Subseries)...................................................................................................36 CL1, CL2 (PD789861 Subseries) ..............................................................................................36 VDD...............................................................................................................................................37 VSS...............................................................................................................................................37 VPP (PD78E9860A, 78E9861A only)..........................................................................................37 IC (mask ROM version only)........................................................................................................37 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................38 CHAPTER 4 CPU ARCHITECTURE ......................................................................................................39 4.1 Memory Space ............................................................................................................................39 4.1.1 4.1.2 4.1.3 4.1.4 Internal program memory space..................................................................................................41 Internal data memory space ........................................................................................................41 Special function register (SFR) area............................................................................................42 Data memory addressing.............................................................................................................42 Control registers ..........................................................................................................................44 User's Manual U14826EJ4V0UD 4.2 Processor Registers ..................................................................................................................44 4.2.1 10 4.2.2 4.2.3 General-purpose registers........................................................................................................... 46 Special function registers (SFRs) ................................................................................................ 47 Relative addressing..................................................................................................................... 49 Immediate addressing ................................................................................................................. 50 Table indirect addressing ............................................................................................................ 50 Register addressing .................................................................................................................... 51 Direct addressing ........................................................................................................................ 52 Short direct addressing ............................................................................................................... 53 Special function register (SFR) addressing ................................................................................. 54 Register addressing .................................................................................................................... 55 Register indirect addressing ........................................................................................................ 56 Based addressing........................................................................................................................ 57 Stack addressing......................................................................................................................... 57 4.3 Instruction Address Addressing .............................................................................................. 49 4.3.1 4.3.2 4.3.3 4.3.4 4.4 Operand Address Addressing.................................................................................................. 52 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 CHAPTER 5 EEPROM (DATA MEMORY)............................................................................................ 58 5.1 5.2 5.3 5.4 Memory Space............................................................................................................................ 58 EEPROM Configuration............................................................................................................. 58 EEPROM Control Register ........................................................................................................ 58 Notes for EEPROM Writing ....................................................................................................... 61 CHAPTER 6 PORT FUNCTIONS........................................................................................................... 63 6.1 6.2 Port Functions............................................................................................................................ 63 Port Configuration ..................................................................................................................... 63 6.2.1 6.2.2 6.2.3 Port 0........................................................................................................................................... 64 Port 2........................................................................................................................................... 65 Port 4........................................................................................................................................... 66 6.3 6.4 Port Function Control Registers .............................................................................................. 67 Operation of Port Functions ..................................................................................................... 68 6.4.1 6.4.2 6.4.3 Writing to I/O port ........................................................................................................................ 68 Reading from I/O port.................................................................................................................. 68 Arithmetic operation of I/O port.................................................................................................... 68 CHAPTER 7 CLOCK GENERATOR (PD789860 SUBSERIES) ....................................................... 69 7.1 7.2 7.3 7.4 Clock Generator Functions....................................................................................................... 69 Clock Generator Configuration ................................................................................................ 69 Clock Generator Control Register............................................................................................ 70 System Clock Oscillators.......................................................................................................... 71 7.4.1 7.4.2 7.4.3 System clock oscillator ................................................................................................................ 71 Examples of incorrect resonator connection................................................................................ 72 Frequency divider........................................................................................................................ 73 7.5 7.6 Clock Generator Operation....................................................................................................... 74 Changing Setting of CPU Clock ............................................................................................... 75 7.6.1 Time required for switching CPU clock........................................................................................ 75 User's Manual U14826EJ4V0UD 11 7.6.2 Switching CPU clock ...................................................................................................................75 CHAPTER 8 CLOCK GENERATOR (PD789861 SUBSERIES) .......................................................76 8.1 8.2 8.3 8.4 Clock Generator Functions .......................................................................................................76 Clock Generator Configuration ................................................................................................76 Clock Generator Control Register............................................................................................77 System Clock Oscillators ..........................................................................................................78 8.4.1 8.4.2 8.4.3 System clock oscillator ................................................................................................................78 Examples of incorrect resonator connection................................................................................79 Frequency divider ........................................................................................................................80 8.5 8.6 Clock Generator Operation .......................................................................................................81 Changing Setting of CPU Clock................................................................................................82 8.6.1 8.6.2 Time required for switching CPU clock ........................................................................................82 Switching CPU clock ...................................................................................................................82 CHAPTER 9 8-BIT TIMERS 30 AND 40..............................................................................................83 9.1 9.2 9.3 9.4 8-Bit Timers 30, 40 Functions ...................................................................................................83 8-Bit Timers 30, 40 Configuration.............................................................................................84 8-Bit Timers 30, 40 Control Registers ......................................................................................88 8-Bit Timers 30, 40 Operation ...................................................................................................93 9.4.1 9.4.2 9.4.3 9.4.4 Operation as 8-bit timer counter ..................................................................................................93 Operation as 16-bit timer counter ..............................................................................................102 Operation as carrier generator...................................................................................................109 Operation as PWM output (timer 40 only)..................................................................................114 9.5 Notes on Using 8-Bit Timers 30, 40........................................................................................116 CHAPTER 10 WATCHDOG TIMER .....................................................................................................118 10.1 10.2 10.3 10.4 Watchdog Timer Functions.....................................................................................................118 Watchdog Timer Configuration ..............................................................................................119 Watchdog Timer Control Registers........................................................................................120 Watchdog Timer Operation .....................................................................................................122 10.4.1 10.4.2 Operation as watchdog timer.....................................................................................................122 Operation as interval timer.........................................................................................................123 CHAPTER 11 POWER-ON-CLEAR CIRCUITS ...................................................................................124 11.1 11.2 11.3 11.4 Power-on-Clear Circuit Functions..........................................................................................124 Power-on-Clear Circuit Configuration ...................................................................................124 Power-on-Clear Circuit Control Registers.............................................................................126 Power-on-Clear Circuit Operation ..........................................................................................128 11.4.1 11.4.2 Power-on-clear (POC) circuit operation .....................................................................................128 Operation of low-voltage detection (LVI) circuit .........................................................................130 CHAPTER 12 BIT SEQUENTIAL BUFFER ........................................................................................132 12.1 Bit Sequential Buffer Functions .............................................................................................132 12 User's Manual U14826EJ4V0UD 12.2 Bit Sequential Buffer Configuration....................................................................................... 132 12.3 Bit Sequential Buffer Control Register ..................................................................................133 12.4 Bit Sequential Buffer Operation .............................................................................................134 CHAPTER 13 KEY RETURN CIRCUIT...............................................................................................135 13.1 Key Return Circuit Function ...................................................................................................135 13.2 Key Return Circuit Configuration and Operation .................................................................135 CHAPTER 14 INTERRUPT FUNCTIONS ............................................................................................136 14.1 14.2 14.3 14.4 Interrupt Function Types.........................................................................................................136 Interrupt Sources and Configuration.....................................................................................137 Interrupt Function Control Registers.....................................................................................139 Interrupt Servicing Operation.................................................................................................141 14.4.1 14.4.2 14.4.3 14.4.4 Non-maskable interrupt request acknowledgment operation..................................................... 141 Maskable interrupt request acknowledgment operation ............................................................ 143 Multiple interrupt servicing......................................................................................................... 146 Interrupt request pending .......................................................................................................... 147 CHAPTER 15 STANDBY FUNCTION..................................................................................................148 15.1 Standby Function and Configuration ....................................................................................148 15.1.1 15.1.2 15.2.1 15.2.2 Standby function........................................................................................................................ 148 Standby function control register ............................................................................................... 149 HALT mode ............................................................................................................................... 150 STOP mode .............................................................................................................................. 153 15.2 Standby Function Operation ..................................................................................................150 CHAPTER 16 RESET FUNCTION .......................................................................................................156 CHAPTER 17 PD78E9860A, 78E9861A ...........................................................................................159 17.1 EEPROM Features (Program Memory) ..................................................................................160 17.1.1 17.1.2 17.1.3 17.1.4 Programming environment ........................................................................................................ 160 Communication mode ............................................................................................................... 161 On-board pin processing ........................................................................................................... 164 Connection of adapter for EEPROM writing .............................................................................. 167 CHAPTER 18 MASK OPTIONS ...........................................................................................................169 CHAPTER 19 INSTRUCTION SET OVERVIEW.................................................................................170 19.1 Operation ..................................................................................................................................170 19.1.1 19.1.2 19.1.3 Operand identifiers and description methods ............................................................................ 170 Description of "Operation" column............................................................................................. 171 Description of "Flag" column...................................................................................................... 171 19.2 Operation List...........................................................................................................................172 User's Manual U14826EJ4V0UD 13 19.3 Instructions Listed by Addressing Type ...............................................................................177 CHAPTER 20 ELECTRICAL SPECIFICATIONS .................................................................................180 CHAPTER 21 EXAMPLE OF RC OSCILLATION FREQUENCY CHARACTERISTICS (REFERENCE VALUES)...............................................................................................195 CHAPTER 22 PACKAGE DRAWING ..................................................................................................196 CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS...........................................................197 APPENDIX A DEVELOPMENT TOOLS...............................................................................................199 A.1 A.2 A.3 A.4 A.5 A.6 Software Package ....................................................................................................................201 Language Processing Software .............................................................................................201 Control Software ......................................................................................................................202 EEPROM (Program Memory) Writing Tools ..........................................................................202 Debugging Tools (Hardware) ..................................................................................................203 Debugging Tools (Software) ...................................................................................................204 APPENDIX B NOTES ON TARGET SYSTEM DESIGN ...................................................................205 APPENDIX C REGISTER INDEX .........................................................................................................206 C.1 C.2 Register Name Index (in Alphabetical Order)........................................................................206 Register Symbol Index (in Alphabetical Order) ....................................................................207 APPENDIX D REVISION HISTORY .....................................................................................................208 14 User's Manual U14826EJ4V0UD LIST OF FIGURES (1/4) Figure No. 3-1 Title Page Pin I/O Circuits ................................................................................................................................................38 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 Memory Map (PD789860, 789861)...............................................................................................................39 Memory Map (PD78E9860A, 78E9861A) .....................................................................................................40 Data Memory Addressing (PD789860, 789861) ...........................................................................................42 Data Memory Addressing (PD78E9860A, 78E9861A)..................................................................................43 Program Counter Configuration ......................................................................................................................44 Program Status Word Configuration ...............................................................................................................44 Stack Pointer Configuration ............................................................................................................................45 Data to Be Saved to Stack Memory ................................................................................................................45 Data to Be Restored from Stack Memory .......................................................................................................45 General-Purpose Register Configuration ........................................................................................................46 5-1 5-2 EEPROM Block Diagram ................................................................................................................................58 Format of EEPROM Write Control Register 10 ...............................................................................................59 6-1 6-2 6-3 6-4 6-5 Block Diagram of P00 to P07 ..........................................................................................................................64 Block Diagram of P20 .....................................................................................................................................65 Block Diagram of P21 .....................................................................................................................................66 Block Diagram of P40 to P43 ..........................................................................................................................66 Format of Port Mode Register.........................................................................................................................67 7-1 7-2 7-3 7-4 7-5 Block Diagram of Clock Generator..................................................................................................................69 Format of Processor Clock Control Register...................................................................................................70 External Circuit of System Clock Oscillator .....................................................................................................71 Examples of Incorrect Resonator Connection.................................................................................................72 Switching Between System Clock and CPU Clock .........................................................................................75 8-1 8-2 8-3 8-4 8-5 Block Diagram of Clock Generator..................................................................................................................76 Format of Processor Clock Control Register...................................................................................................77 External Circuit of System Clock Oscillator .....................................................................................................78 Examples of Incorrect Resonator Connection.................................................................................................79 Switching Between System Clock and CPU Clock .........................................................................................82 9-1 9-2 9-3 Timer 30 Block Diagram .................................................................................................................................85 Timer 40 Block Diagram .................................................................................................................................86 Block Diagram of Output Controller (Timer 40) ...............................................................................................87 User's Manual U14826EJ4V0UD 15 LIST OF FIGURES (2/4) Figure No. 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 Title Page Format of 8-Bit Timer Mode Control Register 30.............................................................................................89 Format of 8-Bit Timer Mode Control Register 40.............................................................................................90 Format of Carrier Generator Output Control Register 40 ................................................................................91 Format of Port Mode Register 2 ......................................................................................................................92 Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)....................................................95 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Cleared to 00H).............................95 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) ...................................96 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N < M))..........96 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M))..........97 Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for Timer 30 Count Clock) ....................................................................................................................................98 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 Timing of Operation of External Event Counter with 8-Bit Resolution .............................................................99 Timing of Square-Wave Output with 8-Bit Resolution ...................................................................................101 Timing of Interval Timer Operation with 16-Bit Resolution ............................................................................104 Timing of External Event Counter Operation with 16-Bit Resolution .............................................................106 Timing of Square-Wave Output with 16-Bit Resolution .................................................................................108 Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N))...........................................111 Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N))...........................................112 Timing of Carrier Generator Operation (When CR40 = CRH40 = N) ............................................................113 PWM Output Mode Timing (Basic Operation) ...............................................................................................115 PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten)........................................................115 Case of Error Occurrence of up to 1.5 Clocks...............................................................................................116 Counting Operation if Timer Is Started When TMI Is High ............................................................................117 Timing of Operation as External Event Counter (8-Bit Resolution) ...............................................................117 10-1 10-2 10-3 Block Diagram of Watchdog Timer................................................................................................................119 Format of Timer Clock Selection Register 2..................................................................................................120 Format of Watchdog Timer Mode Register ...................................................................................................121 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 Block Diagram of Power-on-Clear Circuit......................................................................................................125 Block Diagram of Low-Voltage Detection Circuit ...........................................................................................125 Format of Power-on-Clear Register 1 ...........................................................................................................126 Format of Low-Voltage Detection Register 1.................................................................................................127 Format of Low-Voltage Detection Level Selection Register 1 .......................................................................127 Timing of Internal Reset Signal Generation When POC Circuit Normally Operating.....................................128 Timing of Internal Reset Signal Generation When POC Circuit Normally Halted ..........................................129 Timing of Internal Reset Signal Generation in POC Switching Circuit...........................................................129 User's Manual U14826EJ4V0UD 16 LIST OF FIGURES (3/4) Figure No. 11-9 Title Page LVI Circuit Operation Timing .........................................................................................................................131 12-1 12-2 12-3 12-4 Block Diagram of Bit Sequential Buffer .........................................................................................................132 Format of Bit Sequential Buffer Output Control Register 10 .........................................................................133 Format of Port Mode Register 2....................................................................................................................133 Operation Timing of Bit Sequential Buffer .....................................................................................................134 13-1 13-2 Block Diagram of Key Return Circuit.............................................................................................................135 Generation Timing of Key Return Interrupt ...................................................................................................135 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 Basic Configuration of Interrupt Function......................................................................................................138 Format of Interrupt Request Flag Register 0.................................................................................................139 Format of Interrupt Mask Flag Register 0 .....................................................................................................140 Program Status Word Configuration .............................................................................................................140 Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment (INTWDT)......................142 Timing of Non-Maskable Interrupt Request Acknowledgment ......................................................................142 Acknowledgment of Non-Maskable Interrupt Request ..................................................................................142 Interrupt Request Acknowledgment Processing Algorithm ...........................................................................144 Interrupt Request Acknowledgment Timing (Example of MOV A, r) .............................................................144 Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) ...................................................................................................................................145 14-11 Example of Multiple Interrupts.......................................................................................................................146 15-1 15-2 15-3 15-4 15-5 Format of Oscillation Stabilization Time Selection Register ..........................................................................149 Releasing HALT Mode by Interrupt...............................................................................................................151 Releasing HALT Mode by RESET Input .......................................................................................................152 Releasing STOP Mode by Interrupt ..............................................................................................................154 Releasing STOP Mode by RESET Input.......................................................................................................155 16-1 16-2 16-3 16-4 Block Diagram of Reset Function..................................................................................................................156 Reset Timing by RESET Input ......................................................................................................................157 Reset Timing by Watchdog Timer Overflow..................................................................................................157 Reset Timing by RESET Input in STOP Mode..............................................................................................157 17-1 17-2 17-3 Environment for Writing Program to EEPROM (Program Memory) ..............................................................160 Communication Mode Selection Format .......................................................................................................161 Example of Connection with Dedicated Flash Programmer ..........................................................................162 User's Manual U14826EJ4V0UD 17 LIST OF FIGURES (4/4) Figure No. 17-4 17-5 17-6 17-7 17-8 Title Page VPP Pin Connection Example ........................................................................................................................164 Signal Conflict (Input Pin of Serial Interface).................................................................................................165 Abnormal Operation of Other Device ............................................................................................................165 Signal Conflict (RESET Pin)..........................................................................................................................166 Wiring Example for EEPROM Writing Adapter with Pseudo 3-Wire..............................................................167 A-1 Development Tools .......................................................................................................................................200 B-1 Connection Condition of Target.....................................................................................................................205 18 User's Manual U14826EJ4V0UD LIST OF TABLES (1/2) Table No. 3-1 Title Page Types of Pin I/O Circuits and Recommended Connection of Unused Pins .....................................................38 4-1 4-2 4-3 Internal ROM Capacity....................................................................................................................................41 Vector Table ...................................................................................................................................................41 Special Function Registers .............................................................................................................................48 5-1 5-2 EEPROM Write Time (When Operating at fX = 5.0 MHz)................................................................................60 EEPROM Write Time (When Operating at fCC = 1.0 MHz)..............................................................................60 6-1 6-2 6-3 Port Functions.................................................................................................................................................63 Configuration of Port .......................................................................................................................................63 Port Mode Register and Output Latch Settings for Using Alternate Functions................................................67 7-1 7-2 Configuration of Clock Generator....................................................................................................................69 Maximum Time Required for Switching CPU Clock ........................................................................................75 8-1 8-2 Configuration of Clock Generator....................................................................................................................76 Maximum Time Required for Switching CPU Clock ........................................................................................82 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 Mode List ........................................................................................................................................................83 Configuration of 8-Bit Timers 30, 40 ...............................................................................................................84 Interval Time of Timer 30 (During fX = 5.0 MHz Operation).............................................................................94 Interval Time of Timer 30 (During fCC = 1.0 MHz Operation)...........................................................................94 Interval Time of Timer 40 (During fX = 5.0 MHz Operation).............................................................................94 Interval Time of Timer 40 (During fCC = 1.0 MHz Operation)...........................................................................94 Square-Wave Output Range of Timer 40 (During fX = 5.0 MHz Operation) ..................................................100 Square-Wave Output Range of Timer 40 (During fCC = 1.0 MHz Operation) ................................................100 Interval Time with 16-Bit Resolution (During fX = 5.0 MHz Operation) ..........................................................103 Interval Time with 16-Bit Resolution (During fCC = 1.0 MHz Operation) ........................................................103 Square-Wave Output Range with 16-Bit Resolution (During fX = 5.0 MHz Operation)..................................107 Square-Wave Output Range with 16-Bit Resolution (During fCC = 1.0 MHz Operation) ................................107 10-1 10-2 10-3 10-4 10-5 Inadvertent Program Loop Detection Time of Watchdog Timer ....................................................................118 Interval Time of Watchdog Timer ..................................................................................................................118 Configuration of Watchdog Timer .................................................................................................................119 Inadvertent Program Loop Detection Time of Watchdog Timer ....................................................................122 Interval Time of Watchdog Timer ..................................................................................................................123 User's Manual U14826EJ4V0UD 19 LIST OF TABLES (2/2) Table No. 12-1 Title Page Configuration of Bit Sequential Buffer ...........................................................................................................132 14-1 14-2 14-3 Interrupt Sources...........................................................................................................................................137 Interrupt Request Signals and Corresponding Flags.....................................................................................139 Time from Generation of Maskable Interrupt Request to Servicing...............................................................143 15-1 15-2 15-3 15-4 Operation Statuses in HALT Mode................................................................................................................150 Operation After Releasing HALT Mode .........................................................................................................152 Operation Statuses in STOP Mode ...............................................................................................................153 Operation After Releasing STOP Mode ........................................................................................................155 16-1 Status of Hardware After Reset.....................................................................................................................158 Differences Between PD78E9860A, 78E9861A and Mask ROM Versions .................................................159 Communication Mode List.............................................................................................................................161 Pin Connection List .......................................................................................................................................163 17-1 17-2 17-3 19-1 Operand Identifiers and Description Methods ...............................................................................................170 23-1 Surface Mounting Type Soldering Conditions ...............................................................................................197 20 User's Manual U14826EJ4V0UD CHAPTER 1 GENERAL (PD789860 SUBSERIES) 1.1 Features * ROM and RAM capacity Item Product Name Program Memory (ROM) Mask ROM EEPROM 4 KB 4 KB Data Memory Internal High-Speed RAM 128 bytes EEPROM 32 bytes TM PD789860 PD78E9860A * System clock: Ceramic/crystal oscillation * Minimum instruction execution time can be changed from high-speed (0.4 s) to low-speed (1.6 s) at 5.0 MHz operation with system clock. * I/O ports: 14 * Timer: 3 channels * * 8-bit timer: Watchdog timer: 2 channels 1 channel * On-chip power-on-clear circuit * On-chip bit sequential buffer * Power supply voltage: VDD = 1.8 to 5.5 V * Operating ambient temperature: TA = -40 to +85C 1.2 Applications Keyless entry and other automotive electrical equipment. 1.3 Ordering Information Part Number Package 20-pin plastic SSOP (7.62 mm (300)) 20-pin plastic SSOP (7.62 mm (300)) Internal ROM Mask ROM EEPROM PD789860MC-xxx-5A4 PD78E9860AMC-5A4 Remark xxx indicates ROM code suffix. User's Manual U14826EJ4V0UD 21 CHAPTER 1 GENERAL (PD789860 SUBSERIES) 1.4 Pin Configuration (Top View) 20-pin plastic SSOP (7.62 mm (300)) PD789860MC-xxx-5A4 PD78E9860AMC-5A4 RESET X1 X2 VSS IC (VPP) VDD P00 P01 P02 P03 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P21/TMI P20/TMO/BSFO P07 P06 P05 P04 P43/KR13 P42/KR12 P41/KR11 P40/KR10 Caution Remark BSFO: IC: Connect the IC (Internally Connected) pin directly to VSS. Pin connections in parentheses are intended for the PD78E9860A. Bit sequential buffer output Internally connected Key return Port 0 Port 2 Port 4 Reset TMI: TMO: VDD: VPP: VSS: X1, X2: Timer input Timer output Power supply Programming power supply Ground Crystal/ceramic oscillator KR10 to KR13: P00 to P07: P20, P21: P40 to P43: RESET: 22 User's Manual U14826EJ4V0UD CHAPTER 1 GENERAL (PD789860 SUBSERIES) 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Y Subseries products support SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 30-pin 28-pin 20-pin 20-pin PD789046 PD789026 PD789088 PD789074 PD789014 PD789062 PD789052 PD789074 with added subsystem clock PD789014 with enhanced timer and increased ROM, RAM capacity PD789074 with enhanced timer and increased ROM, RAM capacity PD789026 with enhanced timer On-chip UART and capable of low voltage (1.8 V) operation RC oscillation version of the PD789052 PD789860 without EEPROM, POC, and LVI Products under development Small-scale package, general-purpose applications and A/D converter 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A PD789177Y PD789167Y PD789167 with enhanced A/D converter (10 bits) PD789104A with enhanced timer PD789146 with enhanced A/D converter (10 bits) PD789104A with added EEPROM PD789124A with enhanced A/D converter (10 bits) RC oscillation version of the PD789104A PD789104A with enhanced A/D converter (10 bits) PD789026 with added 8-bit A/D converter and multiplier LCD drive 144-pin 88-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 52-pin 52-pin USB 44-pin PD789800 PD789835 PD789830 PD789488 PD789478 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327 UART, 8-bit A/D, and dot LCD (Total display output pins: 96) UART and dot LCD (40 x 16) SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 x 4) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789407A with enhanced A/D converter (10 bits) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789446 with enhanced A/D converter (10 bits) SIO, 8-bit A/D, and on-chip voltage booster type LCD (15 x 4) PD789426 with enhanced A/D converter (10 bits) SIO, 8-bit A/D, and on-chip voltage booster type LCD (5 x 4) RC oscillation version of the PD789306 SIO and on-chip voltage booster type LCD (24 x 4) 8-bit A/D and on-chip voltage booster type LCD (23 x 4) SIO and resistance division type LCD (24 x 4) 78K/0S Series For PC keyboard and on-chip USB function Inverter control 44-pin PD789842 On-chip inverter controller and UART On-chip bus controller 44-pin 30-pin PD789852 PD789850A PD789850A with enhanced functions such as timer and A/D converter On-chip CAN controller Keyless entry 30-pin 20-pin 20-pin PD789862 PD789861 PD789860 PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity RC oscillation version of the PD789860 On-chip POC and key return circuit VFD drive 52-pin PD789871 On-chip VFD controller (Total display output pins: 25) Meter control 64-pin PD789881 UART and resistance division type LCD (26 x 4) Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. User's Manual U14826EJ4V0UD 23 CHAPTER 1 GENERAL (PD789860 SUBSERIES) The major functional differences between the subseries are listed below. Series for General-purpose applications and LCD drive Function ROM Capacity Subseries Name Small-scale PD789046 package, generalpurpose applications (Bytes) 16 KB 4 KB to 16 KB 16 KB to 32 KB 3 ch Timer 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D Serial Interface I/O VDD MIN. Value 1 ch 1 ch 1 ch - 1 ch - - 1 ch (UART: 1 ch) 24 34 1.8 V - Remarks PD789026 PD789088 PD789074 PD789014 PD789062 PD789052 2 KB to 8 KB 2 KB to 4 KB 4 KB 1 ch 2 ch - - 22 14 RC oscillation version - Small-scale PD789177 package, generalpurpose 16 KB to 24 KB 3 ch 1 ch 1 ch 1 ch - 8 ch 8 ch 1 ch - 4 ch - 4 ch - 4 ch - - 1 ch (UART: 1 ch) (UART: 1 ch) 31 1.8 V - PD789167 PD789156 8 KB to 16 KB 1 ch - - 4 ch - 4 ch - 4 ch 20 On-chip EEPROM RC oscillation version - applications PD789146 and A/D converter PD789134A 2 KB to 8 KB PD789124A PD789114A PD789104A LCD drive PD789835 PD789830 PD789488 PD789478 24 KB to 60 KB 24 KB 32 KB to 48 KB 24 KB to 48 KB 6 ch - 1 ch 1 ch 3 ch - 37 1.8 V Note Dot LCD supported 1 ch 3 ch 1 ch 30 8 ch 2 ch (UART: 1 ch) - 45 2.7 V 1.8 V - 8 ch - 7 ch 2 ch - 6 ch - 6 ch PD789417A 12 KB to PD789407A 24 KB PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327 4 KB to 24 KB - 8 KB to 16 KB 12 KB to 16 KB 7 ch 1 ch - 6 ch - 6 ch - 2 ch (UART: 1 ch) (UART: 1 ch) 43 30 40 - 23 RC oscillation version - 1 ch - 1 ch - 18 21 Note Flash memory version: 3.0 V 24 User's Manual U14826EJ4V0UD CHAPTER 1 GENERAL (PD789860 SUBSERIES) Series for ASSP Function ROM Capacity (Bytes) Subseries Name USB Timer 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D Serial Interface I/O VDD MIN. Value 2 ch - - 1 ch - - - 2 ch (USB: 1 ch) Inverter control On-chip bus PD789852 controller 24 KB to 32 KB 3 ch 1 ch - 1 ch - 31 4.0 V - - - Remarks PD789800 PD789842 8 KB 8 KB to 16 KB 3 ch Note 1 1 ch 1 ch 8 ch 1 ch (UART: 1 ch) 30 4.0 V 8 ch 3 ch (UART: 2 ch) - - 31 4.0 V PD789850A 16 KB PD789861 1 ch - - 4 ch - 2 ch (UART: 1 ch) - 18 Keyless entry 4 KB 2 ch 1 ch 14 1.8 V RC oscillation version, onchip EEPROM PD789860 PD789862 PD789871 PD789881 16 KB 1 ch 2 ch - 1 ch - - - - 1 ch (UART: 1 ch) VFD drive Meter control 4 KB to 8 KB 16 KB 3 ch 2 ch 1 ch - 1 ch 1 ch 1 ch 1 ch (UART: 1 ch) 33 2.7 V Note 2 On-chip 22 EEPROM - - 28 2.7 V Notes 1. 10-bit timer: 1 channel 2. Flash memory version: 3.0 V User's Manual U14826EJ4V0UD 25 CHAPTER 1 GENERAL (PD789860 SUBSERIES) 1.6 Block Diagram TMI/P21 TMO/P20 8-bit timer 30 Cascaded 16-bit 8-bit timer/ timer event counter counter 40 Port 0 P00 to P07 78K/0S CPU core Port 2 ROM Port 4 P20, P21 P40 to P43 RESET X1 X2 BSFO/P20 Bit seq. buffer System control Watchdog timer RAM EEPROM Power Power on on clear clear Low voltage indicator VDD VSS IC (VPP) KR10/P40 to KR13/P43 Key return 10 Remark Pin connections in parentheses are intended for the PD78E9860A. 26 User's Manual U14826EJ4V0UD CHAPTER 1 GENERAL (PD789860 SUBSERIES) 1.7 Overview of Functions Part Number Item Internal memory ROM Mask ROM 4 KB High-speed RAM EEPROM Oscillator Minimum instruction execution time General-purpose registers Instruction set 128 bytes 32 bytes Ceramic/crystal oscillator 0.4/1.6 s (@5.0 MHz operation with system clock) 8 bits x 8 registers * 16-bit operations * Bit manipulations (such as set, reset, and test) I/O ports Total: CMOS I/O: CMOS input: Timers * 8-bit timer: * Watchdog timer: Power-on-clear circuit LVI circuit POC circuit 14 10 4 2 channels 1 channel EEPROM PD789860 PD78E9860A Generates internal reset signal according to comparison of detection voltage to power supply voltage Generates interrupt request signal according to comparison of detection voltage to power supply voltage 8 bits x 8 bits = 16 bits Generates key return signal according to falling edge detection Bit sequential buffer Key return function Vectored interrupt sources Power supply voltage Operating ambient temperature Package Maskable Non-maskable Internal: 5 Internal: 1, external: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C 20-pin plastic SSOP (7.62 mm (300)) User's Manual U14826EJ4V0UD 27 CHAPTER 2 GENERAL (PD789861 SUBSERIES) 2.1 Features * ROM and RAM capacity Item Product Name Program Memory (ROM) Mask ROM EEPROM 4 KB 4 KB Data Memory Internal High-Speed RAM 128 bytes EEPROM 32 bytes PD789861 PD78E9861A * System clock: RC oscillation * Minimum instruction execution time can be changed from high-speed (2.0 s) to low-speed (8.0 s) at 1.0 MHz operation with system clock. * I/O ports: 14 * Timer: 3 channels * * 8-bit timer: Watchdog timer: 2 channels 1 channel * On-chip power-on-clear circuit * On-chip bit sequential buffer * Power supply voltage: VDD = 1.8 to 3.6 V * Operating ambient temperature: TA = -40 to +85C 2.2 Applications Keyless entry and other automotive electrical equipment. 2.3 Ordering Information Part Number Package 20-pin plastic SSOP (7.62 mm (300)) 20-pin plastic SSOP (7.62 mm (300)) Internal ROM Mask ROM EEPROM PD789861MC-xxx-5A4 PD78E9861AMC-5A4 Remark xxx indicates ROM code suffix. 28 User's Manual U14826EJ4V0UD CHAPTER 2 GENERAL (PD789861 SUBSERIES) 2.4 Pin Configuration (Top View) 20-pin plastic SSOP (7.62 mm (300)) PD789861MC-xxx-5A4 PD78E9861AMC-5A4 RESET CL1 CL2 VSS IC (VPP) VDD P00 P01 P02 P03 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P21/TMI P20/TMO/BSFO P07 P06 P05 P04 P43/KR13 P42/KR12 P41/KR11 P40/KR10 Caution Remark BSFO: CL1, CL2: IC: Connect the IC (Internally Connected) pin directly to VSS. Pin connections in parentheses are intended for the PD78E9861A. Bit sequential buffer output RC oscillator Internally connected Key return Port 0 Port 2 Port 4 RESET: TMI: TMO: VDD: VPP: VSS: Reset Timer input Timer output Power supply Programming power supply Ground KR10 to KR13: P00 to P07: P20, P21: P40 to P43: User's Manual U14826EJ4V0UD 29 CHAPTER 2 GENERAL (PD789861 SUBSERIES) 2.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Y Subseries products support SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 30-pin 28-pin 20-pin 20-pin PD789046 PD789026 PD789088 PD789074 PD789014 PD789062 PD789052 PD789074 with added subsystem clock PD789014 with enhanced timer and increased ROM, RAM capacity PD789074 with enhanced timer and increased ROM, RAM capacity PD789026 with enhanced timer On-chip UART and capable of low voltage (1.8 V) operation RC oscillation version of the PD789052 PD789860 without EEPROM, POC, and LVI Products under development Small-scale package, general-purpose applications and A/D converter 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A PD789177Y PD789167Y PD789167 with enhanced A/D converter (10 bits) PD789104A with enhanced timer PD789146 with enhanced A/D converter (10 bits) PD789104A with added EEPROM PD789124A with enhanced A/D converter (10 bits) RC oscillation version of the PD789104A PD789104A with enhanced A/D converter (10 bits) PD789026 with added 8-bit A/D converter and multiplier LCD drive 144-pin 88-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 52-pin 52-pin USB 44-pin PD789800 PD789835 PD789830 PD789488 PD789478 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327 UART, 8-bit A/D, and dot LCD (Total display output pins: 96) UART and dot LCD (40 x 16) SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 x 4) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789407A with enhanced A/D converter (10 bits) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789446 with enhanced A/D converter (10 bits) SIO, 8-bit A/D, and on-chip voltage booster type LCD (15 x 4) PD789426 with enhanced A/D converter (10 bits) SIO, 8-bit A/D, and on-chip voltage booster type LCD (5 x 4) RC oscillation version of the PD789306 SIO and on-chip voltage booster type LCD (24 x 4) 8-bit A/D and on-chip voltage booster type LCD (23 x 4) SIO and resistance division type LCD (24 x 4) 78K/0S Series For PC keyboard and on-chip USB function Inverter control 44-pin PD789842 On-chip inverter controller and UART On-chip bus controller 44-pin 30-pin PD789852 PD789850A PD789850A with enhanced functions such as timer and A/D converter On-chip CAN controller Keyless entry 30-pin 20-pin 20-pin PD789862 PD789861 PD789860 PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity RC oscillation version of the PD789860 On-chip POC and key return circuit VFD drive 52-pin PD789871 On-chip VFD controller (Total display output pins: 25) Meter control 64-pin PD789881 UART and resistance division type LCD (26 x 4) Remark VFD (Vacuum Fluorescent Display) is referred to as FIP (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. 30 User's Manual U14826EJ4V0UD CHAPTER 2 GENERAL (PD789861 SUBSERIES) The major functional differences between the subseries are listed below. Series for General-purpose applications and LCD drive Function ROM Capacity Subseries Name Small-scale PD789046 package, generalpurpose applications (Bytes) 16 KB 4 KB to 16 KB 16 KB to 32 KB 3 ch Timer 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D Serial Interface I/O VDD MIN. Value 1 ch 1 ch 1 ch - 1 ch - - 1 ch (UART: 1 ch) 24 34 1.8 V - Remarks PD789026 PD789088 PD789074 PD789014 PD789062 PD789052 2 KB to 8 KB 2 KB to 4 KB 4 KB 1 ch 2 ch - - 22 14 RC oscillation version - Small-scale PD789177 package, generalpurpose 16 KB to 24 KB 3 ch 1 ch 1 ch 1 ch - 8 ch 8 ch 1 ch - 4 ch - 4 ch - 4 ch - - 1 ch (UART: 1 ch) (UART: 1 ch) 31 1.8 V - PD789167 PD789156 8 KB to 16 KB 1 ch - - 4 ch - 4 ch - 4 ch 20 On-chip EEPROM RC oscillation version - applications PD789146 and A/D converter PD789134A 2 KB to 8 KB PD789124A PD789114A PD789104A LCD drive PD789835 PD789830 PD789488 PD789478 24 KB to 60 KB 24 KB 32 KB to 48 KB 24 KB to 48 KB 6 ch - 1 ch 1 ch 3 ch - 37 1.8 V Note Dot LCD supported 1 ch 3 ch 1 ch 30 8 ch 2 ch (UART: 1 ch) - 45 2.7 V 1.8 V - 8 ch - 7 ch 2 ch - 6 ch - 6 ch PD789417A 12 KB to PD789407A 24 KB PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327 4 KB to 24 KB - 8 KB to 16 KB 12 KB to 16 KB 7 ch 1 ch - 6 ch - 6 ch - 2 ch (UART: 1 ch) (UART: 1 ch) 43 30 40 - 23 RC oscillation version - 1 ch - 1 ch - 18 21 Note Flash memory version: 3.0 V User's Manual U14826EJ4V0UD 31 CHAPTER 2 GENERAL (PD789861 SUBSERIES) Series for ASSP Function ROM Capacity Subseries Name USB (Bytes) 8 KB Timer 8-Bit 16-Bit Watch WDT - - 8-Bit 10-Bit A/D A/D Serial Interface I/O VDD MIN. Value 2 ch 1 ch - - - 2 ch (USB: 1 ch) Inverter control On-chip bus PD789852 controller 24 KB to 32 KB 3 ch 1 ch - 1 ch - 31 4.0 V - - - Remarks PD789800 PD789842 8 KB to 16 KB 3 ch Note 1 1 ch 1 ch 8 ch 1 ch (UART: 1 ch) 30 4.0 V 8 ch 3 ch (UART: 2 ch) - - 31 4.0 V PD789850A 16 KB PD789861 1 ch - - 4 ch - 2 ch (UART: 1 ch) - 18 Keyless entry 4 KB 2 ch 1 ch 14 1.8 V RC oscillation version, onchip EEPROM PD789860 PD789862 PD789871 PD789881 16 KB 1 ch 2 ch - 1 ch - - - - 1 ch (UART: 1 ch) VFD drive Meter control 4 KB to 8 KB 16 KB 3 ch 2 ch 1 ch - 1 ch 1 ch 1 ch 1 ch (UART: 1 ch) 33 28 2.7 V 2.7 V Note 2 On-chip 22 EEPROM - - Notes 1. 10-bit timer: 1 channel 2. Flash memory version: 3.0 V 32 User's Manual U14826EJ4V0UD CHAPTER 2 GENERAL (PD789861 SUBSERIES) 2.6 Block Diagram TMI/P21 TMO/P20 8-bit timer 30 Cascaded 16-bit 8-bit timer/ timer event counter counter 40 Port 0 P00 to P07 78K/0S CPU core Port 2 ROM Port 4 P20, P21 P40 to P43 RESET CL1 CL2 BSFO/P20 Bit seq. buffer System control Watchdog timer RAM EEPROM Power Power on on clear clear Low voltage indicator VDD VSS IC (VPP) KR10/P40 to KR13/P43 Key return 10 Remark Pin connections in parentheses are intended for the PD78E9861A. User's Manual U14826EJ4V0UD 33 CHAPTER 2 GENERAL (PD789861 SUBSERIES) 2.7 Overview of Functions Part Number Item Internal memory ROM Mask ROM 4 KB High-speed RAM EEPROM Oscillator Minimum instruction execution time General-purpose registers Instruction set 128 bytes 32 bytes RC oscillator 2.0/8.0 s (@1.0 MHz operation with system clock) 8 bits x 8 registers * 16-bit operations * Bit manipulations (such as set, reset, and test) I/O ports Total: CMOS I/O: CMOS input: Timers * 8-bit timer: * Watchdog timer: Power-on-clear circuit LVI circuit POC circuit 14 10 4 2 channels 1 channel EEPROM PD789861 PD78E9861A Generates internal reset signal according to comparison of detection voltage to power supply voltage Generates interrupt request signal according to comparison of detection voltage to power supply voltage 8 bits x 8 bits = 16 bits Generates key return signal according falling edge detection Bit sequential buffer Key return function Vectored interrupt sources Power supply voltage Operating ambient temperature Package Maskable Non-maskable Internal: 5 Internal: 1, external: 1 VDD = 1.8 to 3.6 V TA = -40 to +85C 20-pin plastic SSOP (7.62 mm (300)) 34 User's Manual U14826EJ4V0UD CHAPTER 3 PIN FUNCTIONS 3.1 Pin Function List (1) Port pins I/O I/O Port 0 8-bit I/O port Input/output can be specified in 1-bit units. P20 P21 P40 to P43 Input I/O Port 2 2-bit I/O port Input/output can be specified in 1-bit units. Port 4 4-bit input-only port For mask ROM versions, an on-chip pull-up resistor can be specified by means of the mask option. Input TMI KR10 to KR13 Input TMO/BSFO Function After Reset Input Alternate Function KR0 to KR3 Pin Name P00 to P07 (2) Non-port pins I/O Input Output Output Input Input - Input - Input - - - - 8-bit timer (TM40) input 8-bit timer (TM40) output Bit sequential buffer (BSF10) output Key return input Connecting ceramic/crystal resonator for system clock oscillation Connecting resistor (R) and capacitor (C) for system clock oscillation System reset input Positive supply voltage Ground potential Internally connected. Connect directly to VSS. This pin is used to set the EEPROM programming mode and applies a high voltage when a program is written or verified. Function After Reset Input Input Input Input - - - - Input - - - - Alternate Function P21 P20/BSFO P20/TMO P40 to P43 - - - - - - - - - Pin Name TMI TMO BSFO KR10 to KR13 X1 X2 Note 1 Note 1 CL1 CL2 Note 2 Note 2 RESET VDD VSS IC VPP Notes 1. PD789860 Subseries only 2. PD789861 Subseries only User's Manual U14826EJ4V0UD 35 CHAPTER 3 PIN FUNCTIONS 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode register 0 (PM0). 3.2.2 P20, P21 (Port 2) These pins constitute a 2-bit I/O port. In addition, these pins function as the timer input/output and bit sequential buffer output. Port 2 can be set to the following operation modes in 1-bit units. (1) Port mode In port mode, P20 and P21 function as a 2-bit I/O port. Port 2 can be set to input or output port mode in 1-bit units by using port mode register 2 (PM2). (2) Control mode In this mode, P20 and P21 function as the timer input/output and the bit sequential buffer output. (a) BSFO This is the output pin of the bit sequential buffer. (b) TMI This is the external clock input pin for the timer 40. (c) TMO This is the output pin of the timer 40. 3.2.3 P40 to P43 (Port 4) These pins constitute a 4-bit input-only port. In addition, these pins function as the key return input. (1) Port mode In port mode, P40 to P43 function as a 4-bit input-only port. For mask ROM versions, an on-chip pull-up resistor can be specified by means of the mask option. (2) Control mode In this mode, P40 to P43 function as the key return input (KR10 to KR13). 3.2.4 RESET An active-low system reset signal is input to this pin. 3.2.5 X1, X2 (PD789860 Subseries) These pins are used to connect a crystal resonator for system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 3.2.6 CL1, CL2 (PD789861 Subseries) These pins are used to connect a resistor (R) and capacitor (C) for system clock oscillation. To supply an external clock, input the clock to CL1 and input the inverted signal to CL2. 36 User's Manual U14826EJ4V0UD CHAPTER 3 PIN FUNCTIONS 3.2.7 VDD This pin supplies positive power. 3.2.8 VSS This pin is the ground potential pin. 3.2.9 VPP (PD78E9860A, 78E9861A only) A high voltage should be applied to this pin when the EEPROM programming mode is set and when the program is written or verified. Perform either of the following pin handling. * Individually connect a 10 k pull-down resistor. * Connect to a dedicate flash programmer in the programming mode and directly to VSS in the normal operation mode by using a jumper on the board. If the wiring length between the VPP and VSS pins is too long or if external noise is superimposed on the VPP pin, your program may not be executed correctly. 3.2.10 IC (mask ROM version only) The IC (Internally Connected) pin is used to set the PD789860 and 789861 to test mode before shipment. In normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as possible. If a potential difference is generated between the IC pin and the VSS pin due to a long wiring length between these pins or an external noise superimposed on the IC pin, the user program may not run correctly. * Directly connect the IC pin to the VSS pin. VSS IC Keep short User's Manual U14826EJ4V0UD 37 CHAPTER 3 PIN FUNCTIONS 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, see Figure 3-1. Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name P00 to P07 P20/TMO/BSFO P21/TMI P40/KR10 to P43/KR13 (mask ROM version) P40/KR10 to P43/KR13 (PD78E9860A, 78E9861A) RESET IC VPP - - Connect directly to VSS. Independently connect to a 10 k pull-down resistor or connect directly to VSS. 2 - 2-E Connect directly to VDD. I/O Circuit Type 5 8 I/O I/O Input: Recommended Connection of Unused Pins Independently connect to VDD or VSS via a resistor. Output: Leave open. Figure 3-1. Pin I/O Circuits Type 2 Type 5 VDD Data P-ch IN/OUT Output disable N-ch VSS IN Schmitt-triggered input with hysteresis characteristics Input enable Type 2-E Type 8 Pull-up resistor (mask option) VDD Data VDD P-ch IN/OUT Output disable IN N-ch VSS 38 User's Manual U14826EJ4V0UD CHAPTER 4 CPU ARCHITECTURE 4.1 Memory Space The PD789860, 789861 Subseries can each access up to 64 KB of memory space. Figures 4-1 and 4-2 show the memory maps. Figure 4-1. Memory Map (PD789860, 789861) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 128 x 8 bits FE80H FE7FH Reserved F820H F81FH F800H F7FFH EEPROM (data memory) 32 x 8 bits 0FFFH Data memory space Reserved 1000H 0FFFH Program area Program memory space Internal ROM 4,096 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 000EH 000DH Vector table area 0000H 0000H User's Manual U14826EJ4V0UD 39 CHAPTER 4 CPU ARCHITECTURE Figure 4-2. Memory Map (PD78E9860A, 78E9861A) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 128 x 8 bits FE80H FE7FH Reserved F820H F81FH F800H F7FFH EEPROM (data memory) 32 x 8 bits 0FFFH Data memory space Reserved 1000H 0FFFH Program area Program memory space EEPROM (program memory) 4,096 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 000EH 000DH 0000H 0000H Vector table area 40 User's Manual U14826EJ4V0UD CHAPTER 4 CPU ARCHITECTURE 4.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The PD789860, 789861 Subseries provide the following internal ROMs (or EEPROM) containing the following capacities. Table 4-1. Internal ROM Capacity Part Number Structure Internal ROM Capacity 4,096 x 8 bits PD789860, 789861 PD78E9860A, 78E9861A Mask ROM EEPROM The following areas are allocated to the internal program memory space: (1) Vector table area The 14-byte area of addresses 0000H to 000DH is reserved as a vector table area. This area stores program start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. Table 4-2. Vector Table Vector Table Address 0000H 0002H 0004H 0006H Interrupt Request RESET input INTKR1 INTWDT INTTM30 Vector Table Address 0008H 000AH 000CH Interrupt Request INTTM40 INTLVI1 INTEE0 (2) CALLT instruction table area The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of addresses 0040H to 007FH. 4.1.2 Internal data memory space The PD789860, 789861 Subseries provide the following RAMs. (1) Internal high-speed RAM The internal high-speed RAM is provided in the area of FE80H to FEFFH. The internal high-speed RAM can also be used as a stack memory. (2) EEPROM The EEPROM is provided in the area of F800H to F81FH. For details of EEPROM, see CHAPTER 5 EEPROM (DATA MEMORY). User's Manual U14826EJ4V0UD 41 CHAPTER 4 CPU ARCHITECTURE 4.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 4-3). 4.1.4 Data memory addressing Each of the PD789860, 789861 Subseries is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. The data memory area (FE80H to FFFFH) can be accessed using a unique addressing mode according to its use, such as a special function register (SFR). Figures 4-3 and 4-4 illustrate the data memory addressing. Figure 4-3. Data Memory Addressing (PD789860, 789861) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FE1FH FF00H FEFFH SFR addressing Short direct addressing Internal high-speed RAM 128 x 8 bits FE80H FE7FH Reserved F820H F81FH F800H F7FFH EEPROM 32 x 8 bits Direct addressing Register indirect addressing Based addressing Reserved 1000H 0FFFH Internal ROM 4,096 x 8 bits 0000H 42 User's Manual U14826EJ4V0UD CHAPTER 4 CPU ARCHITECTURE Figure 4-4. Data Memory Addressing (PD78E9860A, 78E9861A) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FE1FH FF00H FEFFH SFR addressing Short direct addressing Internal high-speed RAM 128 x 8 bits FE80H FE7FH Reserved F820H F81FH F800H F7FFH Direct addressing Register indirect addressing EEPROM (data memory) 32 x 8 bits Based addressing Reserved 1000H 0FFFH EEPROM (program memory) 4,096 x 8 bits 0000H User's Manual U14826EJ4V0UD 43 CHAPTER 4 CPU ARCHITECTURE 4.2 Processor Registers The PD789860, 789861 Subseries provide the following on-chip processor registers: 4.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 4-5. Program Counter Configuration 15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions. RESET input sets PSW to 02H. Figure 4-6. Program Status Word Configuration 7 PSW IE Z 0 AC 0 0 1 0 CY (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt are disabled. When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources. This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases. (c) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all other cases. 44 User's Manual U14826EJ4V0UD CHAPTER 4 CPU ARCHITECTURE (d) Carry flag (CY) This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 4-7. Stack Pointer Configuration 15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 SP0 The SP is decremented before writing (saving) to the stack memory and is incremented after reading (restoring) from the stack memory. Each stack operation saves/restores data as shown in Figures 4-8 and 4-9. Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before instruction execution. Figure 4-8. Data to Be Saved to Stack Memory PUSH rp instruction CALL, CALLT instructions SP SP SP _ 2 SP _ 2 SP _ 1 SP Lower half register pairs Upper half register pairs SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 SP _ 3 SP _ 3 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 PSW Interrupt Figure 4-9. Data to Be Restored from Stack Memory POP rp instruction RET instruction RETI instruction SP SP + 1 SP SP + 2 Lower half register pairs Upper half register pairs SP SP SP + 1 SP + 2 PC7 to PC0 PC15 to PC8 SP SP + 1 SP + 2 SP SP + 3 PC7 to PC0 PC15 to PC8 PSW User's Manual U14826EJ4V0UD 45 CHAPTER 4 CPU ARCHITECTURE 4.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL). Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 4-10. General-Purpose Register Configuration (a) Absolute names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 (b) Function names 16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 0 7 0 46 User's Manual U14826EJ4V0UD CHAPTER 4 CPU ARCHITECTURE 4.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). manipulation can also be specified with an address. * 16-bit manipulation Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying an address, describe an even address. Table 4-3 lists the special function registers. The meanings of the symbols in this table are as follows: * Symbol Indicates the addresses of the implemented special function registers. The symbols shown in this column are reserved words in the assembler, and have already been defined in a header file called "sfrbit.h" in the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. * R/W Indicates whether the special function register can be read or written. R/W: Read/write R: W: Read only Write only This * Number of bits manipulated simultaneously Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated. * After reset Indicates the status of the special function register when the RESET signal is input. User's Manual U14826EJ4V0UD 47 CHAPTER 4 CPU ARCHITECTURE Table 4-3. Special Function Registers Address Special Function Register (SFR) Name Symbol R/W Number of Bits Manipulated Simultaneously 1 Bit FF00H FF02H FF04H FF10H FF11H FF20H FF22H FF42H FF50H FF51H FF52H FF53H FF54H FF55H FF56H FF57H Port 0 Port 2 Port 4 P0 P2 P4 R W R/W - - R/W - W R R/W W - - - - R R/W W - - - 8 Bits - - - - - - - - - - - - - - - - - - - - - FFH 00H 04H 00H Undefined 00H Undefined 00H FFH 16 Bits - - - Note 1 After Reset 00H Bit sequential buffer 10 data register L BSFRL10 Bit sequential buffer 10 data register H BSFRH10 Port mode register 0 Port mode register 2 Timer clock selection register 2 8-bit compare register 30 8-bit timer counter 30 8-bit timer mode control register 30 8-bit compare register 40 8-bit compare register H40 8-bit timer counter 40 8-bit timer mode control register 40 Carrier generator output control register 40 PM0 PM2 TCL2 CR30 TM30 TMC30 CR40 CRH40 TM40 TMC40 TCA40 Undefined FF60H Bit sequential buffer output control register 10 BSFC10 R/W FFD8H FFDDH FFDEH FFDFH EEPROM write control register 10 Power-on-clear register 1 Low-voltage detection register 1 Low-voltage detection level selection register 1 EEWC10 POCF1 LVIF1 LVIS1 08H 00H 00H Note 2 FFE0H FFE4H FFF9H FFFAH Interrupt request flag register 0 Interrupt mask flag register 0 Watchdog timer mode register Oscillation stabilization time selection register Note 3 IF0 MK0 WDTM OSTS FFFBH Processor clock control register PCC 02H Notes 1. Specify address FF10H directly for 16-bit access. 2. This value is 04H only after a power-on-clear reset. 3. PD789860 Subseries only 48 User's Manual U14826EJ4V0UD CHAPTER 4 CPU ARCHITECTURE 4.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination address information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E)). 4.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) to branch. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes the sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 PC + 15 8 7 S jdisp8 15 PC When S = 0, indicates that all bits are "0". When S = 1, indicates that all bits are "1". 0 6 0 0 ... PC is the start address of the next instruction of a BR instruction. User's Manual U14826EJ4V0UD 49 CHAPTER 4 CPU ARCHITECTURE 4.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions 7 CALL or BR Low addr. High addr. 0 15 PC 87 0 4.3.3 Table indirect addressing [Function] The table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH. [Illustration] 7 Instruction code 0 6 1 5 ta4-0 1 0 0 15 Effective address 0 0 0 0 0 0 0 8 0 7 0 6 1 5 10 0 7 Memory (Table) Low addr. 0 Effective address + 1 High addr. 15 PC 8 7 0 50 User's Manual U14826EJ4V0UD CHAPTER 4 CPU ARCHITECTURE 4.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp A 0 7 X 0 15 PC 8 7 0 User's Manual U14826EJ4V0UD 51 CHAPTER 4 CPU ARCHITECTURE 4.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 4.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !FE00H; When setting !addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 OP Code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 OP code addr16 (low) addr16 (high) 0 Memory 52 User's Manual U14826EJ4V0UD CHAPTER 4 CPU ARCHITECTURE 4.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal highspeed RAM is mapped at FE20H to FEFFH and the special function registers (SFR) are mapped at FF00H to FF1FH. The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below. [Operand format] Identifier saddr saddrp Description Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data (even address only) [Description example] MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 0 90H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] 7 OP code saddr-offset 0 Short direct memory 15 Effective address 1 1 1 1 1 1 1 8 0 When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1. User's Manual U14826EJ4V0UD 53 CHAPTER 4 CPU ARCHITECTURE 4.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing. [Operand format] Identifier sfr Description Special function register name [Description example] MOV PM0, A; When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [Illustration] 7 OP code sfr-offset 0 SFR 15 Effective address 1 1 1 1 1 1 1 87 1 0 54 User's Manual U14826EJ4V0UD CHAPTER 4 CPU ARCHITECTURE 4.4.4 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format] Identifier r rp X, A, C, B, E, D, L, H AX, BC, DE, HL Description `r' and `rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; When selecting the C register for r Instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 Register specify code INCW DE; When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specify code User's Manual U14826EJ4V0UD 55 CHAPTER 4 CPU ARCHITECTURE 4.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [DE], [HL] Description [Description example] MOV A, [DE]; When selecting register pair [DE] Instruction code 0 0 1 0 1 0 1 1 [Illustration] 15 DE D 7 The contents of addressed memory are transferred 7 A 0 87 E 0 Memory address specified by register pair DE 0 56 User's Manual U14826EJ4V0UD CHAPTER 4 CPU ARCHITECTURE 4.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [HL+byte] Description [Description example] MOV A, [HL+10H]; When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 4.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt request generation. Stack addressing can be used to access the internal high-speed RAM area only. [Description example] In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 User's Manual U14826EJ4V0UD 57 CHAPTER 5 EEPROM (DATA MEMORY) 5.1 Memory Space Besides internal high-speed RAM, the PD789860, 789861 Subseries have 32 x 8 bits of electrically erasable PROM (EEPROM) on-chip as data memory. Unlike normal RAM, EEPROM can maintain its contents even if its power supply is cut. EPROM, its contents can be electrically erased without using ultraviolet rays. In addition, unlike 5.2 EEPROM Configuration EEPROM consists of the EEPROM itself and a control section. The control section consists of EEPROM write control register 10 (EEWC10) which controls EEPROM writing and a part that detects the termination of writing and generates an interrupt request signal (INTEE0). Figure 5-1. EEPROM Block Diagram Internal bus EEPROM write control register 10 (EEWC10) Data latch EWCS102 EWCS101 EWCS100 ERE10 EWST10 EWE10 fX/23 to fX/28 EEPROM timer Address latch EEPROM (32 x 8 bits) Read/write controller INTEE0 Prescaler 8-bit timer 40 output 5.3 EEPROM Control Register EEPROM is controlled by EEPROM write control register 10 (EEWC10). EEWC10 is the register that sets the EEPROM count clock selection, and EEPROM write control. EEWC10 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 08H. Figure 5-2 shows the format of EEPROM write control register 10. Tables 5-1 and 5-2 show EEPROM write times. 58 User's Manual U14826EJ4V0UD CHAPTER 5 EEPROM (DATA MEMORY) Figure 5-2. Format of EEPROM Write Control Register 10 Symbol EEWC10 7 0 6 5 4 3 1 <2> ERE10 <1> EWST10 <0> EWE10 Address After reset FFD8H 08H R/W R/W Note EWCS102 EWCS101 EWCS100 EWCS102 EWCS101 EWCS100 EEPROM timer count clock selection When operating at fX = 5.0 MHz When operating at fCC = 1.0 MHz fCC/2 (125 kHz) fCC/2 (62.5 kHz) fCC/2 (31.3 kHz) fCC/2 (15.6 kHz) fCC/2 (7.81 kHz) fCC/2 (3.91 kHz) 8 7 6 5 4 3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fX/2 (625 kHz) fX/2 (313 kHz) fX/2 (156 kHz) fX/2 (78.1 kHz) fX/2 (39.1 kHz) fX/2 (19.5 kHz) Output of 8-bit timer 40 Setting prohibited 8 7 6 5 4 3 ERE10 0 0 1 1 EWE10 0 1 0 1 Write Disabled Read Disabled Remarks EEPROM is in standby state (low power consumption mode) Setting prohibited Disabled Enabled Enabled Enabled EWST10 0 1 EEPROM write status flag Not writing to EEPROM (EEPROM can be read or written. However, writing is disabled if EWE10 = 0.) Writing to EEPROM (EEPROM cannot be read or written.) Note Bit 1 is read only. Caution Be sure to clear bit 3 to 1 and bit 7 to 0. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) User's Manual U14826EJ4V0UD 59 CHAPTER 5 EEPROM (DATA MEMORY) Table 5-1. EEPROM Write Time (When Operating at fX = 5.0 MHz) EWCS102 0 0 0 0 1 1 1 1 EWCS101 0 0 1 1 0 0 1 1 EWCS100 0 1 0 1 0 1 0 1 3 EEPROM Timer Count Clock fX/2 (625 kHz) fX/2 (313 kHz) fX/2 (156 kHz) fX/2 (78.1 kHz) fX/2 (39.1 kHz) fX/2 (19.5 kHz) Output of 8-bit timer 40 Setting prohibited 8 7 6 5 4 3 EEPROM Data Write Time 2 /fX x 145 (setting prohibited) 2 /fX x 145 (setting prohibited) 4 Note 1 Note 2 Note 2 2 /fX x 145 (setting prohibited) 5 Note 2 2 /fX x 145 (setting prohibited) 6 Note 2 2 /fX x 145 (3.71 ms) 7 2 /fX x 145 (setting prohibited) 8 Note 2 Output of 8-bit timer 40 x 145 Notes 1. Be sure to set the EEPROM write time within the range of 3.3 to 6.6 ms. 2. During operation at fX = 5.0 MHz, setting is prohibited because the condition that an EEPROM write time must be between 3.3 and 6.6 ms is not satisfied. Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) Table 5-2. EEPROM Write Time (When Operating at fCC = 1.0 MHz) EWCS102 0 0 0 0 1 1 1 1 EWCS101 0 0 1 1 0 0 1 1 EWCS100 0 1 0 1 0 1 0 1 3 EEPROM Timer Count Clock fCC/2 (125 kHz) fCC/2 (62.5 kHz) fCC/2 (31.3 kHz) fCC/2 (15.6 kHz) fCC/2 (7.81 kHz) fCC/2 (3.91 kHz) Output of 8-bit timer 40 Setting prohibited 8 7 6 5 4 3 EEPROM Data Write Time 2 /fCC x 145 (setting prohibited) 2 /fCC x 145 (setting prohibited) 4 Note 1 Note 2 Note 2 2 /fCC x 145 (4.64 ms) 5 2 /fCC x 145 (setting prohibited) 6 Note 2 2 /fCC x 145 (setting prohibited) 7 Note 2 2 /fCC x 145 (setting prohibited) 8 Note 2 Output of 8-bit timer 40 x 145 Notes 1. Be sure to set the EEPROM write time within the range of 3.3 to 6.6 ms. 2. During operation at fCC = 1.0 MHz, setting is prohibited because the condition that an EEPROM write time must be between 3.3 and 6.6 ms is not satisfied. Remark fCC: System clock oscillation frequency (RC oscillation) 60 User's Manual U14826EJ4V0UD CHAPTER 5 EEPROM (DATA MEMORY) 5.4 Notes for EEPROM Writing The following caution points pertain to writing to EEPROM. (1) When fetching an instruction from EEPROM or stopping the system clock oscillator, be sure to do so after setting EEPROM to write-disabled (EWE10 = 0). (2) Set the count clock in a state in which the selected clock is operating (oscillating). If the selected count clock is stopped, there is no transition to the state in which writing is possible even if the clock operation is subsequently started and EEPROM is set to write-enabled (EWE10 = 1). (3) Be sure to set the EEPROM write time within the range of 3.3 to 6.6 ms. (4) When setting ERE10 and EWE10, be sure to use the following procedure. If you set these using other than the following procedure, there is no transition to the state in which writing to EEPROM is possible. <1> Set ERE10 to 1 (In a state in which EWE10 = 0) <2> Set EWE10 to 1 (In a state in which ERE10 = 1) <3> Wait 1 ms or more using software <4> Shift to state in which writing to EEPROM is possible ERE10 A EWE10 1 ms or more B C D A (ERE10 = 1): Transition to state in which reading is possible B (EWE10 = 1): Set count clock before this point. C: D: Transition to state in which writing is possible When ERE10 is cleared (ERE10 = 0), EWE10 is also cleared (EWE10 = 0). Reading or writing is not possible in this state. (5) When performing a write to EEPROM, execute it after confirming that EWST10 = 0. If a write is executed to EEPROM when EWST10 = 1, the instruction is ignored. User's Manual U14826EJ4V0UD 61 CHAPTER 5 EEPROM (DATA MEMORY) (6) Do not execute the following operations while writing to EEPROM, as execution will cause the EEPROM cell value at that address to become undefined. * Turn off the power * Execute a reset * Clear ERE10 to 0 * Clear EWE10 to 0 * Switch the EEPROM timer count clock (7) Do not execute the following operation while writing to EEPROM after selecting system clock division for the EEPROM timer count clock, as execution will cause the EEPROM cell value at that address to become undefined. * Execute a STOP instruction (8) Do not execute the following operations while writing to EEPROM after selecting 8-bit timer 40 output for the EEPROM timer count clock, as execution will cause the EEPROM cell value at that address to become undefined. * Execute a STOP instruction * Stop 8-bit timer 40 timer output * Stop 8-bit timer 40 operation (9) Do not execute the following operations while writing to or reading from EEPROM, as execution will cause the EEPROM data read next to become undefined, and a CPU inadvertent program loop could result. * Clear ERE10 to 0 * Execute a write to EEPROM (10) When not writing to or reading from EEPROM, it is possible to enter low-power consumption mode by clearing ERE10 to 0. In the ERE10 = 1 state, a current of about 0.27 mA (VDD = 3.6 V) is always flowing. If an instruction to read from EEPROM is then executed, a further 0.9 mA current will flow, increasing the total current flow at this time to approximately 1.17 mA (VDD = 3.6 V). In the ERE10 = 1, EWE10 = 1 state, a current of about 0.3 mA (VDD = 3.6 V) is always flowing. If an instruction to write to EEPROM is then executed, a further 0.7 mA current will flow, and if an instruction to read from EEPROM is executed, a further 0.9 mA current will flow, increasing the total current flow at this time to approximately 1.0 mA (VDD = 3.6 V) for the former case and 1.2 mA (VDD = 3.6 V) for the latter. (11) Execution of a STOP instruction causes an automatic change to low-power consumption mode, regardless of the ERE10 and EWE10 settings. The states of ERE10 and EWE10 at the time are maintained. During the wait time following STOP mode release, a current of approximately 300 A (VDD = 3.6 V) flows. Executing a HALT instruction does not change the mode to low-power consumption mode. 62 User's Manual U14826EJ4V0UD CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The PD789860, 789861 Subseries is provided with the ports shown in Table 6-1. These ports enable several types of control. These ports, while originally designed as digital input/output ports, have alternate functions. For the alternate functions, see CHAPTER 3 PIN FUNCTIONS. Table 6-1. Port Functions Name Port 0 Port 2 Port 4 Pin Name P00 to P07 P20, P21 P40 to P43 Function I/O port. Input/output can be specified in 1-bit units. I/O port. Input/output can be specified in 1-bit units. Input-only port. Mask ROM versions can specify an on-chip pull-up resistor by means of the mask option. 6.2 Port Configuration Ports include the following hardware. Table 6-2. Configuration of Port Item Control registers Ports Pull-up resistors Port mode registers (PMm: m = 0, 2) Total: 14 (CMOS I/O: 10, CMOS input: 4) Mask ROM version: 4 (mask option control only) EEPROM version: None Configuration User's Manual U14826EJ4V0UD 63 CHAPTER 6 PORT FUNCTIONS 6.2.1 Port 0 This is an 8-bit I/O port with an output latch. Port 0 can be set to input or output mode in 1-bit units by using port mode register 0 (PM0). RESET input sets port 0 to input mode. Figure 6-1 shows a block diagram of port 0. Figure 6-1. Block Diagram of P00 to P07 RD Internal bus WRPORT Output latch (P00 to P07) WRPM Selector P00 to P07 PM00 to PM07 PM: RD: WR: Port mode register Port 0 read signal Port 0 write signal 64 User's Manual U14826EJ4V0UD CHAPTER 6 PORT FUNCTIONS 6.2.2 Port 2 This is a 2-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (PM2). RESET input sets port 2 to input mode. Figures 6-2 and 6-3 show block diagrams of port 2. Figure 6-2. Block Diagram of P20 RD WRPORT Internal bus Output latch (P20) WRPM Selector P20/TMO /BSFO PM20 Alternate function Alternate function PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal User's Manual U14826EJ4V0UD 65 CHAPTER 6 PORT FUNCTIONS Figure 6-3. Block Diagram of P21 Alternate function RD Selector Internal bus WRPORT Output latch (P21) WRPM P21/TMI PM21 PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal 6.2.3 Port 4 This is a 4-bit input-only port. Mask ROM versions can specify an on-chip pull-up resistor by means of the mask option. The port is also used as key return input. RESET input sets port 4 to input mode. Figure 6-4 shows a block diagram of port 4. Figure 6-4. Block Diagram of P40 to P43 VDD Alternate function Internal bus RD Mask option resistor (mask ROM versions only. EEPROM versions have no pull-up resistor.) P40/KR10 to P43/KR13 RD: Port 4 read signal 66 User's Manual U14826EJ4V0UD CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following registers are used to control the ports. * Port mode registers (PM0, PM2) (1) Port mode registers (PM0, PM2) PM0 and PM2 are registers for which port I/O settings can be controlled in 1-bit units. Each port mode register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When port pins are used for alternate functions, the corresponding port mode register and output latch must be set or reset as described in Table 6-3. Figure 6-5. Format of Port Mode Register Symbol PM0 7 PM07 6 PM06 5 PM05 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00 Address FF20H After reset FFH R/W R/W PM2 1 1 1 1 1 1 PM21 PM20 FF22H FFH R/W PMmn 0 1 Output mode (output buffer on) Input mode (output buffer off) Pmn pin input/output mode selection (m = 0, 2, n = 0 to 7) Table 6-3. Port Mode Register and Output Latch Settings for Using Alternate Functions Pin Name Name P20 TMO BSFO P21 TMI Alternate Function Input/Output Output Output input 0 0 1 0 0 x PMxx Pxx Remark x: PMxx: Pxx: don't care Port mode register Port output latch User's Manual U14826EJ4V0UD 67 CHAPTER 6 PORT FUNCTIONS 6.4 Operation of Port Functions The operation of a port differs depending on whether the port is set to input or output mode, as described below. 6.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port. The data once written to the output latch is retained until new data is written to the output latch. (2) In input mode A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is not changed because the output buffer is OFF. The data once written to the output latch is retained until new data is written to the output latch. Caution A 1-bit memory manipulation instruction is executed to manipulate one bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined. 6.4.2 Reading from I/O port (1) In output mode The contents of the output latch can be read by using a transfer instruction. The contents of the output latch are not changed. (2) In input mode The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed. 6.4.3 Arithmetic operation of I/O port (1) In output mode An arithmetic operation can be performed with the contents of the output latch. The result of the operation is written to the output latch. The contents of the output latch are output from the port pins. The data once written to the output latch is retained until new data is written to the output latch. (2) In input mode The contents of the output latch become undefined. However, the status of the pin is not changed because the output buffer is OFF. Caution A 1-bit memory manipulation instruction is executed to manipulate one bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined. 68 User's Manual U14826EJ4V0UD CHAPTER 7 CLOCK GENERATOR (PD789860 SUBSERIES) 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is used. * System clock (crystal/ceramic) oscillator This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction. 7.2 Clock Generator Configuration The clock generator includes the following hardware. Table 7-1. Configuration of Clock Generator Item Control register Oscillator Processor clock control register (PCC) Crystal/ceramic oscillator Configuration Figure 7-1. Block Diagram of Clock Generator Prescaler X1 X2 System clock oscillator Clock to peripheral hardware fX Prescaler fX 22 Selector STOP Standby controller Wait controller CPU clock (fCPU) PCC0 Processor clock control register (PCC) Internal bus User's Manual U14826EJ4V0UD 69 CHAPTER 7 CLOCK GENERATOR (PD789860 SUBSERIES) 7.3 Clock Generator Control Register The clock generator is controlled by the following register: * Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC selects the CPU clock and the division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 02H. Figure 7-2. Format of Processor Clock Control Register Symbol PCC 7 0 6 0 5 0 4 0 3 0 2 0 1 PCC0 0 0 Address FFFBH After reset 02H R/W R/W PCC0 CPU clock (fCPU) selection Minimum instruction execution time: 2/fCPU At fX = 5.0 MHz operation 0 1 fX fX/2 2 0.4 s 1.6 s Caution Remark Be sure to clear bits 0 and 2 to 7 to 0. fX: System clock oscillation frequency 70 User's Manual U14826EJ4V0UD CHAPTER 7 CLOCK GENERATOR (PD789860 SUBSERIES) 7.4 System Clock Oscillators 7.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin. Figure 7-3 shows the external circuit of the system clock oscillator. Figure 7-3. External Circuit of System Clock Oscillator (a) Crystal or ceramic oscillation VSS X1 External clock (b) External clock X1 X2 Crystal or ceramic resonator X2 Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in Figure 7-3 to avoid an adverse effect from wiring capacitance. * * * * Keep the wiring length as short as possible. Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. Do not fetch signals from the oscillator. User's Manual U14826EJ4V0UD 71 CHAPTER 7 CLOCK GENERATOR (PD789860 SUBSERIES) 7.4.2 Examples of incorrect resonator connection Figure 7-4 shows examples of incorrect resonator connections. Figure 7-4. Examples of Incorrect Resonator Connection (1/2) (a) Wiring too long (b) Crossed signal line PORTn (n = 0, 2, 4) VSS X1 X2 VSS X1 X2 (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD PORTn (n = 0, 2, 4) VSS X1 X2 VSS X1 X2 High current A B High current C 72 User's Manual U14826EJ4V0UD CHAPTER 7 CLOCK GENERATOR (PD789860 SUBSERIES) Figure 7-4. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched VSS X1 X2 7.4.3 Frequency divider The frequency divider divides the system clock oscillator output (fX) and generates clocks. User's Manual U14826EJ4V0UD 73 CHAPTER 7 CLOCK GENERATOR (PD789860 SUBSERIES) 7.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode: * System clock * CPU clock fX fCPU * Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) as follows: (a) The slow mode (1.6 s: at 5.0 MHz operation) of the system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is stopped. (b) Two types of minimum instruction execution time (fCPU) (0.4 s, 1.6 s: at 5.0 MHz operation) can be selected by setting PCC. (c) (d) Two standby modes, STOP and HALT, can be used. The clock for the peripheral hardware is generated by dividing the frequency of the system clock. Therefore, the peripheral hardware stops when the system clock stops (except for an external input clock). 74 User's Manual U14826EJ4V0UD CHAPTER 7 CLOCK GENERATOR (PD789860 SUBSERIES) 7.6 Changing Setting of CPU Clock 7.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC0) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (see Table 7-2). Table 7-2. Maximum Time Required for Switching CPU Clock Set Value Before Switching PCC0 Set Value After Switching PCC0 0 0 1 2 clocks 4 clocks PCC0 1 Remark Two clocks are the minimum instruction execution time of the CPU clock before switching. 7.6.2 Switching CPU clock The following figure illustrates how the CPU clock is switched. Figure 7-5. Switching Between System Clock and CPU Clock VDD RESET CPU Clock Slow operation Fast operation Wait (6.55 ms: @5.0 MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the oscillation stabilization time (215/fX) is automatically secured. After that, the CPU starts instruction execution at the slow speed of the system clock (1.6 s: @5.0 MHz operation). <2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at the high speed has elapsed, the processor clock control register (PCC) is rewritten so that the high-speed operation can be selected. User's Manual U14826EJ4V0UD 75 CHAPTER 8 CLOCK GENERATOR (PD789861 SUBSERIES) 8.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is used. * System clock (RC) oscillator This circuit oscillates at 1.0 MHz 15%. Oscillation can be stopped by executing the STOP instruction. 8.2 Clock Generator Configuration The clock generator includes the following hardware. Table 8-1. Configuration of Clock Generator Item Control register Oscillator Processor clock control register (PCC) RC oscillator Configuration Figure 8-1. Block Diagram of Clock Generator Prescaler CL1 CL2 System clock oscillator Clock to peripheral hardware fCC Prescaler fCC 22 Selector STOP Standby controller Wait controller CPU clock (fCPU) PCC0 Processor clock control register (PCC) Internal bus 76 User's Manual U14826EJ4V0UD CHAPTER 8 CLOCK GENERATOR (PD789861 SUBSERIES) 8.3 Clock Generator Control Register The clock generator is controlled by the following register: * Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC selects the CPU clock and the division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 02H. Figure 8-2. Format of Processor Clock Control Register Symbol PCC 7 0 6 0 5 0 4 0 3 0 2 0 1 PCC0 0 0 Address FFFBH After reset 02H R/W R/W PCC0 CPU clock (fCPU) selection Minimum instruction execution time: 2/fCPU At fCC = 1.0 MHz operation 0 1 fCC fCC/2 2 2.0 s 8.0 s Caution Remark Be sure to clear bits 0 and 2 to 7 to 0. fCC: System clock oscillation frequency User's Manual U14826EJ4V0UD 77 CHAPTER 8 CLOCK GENERATOR (PD789861 SUBSERIES) 8.4 System Clock Oscillators 8.4.1 System clock oscillator The system clock oscillator is oscillated by the resistor (R) and capacitor (C) (1.0 MHz TYP.) connected across the CL1 and CL2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the CL1 pin, and input the inverted signal to the CL2 pin. Figure 8-3 shows the external circuit of the system clock oscillator. Figure 8-3. External Circuit of System Clock Oscillator (a) RC oscillation CL1 C R CL2 VSS CL2 External clock (b) External clock CL1 Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in Figure 8-3 to avoid an adverse effect from wiring capacitance. * * * * Keep the wiring length as short as possible. Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. Do not fetch signals from the oscillator. 78 User's Manual U14826EJ4V0UD CHAPTER 8 CLOCK GENERATOR (PD789861 SUBSERIES) 8.4.2 Examples of incorrect resonator connection Figure 8-4 shows examples of incorrect resonator connections. Figure 8-4. Examples of Incorrect Resonator Connection (1/2) (a) Wiring too long (b) Crossed signal line PORTn (n = 0, 2, 4) CL1 CL2 VSS CL1 CL2 VSS (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD PORTn (n = 0, 2, 4) CL1 CL2 VSS CL1 High current CL2 VSS A High current B User's Manual U14826EJ4V0UD 79 CHAPTER 8 CLOCK GENERATOR (PD789861 SUBSERIES) Figure 8-4. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched CL1 CL2 VSS 8.4.3 Frequency divider The frequency divider divides the system clock oscillator output (fCC) and generates clocks. 80 User's Manual U14826EJ4V0UD CHAPTER 8 CLOCK GENERATOR (PD789861 SUBSERIES) 8.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode: * System clock * CPU clock fCC fCPU * Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) as follows: (a) The slow mode (8.0 s: at 1.0 MHz operation) of the system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is stopped. (b) Two types of minimum instruction execution time (fCPU) (2.0 s, 8.0 s: at 1.0 MHz operation) can be selected by the PCC setting. (c) (d) Two standby modes, STOP and HALT, can be used. The clock for the peripheral hardware is generated by dividing the frequency of the system clock. Therefore, the peripheral hardware stops when the system clock stops (except for an external input clock). User's Manual U14826EJ4V0UD 81 CHAPTER 8 CLOCK GENERATOR (PD789861 SUBSERIES) 8.6 Changing Setting of CPU Clock 8.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC0) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (see Table 8-2). Table 8-2. Maximum Time Required for Switching CPU Clock Set Value Before Switching PCC0 Set Value After Switching PCC0 0 0 1 2 clocks 4 clocks PCC0 1 Remark Two clocks are the minimum instruction execution time of the CPU clock before switching. 8.6.2 Switching CPU clock The following figure illustrates how the CPU clock is switched. Figure 8-5. Switching Between System Clock and CPU Clock VDD RESET CPU Clock Slow operation Fast operation Wait (128 s: @1.0 MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the oscillation stabilization time (27/fCC) is automatically secured. After that, the CPU starts instruction execution at the slow speed of the system clock (8.0 s: @1.0 MHz operation). <2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at the high speed has elapsed, the processor clock control register (PCC) is rewritten so that the high-speed operation can be selected. 82 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 9.1 8-Bit Timers 30, 40 Functions The PD789860, 789861 Subseries have on chip an 8-bit timer (timer 30) (1 channel) and an 8-bit timer/event counter (timer 40) (1 channel). The operation modes shown in the table below are possible by means of mode register settings. Table 9-1. Mode List Channel Mode 8-bit timer counter mode (discrete mode) 16-bit timer counter mode (cascade connection mode) Carrier generator mode PWM output mode x Timer 30 Timer 40 (1) 8-bit timer counter mode (discrete mode) The following functions can be used. * * * 8-bit resolution interval timer 8-bit resolution external event counter (timer 40 only) 8-bit resolution square wave output 16-bit timer counter mode (cascade connection mode) Operates as a 16-bit timer/event counter due to cascade connection. The following functions can be used. * 16-bit resolution interval timer * 16-bit resolution external event counter * 16-bit resolution square wave output (2) (3) Carrier generator mode In this mode, the carrier clock generated by timer 40 is output in the cycle set by timer 30. (4) PWM output mode (timer 40 only) Outputs a pulse of an arbitrary duty factor set by timer 40. User's Manual U14826EJ4V0UD 83 CHAPTER 9 8-BIT TIMERS 30 AND 40 9.2 8-Bit Timers 30, 40 Configuration The 8-bit timers include the following hardware. Table 9-2. Configuration of 8-Bit Timers 30, 40 Item Timer counter Registers Timer output Control registers 8 bits x 2 (TM30, TM40) Compare registers: 8 bits x 3 (CR30, CR40, CRH40) 1 (TMO) 8-bit timer mode control register 30 (TMC30) 8-bit timer mode control register 40 (TMC40) Carrier generator output control register 40 (TCA40) Port mode register 2 (PM2) Port 2 (P2) Configuration 84 User's Manual U14826EJ4V0UD Figure 9-1. Timer 30 Block Diagram Internal bus 8-bit timer mode control register 30 (TMC30) TCE30 TCL302 TCL301 TCL300 TMD301 TMD300 Decoder Selector (A) Bit 7 of TM40 (From Figure 9-2 (A)) User's Manual U14826EJ4V0UD 8-bit compare register 30 (CR30) CHAPTER 9 8-BIT TIMERS 30 AND 40 Match (G) To Figure 9-2 (G) Timer 30 match signal (in carrier generator mode) fCLK/26 fCLK/28 Timer 40 interrupt request signal (From Figure 9-2 (B)) (B) Carrier clock (From Figure 9-2 (C)) (C) Selector 8-bit timer counter 30 (TM30) Clear OVF Selector Internal reset signal (D) From Figure 9-2 (D) Count operation start signal (in cascade connection mode) Selector Cascade connection mode INTTM30 (E) From Figure 9-2 (E) Timer 40 match signal (in cascade connection mode) (F) To Figure 9-2 (F) Timer 30 match signal (in cascade connection mode) Remark fCLK: fX or fCC 85 Prescaler TMI/2 TMI/2 2 Selector 86 8-bit timer mode control register 40 (TMC40) TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 Decoder User's Manual U14826EJ4V0UD Figure 9-2. Timer 40 Block Diagram Internal bus Carrier generator output control register 40 (TCA40) 8-bit compare register 40 (CR40) 8-bit compare register H40 (CRH40) RMC40 NRZB40 NRZ40 Selector From Figure 9-1 (G) Timer counter match (G) signal from timer 30 (in carrier generator mode) CHAPTER 9 8-BIT TIMERS 30 AND 40 Match fCLK fCLK/22 TMI/P21 8-bit timer counter 40 (TM40) Clear Carrier generator mode PWM mode OVF F/F Output controllerNote TMO/P20/BSFO To Figure 9-1 (C) (C) Carrier clock Reset Cascade connection mode TMI/23 To Figure 9-1 (A) Bit 7 of TM40 (A) (in cascade connection mode) Internal reset signal (D) To Figure 9-1 (D) Count operation start signal to timer 30 (in cascade connection mode) (E) To Figure 9-1 (E) TM40 timer counter match signal (in cascade connection mode) INTTM40 To Figure 9-1 (B) Timer 40 interrupt request signal (B) count clock input signal to TM30 (F) From Figure 9-1 (F) TM30 match signal (in cascade connection mode) Note For details, see Figure 9-3. Remark fCLK: fX or fCC CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-3. Block Diagram of Output Controller (Timer 40) TOE40 RMC40 NRZ40 P20 output latch PM20 Selector F/F TMO/P20/ BSFO Carrier clock Carrier generator mode (1) 8-bit compare register 30 (CR30) This register is an 8-bit register that always compares the count value of 8-bit timer counter 30 (TM30) with the value set in CR30 and generates an interrupt request (INTTM30) if they match. CR30 is set with an 8-bit memory manipulation instruction. RESET input makes this register undefined. Caution CR30 cannot be used in PWM output mode. (2) 8-bit compare register 40 (CR40) This register is an 8-bit register that always compares the count value of 8-bit timer counter 40 (TM40) with the value set in CR40 and generates an interrupt request (INTTM40) if they match. In addition, when cascade-connected to TM30 and used as a 16-bit timer/event counter, an interrupt request (INTTM40) is generated only if TM30 matches with CR30 and TM40 matches with CR40 simultaneously (INTTM30 is not generated). In carrier generator mode or PWM output mode, set the low-level width of the timer output. CR40 is set with an 8-bit memory manipulation instruction. RESET input makes this register undefined. (3) 8-bit compare register H40 (CRH40) In carrier generator mode or PWM output mode, writing a CRH40 value sets the width of high level timer output. The value set in CRH40 is constantly compared with the TM40 count value, and an interrupt request (INTTM40) is generated if they match. CRH40 is set with an 8-bit memory manipulation instruction. RESET input makes this register undefined. (4) 8-bit timer counters 30 and 40 (TM30, TM40) These 8-bit registers count pulse counts. Each of TM30 and TM40 is read with an 8-bit memory manipulation instruction. RESET input clears these registers to 00H. The conditions under which TM30 and TM40 are cleared to 00H are shown next. User's Manual U14826EJ4V0UD 87 CHAPTER 9 8-BIT TIMERS 30 AND 40 (a) Discrete mode (i) TM30 * Reset * Clearing of TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) to 0 * Match of TM30 and CR30 * TM30 count value overflow (ii) TM40 * Reset * Clearing of TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) to 0 * Match of TM40 and CR40 * TM40 count value overflow (b) Cascade connection mode (TM30, TM40 simultaneously cleared to 00H) * Reset * Clearing of the TCE40 flag to 0 * Simultaneous match of TM30 with CR30 and TM40 with CR40 * TM30 and TM40 count values overflow simultaneously (c) Carrier generator/PWM output mode (TM40 only) * Reset * Clearing of the TCE40 flag to 0 * Match of TM40 and CR40 * Match of TM40 and CRH40 * TM40 count value overflow 9.3 8-Bit Timers 30, 40 Control Registers The 8-bit timers are controlled by the following five registers. * 8-bit timer mode control register 30 (TMC30) * 8-bit timer mode control register 40 (TMC40) * Carrier generator output control register 40 (TCA40) * Port mode register 2 (PM2) * Port 2 (P2) 88 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 (1) 8-bit timer mode control register 30 (TMC30) TMC30 is the register that controls the setting of the timer 30 count clock and the setting of the operating mode. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-4. Format of 8-Bit Timer Mode Control Register 30 Symbol TMC30 <7> TCE30 6 0 5 TCL302 4 TCL301 3 TCL300 2 TMD301 1 TMD300 0 0 Address After reset FF52H 00H R/W R/W TCE30 0 1 TM30 count operation control Clears TM30 count value and halt operation Starts count operation Note 1 TCL302 TCL301 TCL300 Selection of timer 30 count clock When operating at fX = 5.0 MHz When operating at fCC = 1.0 MHz fCC/2 (15.6 kHz) fCC/2 (3.91 kHz) 8 6 0 0 0 0 0 0 1 1 Other than above 0 1 0 1 fX/2 (78.1 kHz) fX/2 (19.5 kHz) Timer 40 match signal Carrier clock generated by timer 40 Setting prohibited 8 6 TMD301 0 0 0 0 TMD300 0 1 0 0 TMD401 0 0 1 1 TMD400 0 1 1 0 Selection of timer 30, timer 40 operating mode Discrete mode Cascade connection mode Carrier generator mode PWM output mode Setting prohibited Note 2 Other than above Notes 1. In cascade connection mode, since count operations are controlled by TCE40 (bit 7 of TMC40), TCE30 is ignored even if it is set. 2. The selection of operating mode is made by combining the two registers TMC30 and TMC40. Cautions 1. Be sure to clear bits 0 and 6 to 0. 2. In cascade connection mode, timer 40 output signal is forcibly selected for count clock. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) User's Manual U14826EJ4V0UD 89 CHAPTER 9 8-BIT TIMERS 30 AND 40 (2) 8-bit timer mode control register 40 (TMC40) TMC40 is the register that controls the setting of the timer 40 count clock and the setting of the operating mode. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-5. Format of 8-Bit Timer Mode Control Register 40 Symbol TMC40 <7> TCE40 6 0 5 TCL402 4 TCL401 3 TCL400 2 TMD401 1 TMD400 <0> TOE40 Address After reset FF56H 00H R/W R/W TCE40 0 TM40 count operation control Note 1 Clears TM40 count value and halt operation (in cascade connection mode, the TM30 count value is simultaneously cleared as well.) Starts count operation (in cascade connection mode, the TM30 count operation is simultaneously started as well.) 1 TCL402 TCL401 TCL400 Selection of timer 40 count clock When operating at fX = 5.0 MHz When operating at fCC = 1.0 MHz fCC (1.0 MHz) fCC/2 (250 kHz) 2 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 fX (5.0 MHz) fX/2 (1.25 MHz) fTMI fTMI/2 fTMI/2 fTMI/2 2 2 3 TMD301 0 0 0 0 TMD300 0 1 0 0 TMD401 0 0 1 1 TMD400 0 1 1 0 Selection of timer 30, timer 40 operating mode Discrete mode Cascade connection mode Carrier generator mode PWM output mode Setting prohibited Note 2 Other than above TOE40 0 1 Output disabled Output enabled (port mode) Timer output control Notes 1. In cascade connection mode, since count operations are controlled by TCE40, TCE30 (bit 7 of TMC30) is ignored even if it is set. 2. The selection of operating mode is made by combining the two registers TMC30 and TMC40. Caution Be sure to clear bit 6 to 0. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) 3. fTMI: External clock input from TMI/P21 pin 90 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 (3) Carrier generator output control register 40 (TCA40) TCA40 is used to set the timer output data in the carrier generator mode. This register is set with an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-6. Format of Carrier Generator Output Control Register 40 Symbol TCA40 7 0 6 0 5 0 4 0 3 0 2 RMC40 1 NRZB40 0 NRZ40 Address After reset FF57H 00H R/W W RMC40 0 1 Remote controller output control When NRZ40 = 1, a carrier pulse is output to the TMO/P20/BSFO pin When NRZ40 = 1, a high level is output to the TMO/P20/BSFO pin NRZB40 This bit stores the data that NRZ40 will output next. Data is transferred to NRZ40 upon the generation of a timer 30 match signal. Input the necessary value in NRZB40 in advance by program. NRZ40 0 1 No return zero data A low level is output (the carrier clock is stopped) A carrier pulse or high level is output Cautions 1. Be sure to clear bits 3 to 7 to 0. 2. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8bit memory manipulation instruction to set TCA40. 3. The NRZ40 flag can be written only when carrier generator output is stopped (TOE40 = 0). The data cannot be overwritten when TOE40 = 1. 4. When the carrier generator is stopped once and then started again, NRZB40 does not hold the previous data. manipulation instruction. 5. To enable operation in the carrier generator mode, set a value to the compare registers (CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40 flags in advance. Otherwise, the signal of the timer match circuit will become unstable and the NRZ40 flag will be undefined. 6. Note that the PD78E9860 and 78E9861 have the following restrictions (which do not apply to the mask ROM version and the PD78E9860A and 78E9861A). (a) While INTTM30 (interrupt generated by the match signal of timer 30) is being output, accessing TCA40 is prohibited. (b) Accessing TCA40 is prohibited while 8-bit timer/counter 30 (TM30) is 00H. To access TCA40 while TM30 = 00H, wait for more than half a period of the TM30 count clock and then rewrite TCA40. Re-set data to NRZB40. At this time, a 1-bit memory manipulation instruction must not be used. Be sure to use an 8-bit memory User's Manual U14826EJ4V0UD 91 CHAPTER 9 8-BIT TIMERS 30 AND 40 (4) Port mode register 2 (PM2) PM2 sets port 2 to input/output in 1-bit units. When using the P20/TMO/BSFO pin as a timer output, clear the PM20 and P20 output latch to 0. When using the P21/TMI pin as a timer input, set the PM21 to 1. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 9-7. Format of Port Mode Register 2 Symbol PM2 7 1 6 1 5 1 4 1 3 1 2 1 1 PM21 0 PM20 Address After reset FF22H FFH R/W R/W PM2m 0 1 Output mode (output buffer on) Input mode (output buffer off) P2m pin input/output mode (m = 0, 1) 92 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 9.4 8-Bit Timers 30, 40 Operation 9.4.1 Operation as 8-bit timer counter Timer 30 and timer 40 can independently be used as an 8-bit timer counter. The following modes can be used for the 8-bit timer counter. * * * (1) Interval timer with 8-bit resolution External event counter with 8-bit resolution (timer 40 only) Square wave output with 8-bit resolution (timer 40 only) Operation as interval timer with 8-bit resolution The interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register n0 (CRn0). To operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence. <1> Disable operation of 8-bit timer counter n0 (TMn0) (TCEn0 = 0). <2> Disable timer output of TMO (TOE40 = 0)Note. <3> Set a count value in CRn0. <4> Set the operation mode of timer n0 to 8-bit timer counter mode (see Figures 9-4 and 9-5). <5> Set the count clock for timer n0 (see Tables 9-3 to 9-6). <6> Enable the operation of TMn0 (TCEn0 = 1). When the count value of 8-bit timer counter n0 (TMn0) matches the value set in CRn0, TMn0 is cleared to 0 and continues counting. At the same time, an interrupt request signal (INTTMn0) is generated. Tables 9-3 to 9-6 show interval time, and Figures 9-8 to 9-13 show the timing of the interval timer operation. Note Timer 40 only Caution Remark Be sure to stop the timer operation before overwriting the count clock with different data. n = 3, 4 User's Manual U14826EJ4V0UD 93 CHAPTER 9 8-BIT TIMERS 30 AND 40 Table 9-3. Interval Time of Timer 30 (During fX = 5.0 MHz Operation) TCL302 TCL301 TCL300 0 0 0 0 0 1 0 1 0 6 Minimum Interval Time 2 /fX (12.8 s) 2 /fX (51.2 s) 8 14 Maximum Interval Time 2 /fX (3.28 ms) 2 /fX (13.1 ms) Input cycle of timer 40 match 8 signal x 2 Carrier clock cycle generated 8 by timer 40 x 2 16 6 Resolution 2 /fX (12.8 s) 2 /fX (51.2 s) 8 Input cycle of timer 40 match signal Input cycle of timer 40 match signal Carrier clock cycle generated by timer 40 0 1 1 Carrier clock cycle generated by timer 40 Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) Table 9-4. Interval Time of Timer 30 (During fCC = 1.0 MHz Operation) TCL302 TCL301 TCL300 0 0 0 0 0 1 0 1 0 6 Minimum Interval Time 2 /fCC (64 s) 2 /fCC (256 s) 8 14 Maximum Interval Time 2 /fCC (16.4 ms) 2 /fCC (65.5 ms) Input cycle of timer 40 match 8 signal x 2 Carrier clock cycle generated 8 by timer 40 x 2 16 6 Resolution 2 /fCC (64 s) 2 /fCC (256 s) 8 Input cycle of timer 40 match signal Input cycle of timer 40 match signal Carrier clock cycle generated by timer 40 0 1 1 Carrier clock cycle generated by timer 40 Remark fCC: System clock oscillation frequency (RC oscillation) Table 9-5. Interval Time of Timer 40 (During fX = 5.0 MHz Operation) TCL402 TCL401 TCL400 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Minimum Interval Time 1/fX (0.2 s) 2 /fX (0.8 s) 2 8 Maximum Interval Time 2 /fX (51.2 s) 2 /fX (204.8 s) 10 Resolution 1/fX (0.2 s) 2 /fX (0.8 s) 2 fTMI input cycle fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI input cycle x 2 8 fTMI input cycle 8 fTMI/2 input cycle x 2 2 fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI/2 input cycle x 2 fTMI/2 input cycle x 2 3 8 8 Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) Table 9-6. Interval Time of Timer 40 (During fCC = 1.0 MHz Operation) TCL402 TCL401 TCL400 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Minimum Interval Time 1/fCC (1.0 s) 2 /fCC (4.0 s) 2 8 Maximum Interval Time 2 /fCC (256 s) 2 /fCC (1024 s) 10 Resolution 1/fCC (1.0 s) 2 /fCC (4.0 s) 2 fTMI input cycle fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI input cycle x 2 8 fTMI input cycle 8 fTMI/2 input cycle x 2 2 fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI/2 input cycle x 2 fTMI/2 input cycle x 2 3 8 8 Remark fCC: System clock oscillation frequency (RC oscillation) 94 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) t Count clock TMn0 00H 01H N 00H Clear 01H N 00H Clear N 01H N 00H Clear 01H 00H CRn0 TCEn0 Count start INTTMn0 Interrupt acknowledgement TMONote Interval time Interval time Interrupt acknowledgement Interrupt acknowledgement Count stop Note Timer 40 only Remarks 1. Interval time: (N + 1) x t: N = 00H to FFH 2. n = 3, 4 Figure 9-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Cleared to 00H) Count clock TMn0 00H CRn0 00H TCEn0 Count start INTTMn0 TMONote Note Timer 40 only Remark n = 3, 4 User's Manual U14826EJ4V0UD 95 CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) Count clock TMn0 00H 01H FFH 00H Clear 01H FFH 00H Clear 01H FFH 00H Clear FFH 00H CRn0 FFH TCEn0 Count start INTTMn0 TMONote Note Timer 40 only Remark n = 3, 4 Figure 9-11. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N < M)) Count clock TMn0 00H 01H N 00H Clear N M 00H Clear M N M 00H Clear 01H CRn0 N TCEn0 Count start INTTMn0 Interrupt acknowledgement TMONote Interrupt acknowledgement CRn0 overwritten Note Timer 40 only Remark n = 3, 4 96 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-12. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M)) Count clock TMn0 N-1 N 00H Clear M N FFH 00H Clear M M 00H Clear M 00H CRn0 N TCEn0 H TMn0 overflows because M < N INTTMn0 TMONote CRn0 overwritten Note Timer 40 only Remark n = 3, 4 User's Manual U14826EJ4V0UD 97 CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-13. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for Timer 30 Count Clock) Timer 40 count clock TM40 00H 01H N 00H Clear M 00H Clear M 00H Clear M 00H Clear CR40 N M TCE40 Count start INTTM40 Input clock to timer 30 (timer 40 match signal) Y-1 Y 00H 00H TM30 00H 01H Y CR30 Y TCE30 Count start INTTM30 TMO Remark n = 3, 4 98 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 (2) Operation as external event counter with 8-bit resolution (timer 40 only) The external event counter counts the number of external clock pulses input to the TMI/P21 pin by using 8-bit timer counter 40 (TM40). To operate timer 40 as an external event counter, settings must be made in the following sequence. <1> Disable operation of 8-bit timer counter 40 (TM40) (TCE40 = 0). <2> Disable timer output of TMO (TOE40 = 0). <3> Set P21 to input mode (PM21 = 1). <4> Select the external input clock for timer 40 (see Tables 9-5 and 9-6). <5> Set the operation mode of timer 40 to 8-bit timer counter mode (see Figures 9-4 and 9-5). <6> Set a count value in CR40. <7> Enable the operation of TM40 (TCE40 = 1). Each time the valid edge is input, the value of TM40 is incremented. When the count value of TM40 matches the value set in CR40, TM40 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTM40) is generated. Figure 9-14 shows the timing of the external event counter operation. Caution Be sure to stop the timer operation before overwriting the count clock with different data. Figure 9-14. Timing of Operation of External Event Counter with 8-Bit Resolution TMI pin input TM40 count value 00H 01H 02H 03H 04H 05H N-1 N 00H 01H 02H 03H CR40 N TCE40 INTTM40 Remark N = 00H to FFH User's Manual U14826EJ4V0UD 99 CHAPTER 9 8-BIT TIMERS 30 AND 40 (3) Operation as square-wave output wit 8-bit resolution (timer 40 only) Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register 40 (CR40). To operate timer 40 for square-wave output, settings must be made in the following sequence. <1> Set P20 to output mode (PM20 = 0). <2> Clear the output latches of P20 to 0. <3> Disable operation of 8-bit timer counter 40 (TM40) (TCE40 = 0). <4> Set a count clock for timer 40 and enable output of TMO (TOE40 = 1). <5> Set a count value in CR40. <6> Enable the operation of TM40 (TCE40 = 1). When the count value of TM40 matches the value set in CR40, the TMO pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, TM40 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTM40) is generated. The square-wave output is cleared to 0 by setting TCE40 to 0. Tables 9-7 and 9-8 show the square-wave output range, and Figure 9-15 shows the timing of square-wave output. Caution Be sure to stop the timer operation before overwriting the count clock with different data. Table 9-7. Square-Wave Output Range of Timer 40 (During fX = 5.0 MHz Operation) TCL402 TCL401 TCL400 0 0 0 0 0 1 Minimum Pulse Width 1/fX (0.2 s) 2 /fX (0.8 s) 2 8 Maximum Pulse Width 2 /fX (51.2 s) 2 /fX (204.8 s) 10 Resolution 1/fX (0.2 s) 2 /fX (0.8 s) 2 Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) Table 9-8. Square-Wave Output Range of Timer 40 (During fCC = 1.0 MHz Operation) TCL402 TCL401 TCL400 0 0 0 0 0 1 Minimum Pulse Width 1/fCC (1.0 s) 2 /fCC (4.0 s) 2 8 Maximum Pulse Width 2 /fCC (256 s) 2 /fCC (1024 s) 10 Resolution 1/fCC (1.0 s) 2 /fCC (4.0 s) 2 Remark fCC: System clock oscillation frequency (RC oscillation) 100 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-15. Timing of Square-Wave Output with 8-Bit Resolution t Count clock TM40 00H 01H N 00H Clear 01H N 00H Clear N 01H N 00H Clear 01H CR40 TCE40 Count start INTTM40 Interrupt acknowledgement TMONote Interrupt acknowledgement Interrupt acknowledgement Square-wave output cycle Note The initial value of TMO is low level when output is enabled (TOE40 = 1). Remark Square-wave output cycle = 2 (N+1) x t: N = 00H to FFH User's Manual U14826EJ4V0UD 101 CHAPTER 9 8-BIT TIMERS 30 AND 40 9.4.2 Operation as 16-bit timer counter Timer 30 and timer 40 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer counter 30 (TM30) is the higher 8 bits and 8-bit timer counter 40 (TM40) is the lower 8 bits. 8-bit timer 40 controls reset and clear. The following modes can be used for the 16-bit timer counter. * * * (1) Interval timer with 16-bit resolution External event counter with 16-bit resolution Square wave output with 16-bit resolution Operation as interval timer with 16-bit resolution The interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register 30 (CR30) and 8-bit compare register 40 (CR40). To operate as an interval timer with 16-bit resolution, settings must be made in the following sequence. <1> Disable operation of 8-bit timer counter 30 (TM30) and 8-bit timer counter 40 (TM40) (TCE30 = 0, TCE40 = 0). <2> Disable timer output of TMO (TOE40 = 0)Note 1. <3> Set the count clock for timer 40 (see Tables 9-9 and 9-10). <4> Set the operation mode of timer 30 and timer 40 to 16-bit timer counter mode (see Figures 9-4 and 95). <5> Set a count value in CR30 and CR40. <6> Enable the operation of TM30 and TM40 (TCE40 = 1Note 2). Notes 1. Timer 40 only 2. Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of TCE30 is invalid). When the count values of TM30 and TM40 match the values set in CR30 and CR40 respectively, both TM30 and TM40 are simultaneously cleared to 00H and counting continues. At the same time, an interrupt request signal (INTTM40) is generated (INTTM30 is not generated). Tables 9-9 and 9-10 show interval time, and Figure 9-16 shows the timing of the interval timer operation. Caution Be sure to stop the timer operation before overwriting the count clock with different data. 102 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 Table 9-9. Interval Time with 16-Bit Resolution (During fX = 5.0 MHz Operation) TCL402 0 0 0 0 1 1 TCL401 0 0 1 1 0 0 TCL400 0 1 0 1 0 1 Minimum Interval Time 1/fX (0.2 s) 2 /fX (0.8 s) 2 16 Maximum Interval Time 2 /fX (13.1 ms) 2 /fX (52.4 ms) fTMI input cycle x 2 16 18 Resolution 1/fX (0.2 s) 2 /fX (0.8 s) 2 fTMI input cycle fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI input cycle 16 fTMI/2 input cycle x 2 2 fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI/2 input cycle x 2 fTMI/2 input cycle x 2 3 16 16 Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) Table 9-10. Interval Time with 16-Bit Resolution (During fCC = 1.0 MHz Operation) TCL402 0 0 0 0 1 1 TCL401 0 0 1 1 0 0 TCL400 0 1 0 1 0 1 Minimum Interval Time 1/fCC (1.0 s) 2 /fCC (4.0 s) 2 16 Maximum Interval Time 2 /fCC (65.5 ms) 2 /fCC (262.1 ms) fTMI input cycle x 2 16 18 Resolution 1/fCC (1.0 s) 2 /fCC (4.0 s) 2 fTMI input cycle fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI input cycle 16 fTMI/2 input cycle x 2 2 fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI/2 input cycle x 2 fTMI/2 input cycle x 2 3 16 16 Remark fCC: System clock oscillation frequency (RC oscillation) User's Manual U14826EJ4V0UD 103 104 t TM40 count clock TM40 count value 00H N CR40 N N N TCE40 User's Manual U14826EJ4V0UD Figure 9-16. Timing of Interval Timer Operation with 16-Bit Resolution 7FH 80H FFH 00H 7FH 80H FFH 00H N 00H 7FH 80H FFH 00H N 00H Not cleared because TM30 does not match N N N Cleared because TM30 and TM40 match simultaneously N N N N CHAPTER 9 8-BIT TIMERS 30 AND 40 Count start TM30 count clock TM30 00H 01H X-1 X 00H X-1 X 00H CR30 X X X INTTM40 Interrupt not generated because TM30 does not match Interrupt acknowledgement Interrupt acknowledgement TMO Interval time Remark Interval time: (256X + N + 1) x t: X = 00H to FFH, N = 00H to FFH CHAPTER 9 8-BIT TIMERS 30 AND 40 (2) Operation as external event counter with 16-bit resolution The external event counter counts the number of external clock pulses input to the TMI/P21 pin by TM30 and TM40. To operate as an external event counter with 16-bit resolution, settings must be made in the following sequence. <1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0). <2> Disable timer output of TMO (TOE40 = 0)Note 1. <3> Set P21 to input mode (PM21 = 1). <4> Select the external input clock for timer 40 (see Tables 9-9 and 9-10). <5> Set the operation mode of timer 30 and timer 40 to 16-bit timer counter mode (see Figures 9-4 and 95). <6> Set a count value in CR30 and CR40. <7> Enable the operation of TM30 and TM40 (TCE40 = 1Note 2). Notes 1. Timer 40 only 2. Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of TCE30 is invalid). Each time the valid edge is input, the values of TM30 and TM40 are incremented. When the count values of TM30 and TM40 match the values set in CR30 and CR40 respectively, both TM30 and TM40 are simultaneously cleared to 00H and counting continues. At the same time, an interrupt request signal (INTTM40) is generated (INTTM30 is not generated). Figure 9-17 shows the timing of the external event counter operation. Caution Be sure to stop the timer operation before overwriting the count clock with different data. User's Manual U14826EJ4V0UD 105 106 TMI pin input TM40 count value 00H N CR40 N N TCE40 Count start TM30 count clock Figure 9-17. Timing of External Event Counter Operation with 16-Bit Resolution 7FH 80H FFH 00H 7FH 80H FFH 00H N 00H 7FH 80H FFH 00H N 00H Not cleared because TM30 does not match N N N N Cleared because TM30 and TM40 match simultaneously N N N N CHAPTER 9 8-BIT TIMERS 30 AND 40 User's Manual U14826EJ4V0UD TM30 00H 01H X-1 X 00H X-1 X 00H CR30 XX X X X INTTM40 Interrupt not generated because TM30 does not match Interrupt acknowledgement Interrupt acknowledgement Remark X = 00H to FFH, N = 00H to FFH CHAPTER 9 8-BIT TIMERS 30 AND 40 (3) Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR30 and CR40. To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0). <2> Disable output of TMO (TOE40 = 0). <3> Set a count clock for timer 40. <4> Clear P20 to output mode (PM20 = 0) and P20 output latch to 0 and enable TMO output (TOE40 = 1). <5> Set count values in CR30 and CR40. <6> Enable the operation of TM40 (TCE40 = 1Note). Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of TCE30 is invalid). When the count values of TM30 and TM40 simultaneously match the values set in CR30 and CR40 respectively, the TMO pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, TM30 and TM40 are cleared to 00H and counting continues. At the same time, an interrupt request signal (INTTM40) is generated (INTTM30 is not generated). The square-wave output is cleared to 0 by setting TCE40 to 0. Tables 9-11 and 9-12 show the square wave output range, and Figure 9-18 shows timing of square wave output. Caution Be sure to stop the timer operation before overwriting the count clock with different data. Table 9-11. Square-Wave Output Range with 16-Bit Resolution (During fX = 5.0 MHz Operation) TCL402 TCL401 0 0 0 0 TCL400 0 1 Minimum Pulse Time 1/fX (0.2 s) 2 /fX (0.8 s) 2 16 18 Maximum Pulse Time 2 /fX (13.1 ms) 2 /fX (52.4 ms) Resolution 1/fX (0.2 s) 2 /fX (0.8 s) 2 Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) Table 9-12. Square-Wave Output Range with 16-Bit Resolution (During fCC = 1.0 MHz Operation) TCL402 TCL401 0 0 0 0 TCL400 0 1 Minimum Pulse Time 1/fCC (1.0 s) 2 /fCC (4.0 s) 2 16 18 Maximum Pulse Time 2 /fCC (65.5 ms) 2 /fCC (262.1 ms) Resolution 1/fCC (1.0 s) 2 /fCC (4.0 s) 2 Remark fCC: System clock oscillation frequency (RC oscillation) User's Manual U14826EJ4V0UD 107 108 TM40 count clock TM40 count value 00H N 7FH 80H CR40 N N N TCE40 Count start TM30 count clock Figure 9-18. Timing of Square-Wave Output with 16-Bit Resolution FFH 00H 7FH 80H FFH 00H N 00H 7FH 80H FFH 00H N 00H Not cleared because TM30 does not match N N N Cleared because TM30 and TM40 match simultaneously N N N N CHAPTER 9 8-BIT TIMERS 30 AND 40 User's Manual U14826EJ4V0UD TM30 00H 01H X-1 X 00H X-1 X 00H CR30 X X X INTTM40 Interrupt not generated because TM30 does not match Interrupt acknowledgement Interrupt acknowledgement TMO Note Note The initial value of TMO is low level when output is enabled (TOE40 = 1). Remark X = 00H to FFH, N = 00H to FFH CHAPTER 9 8-BIT TIMERS 30 AND 40 9.4.3 Operation as carrier generator An arbitrary carrier clock generated by TM40 can be output in the cycle set in TM30. To operate timer 30 and timer 40 as carrier generators, setting must be made in the following sequence. <1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0). <2> Disable timer output of TMO (TOE40 = 0). <3> Set count values in CR30, CR40, and CRH40. <4> Set the operation mode of timer 40 to carrier generator mode (see Figures 9-4 and 9-5). <5> Set the count clock for timer 30 and timer 40. <6> Set remote control output to carrier pulse (RMC40 (bit 2 of carrier generator output control register 40 (TCA40)) = 0). Input the required value to NRZB40 (bit 1 of TCA40) by program. Input a value to NRZ40 (bit 0 of TCA40) before it is reloaded from NRZB40. <7> Clear P20 to output mode (PM20 = 0) and the P20 output latch to 0 and enable TMO output by setting TOE40 to 1. <8> Enable the operation of TM30 and TM40 (TCE30 = 1, TCE40 = 1). <9> Save the value of NRZB40 to a general-purpose register. <10> When INTTM30 rises, the value of NRZB40 is transferred to NRZ40. After that, rewrite TCA40 with an 8-bit memory manipulation instruction. Input the value to be transferred to NRZ40 next time to NRZB40, and input the value saved in <9> to NRZ40. <11> Generate the desired carrier signal by repeating <9> and <10>. User's Manual U14826EJ4V0UD 109 CHAPTER 9 8-BIT TIMERS 30 AND 40 The operation of the carrier generator is as follows. <1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is generated and output of timer 40 is inverted, which makes the compare register switch from CR40 to CRH40. <2> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal (INTTM40) is generated and output of timer 40 is inverted again, which makes the compare register switch from CRH40 to CR40. <3> The carrier clock is generated by repeating <1> and <2> above. <4> When the count value of TM30 matches the value set in CR30, an interrupt request signal (INTTM30) is generated. The rising edge of INTTM30 is the data reload signal of NRZB40 and is transferred to NRZ40. <5> When NRZ40 is 1, a carrier clock is output from TMO pin. Cautions 1. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-bit memory manipulation instruction to set TCA40. 2. The NRZ40 flag can be written only when carrier generator output is stopped (TOE40 = 0). The data cannot be overwritten when TOE40 = 1. 3. When the carrier generator is stopped once and then started again, NRZB40 does not hold the previous data. Re-set data to NRZB40. At this time, a 1-bit memory manipulation instruction must not be used. Be sure to use an 8-bit memory manipulation instruction. 4. To enable operation in the carrier generator mode, set a value to the compare registers (CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40 flags in advance. Otherwise, the signal of the timer match circuit will become unstable and the NRZ40 flag will be undefined. 5. Note that the PD78E9860 and 78E9861 have the following restrictions (which do not apply to the mask ROM version and the PD78E9860A and 78E9861A). (a) While INTTM30 (interrupt generated by the match signal of timer 30) is being output, accessing TCA40 is prohibited. (b) Accessing TCA40 is prohibited while 8-bit timer/counter 30 (TM30) is 00H. To access TCA40 while TM30 = 00H, wait for more than half a period of the TM30 count clock and then rewrite TCA40. 110 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-19. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N)) TM40 count clock TM40 count value 00H 01H N 00H Clear N M 00H Clear N 00H Clear N M 00H Clear CR40 N CRH40 M TCE40 Count start INTTM40 Carrier clock TM30 count clock TM30 00H 01H X 00H 01H X 00H 01H X 00H X 00H 01H CR30 X TCE30 INTTM30 NRZB40 0 1 0 1 0 NRZ40 0 1 0 1 0 Carrier clock TMO User's Manual U14826EJ4V0UD 111 CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-20. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N)) TM40 count clock TM40 count value 00H M N 00H Clear M 00H Clear M N 00H Clear M 00H Clear CR40 N CRH40 M TCE40 Count start INTTM40 Carrier clock TM30 count clock TM30 00H 01H X 00H 01H X 00H 01H X 00H X 00H 01H CR30 X TCE30 INTTM30 NRZB40 0 1 0 1 0 NRZ40 0 1 0 1 0 Carrier clock TMO Remark This timing chart shows an example in which the value of NRZ40 is changed while the carrier clock is high. 112 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-21. Timing of Carrier Generator Operation (When CR40 = CRH40 = N) Count clock TM40 count value 00H N 00H Clear N 00H Clear N 00H Clear N 00H Clear N 00H Clear N CR40 N CRH40 N TCE40 Count start INTTM40 Carrier clock Count pulse TM30 00H 01H X 00H 01H X 00H 01H X 00H X 00H 01H CR30 X TCE30 INTTM30 NRZB40 0 1 0 1 0 NRZ40 0 1 0 1 0 Carrier clock TMO User's Manual U14826EJ4V0UD 113 CHAPTER 9 8-BIT TIMERS 30 AND 40 9.4.4 Operation as PWM output (timer 40 only) In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CR40 and a high-level width using CRH40. To operate timer 40 in PWM output mode, settings must be made in the following sequence. <1> Disable operation of TM40 (TCE40 = 0). <2> Disable timer output of TMO (TOE40 = 0). <3> Set count values in CR40 and CRH40. <4> Set the operation mode of timer 40 to PWM output mode (see Figure 9-5). <5> Set the count clock for timer 40. <6> Clear P20 to output mode (PM20 = 0) and the P20 output latch to 0 and enable timer output of TMO (TOE40 = 1). <7> Enable the operation of TM40 (TCE40 = 1). The operation in the PWM output mode is as follows. <1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is generated and output of timer 40 is inverted, which makes the compare register switch from CR40 to CRH40. <2> A match between TM40 and CR40 clears the TM40 value to 00H and then counting starts again. <3> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal (INTTM40) is generated and output of timer 40 is inverted again, which makes the compare register switch from CRH40 to CR40. <4> A match between TM40 and CRH40 clears the TM40 value to 00H and then counting starts again. A pulse of any duty ratio is output by repeating <1> to <4> above. Figures 9-22 and 9-23 show the operation timing in the PWM output mode. 114 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-22. PWM Output Mode Timing (Basic Operation) TM40 count clock TM40 count value 00H 01H N 00H Clear 01H M 00H Clear 01H N 00H Clear 01H M 00H Clear CR40 N CRH40 M TCE40 Count start INTTM40 TMONote Note The initial value of TMO is low level when output is enabled (TOE40 = 1). Figure 9-23. PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten) TM40 count clock TM40 count value 00H 01H N 00H Clear Y 01H 00H Clear X N 00H X 00H Clear M 00H Clear X CR40 N CRH40 M Y M TCE40 Count start INTTM40 TMONote Note The initial value of TMO is low level when output is enabled (TOE40 = 1). User's Manual U14826EJ4V0UD 115 CHAPTER 9 8-BIT TIMERS 30 AND 40 9.5 Notes on Using 8-Bit Timers 30, 40 (1) Error on starting timer An error of up to 1.5 clocks is included in the time between the timer being started and a match signal being generated. This is because the rising edge is detected and the counter is incremented if the timer is started while the count clock is high (see Figure 9-24). Figure 9-24. Case of Error Occurrence of up to 1.5 Clocks Delay A Selected clock Count pulse 8-bit timer counter n0 (TMn0) Clear signal TCEn0 Delay B Selected clock TCEn0 Clear signal Count pulse TMn0 counter value 00H 01H Delay A Delay B 02H 03H An error of up to 1.5 clocks occurs if the timer is started when the selected clock is high and delay A > delay B. Remark n = 3, 4 116 User's Manual U14826EJ4V0UD CHAPTER 9 8-BIT TIMERS 30 AND 40 (2) Count value if external clock input from TMI pin is selected When the external clock signal input from the TMI pin is selected as the count clock, the count value may start from 01H if the timer is enabled (TCE40 = 0 1) while the TMI pin is high. This is because the input signal of the TMI pin is internally ANDed with the TCE40 signal. Consequently, the counter is incremented because the rising edge of the count clock is input to the timer immediately when the TCE40 pin is set. Depending on the delay timing, the count value is incremented by one if the rising edge is input after the counter is cleared. Counting is not affected if the rising edge is input before the counter is cleared (the counter operates normally). Use the timer being aware that it has an error of one count, or take either of the following actions A or B. Clear TCE40 flag TMI H Rising edge detector Increment Counter (3) Setting of 8-bit compare register n0 8-bit compare register n0 (CRn0) can be cleared to 00H. Therefore, one pulse can be counted when the 8-bit timer operates as an event counter. Figure 9-26. Timing of Operation as External Event Counter (8-Bit Resolution) TMI input CR40 00H TM40 count value Interrupt request flag 00H 00H 00H 00H User's Manual U14826EJ4V0UD 117 CHAPTER 10 WATCHDOG TIMER 10.1 Watchdog Timer Functions The watchdog timer has the following functions: * Watchdog timer * Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect inadvertent program loops. When the inadvertent program loop is detected, a non-maskable interrupt or a RESET signal can be generated. Table 10-1. Inadvertent Program Loop Detection Time of Watchdog Timer Inadvertent Program Loop Detection Time 2 x 1/fCLK 11 11 At fX = 5.0 MHz Operation 2 /fX (410 s) 2 /fX (1.64 ms) 2 /fX (6.55 ms) 2 /fX (26.2 ms) 17 15 13 At fCC = 1.0 MHz Operation 2 /fCC (2.05 ms) 2 /fCC (8.19 ms) 2 /fCC (32.8 ms) 2 /fCC (131.1 ms) 17 15 13 11 2 x 1/fCLK 13 2 x 1/fCLK 15 2 x 1/fCLK 17 Remarks 1. fCLK: fX or fCC 2. fX: System clock oscillation frequency (ceramic/crystal oscillation) 3. fCC: System clock oscillation frequency (RC oscillation) (2) Interval timer The interval timer generates an interrupt at an arbitrary preset interval. Table 10-2. Interval Time of Watchdog Timer Interval 2 x 1/fCLK 11 11 At fX = 5.0 MHz Operation 2 /fX (410 s) 2 /fX (1.64 ms) 2 /fX (6.55 ms) 2 /fX (26.2 ms) 17 15 13 11 At fCC = 1.0 MHz Operation 2 /fCC (2.05 ms) 2 /fCC (8.19 ms) 2 /fCC (32.8 ms) 2 /fCC (131.1 ms) 17 15 13 2 x 1/fCLK 13 2 x 1/fCLK 15 2 x 1/fCLK 17 Remarks 1. fCLK: fX or fCC 2. fX: System clock oscillation frequency (ceramic/crystal oscillation) 3. fCC: System clock oscillation frequency (RC oscillation) 118 User's Manual U14826EJ4V0UD CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 10-3. Configuration of Watchdog Timer Item Control registers Timer clock selection register 2 (TCL2) Watchdog timer mode register (WDTM) Configuration Figure 10-1. Block Diagram of Watchdog Timer Internal bus fCLK 24 fCLK 26 Prescaler fCLK 28 fCLK 210 TMMK4 TMIF4 Selector INTWDT Maskable interrupt request RESET INTWDT Non-maskable interrupt request 7-bit counter Clear Controller 3 TCL22 TCL21 TCL20 Timer clock selection register 2 (TCL2) RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal bus Remark fCLK: fX or fCC User's Manual U14826EJ4V0UD 119 CHAPTER 10 WATCHDOG TIMER 10.3 Watchdog Timer Control Registers The following two registers are used to control the watchdog timer. * Timer clock selection register 2 (TCL2) * Watchdog timer mode register (WDTM) (1) Timer clock selection register 2 (TCL2) TCL2 sets the watchdog timer count clock. This register is set with an 8-bit memory manipulation instruction. RESET input clears TCL2 to 00H. Figure 10-2. Format of Timer Clock Selection Register 2 Symbol TCL2 7 0 6 0 5 0 4 0 3 0 <2> TCL22 <1> TCL21 <0> TCL20 Address FF42H After reset 00H R/W R/W TCL22 TCL21 TCL20 Count clock selection At fX = 5.0 MHz operation At fCC= 1.0 MHz operation fCC/24 fCC/26 fCC/28 (62.5 kHz) (15.6 kHz) (3.91 kHz) 0 0 1 1 0 1 0 1 Other than above 0 0 0 0 fX/24 fX/26 fX/28 (313 kHz) (78.1 kHz) (19.5 kHz) fX/210 (4.88 kHz) Setting prohibited fCC/210 (977 Hz) Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) 120 User's Manual U14826EJ4V0UD CHAPTER 10 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) WDTM sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 10-3. Format of Watchdog Timer Mode Register Symbol WDTM <7> RUN 6 0 5 0 4 WDTM4 3 WDTM3 2 0 1 0 0 0 Address FFF9H After reset 00H R/W R/W RUN 0 1 Stops counting. Watchdog timer operation selectionNote 1 Clears counter and starts counting. WDTM4 0 0 1 1 WDTM3 0 1 0 1 Operation stop Watchdog timer operation mode selectionNote 2 Interval timer mode (Generates a maskable interrupt upon overflow occurrence.)Note 3 Watchdog timer mode 1 (Generates a non-maskable interrupt upon overflow occurrence.) Watchdog timer mode 2 (Starts a reset operation upon overflow occurrence.) Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is started, it cannot be stopped by any means other than RESET input. 2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software. 3. The watchdog timer starts operation as an interval timer when RUN is set to 1. Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to 0.8% shorter than the time set by the timer clock selection register 2 (TCL2). 2. To set watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of interrupt request flag register 0 (IF0)) being cleared to 0. When watchdog timer mode 1 or 2 is selected with TMIF4 set to 1, a non-maskable interrupt is generated upon the completion of rewriting WDTM. User's Manual U14826EJ4V0UD 121 CHAPTER 10 WATCHDOG TIMER 10.4 Watchdog Timer Operation 10.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of the timer clock selection register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started. Set RUN to 1 within the set inadvertent program loop detection time interval after the watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the inadvertent program loop detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on the value of bit 3 (WDTM3) of WDTM. The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to clear the watchdog timer before executing the STOP instruction. Caution The actual inadvertent program loop detection time may be up to 0.8% shorter than the set time. Table 10-4. Inadvertent Program Loop Detection Time of Watchdog Timer TCL22 0 0 1 1 TCL21 0 1 0 1 Other than above TCL20 0 0 0 0 11 At fX = 5.0 MHz Operation 2 /fX (410 s) 2 /fX (1.64 ms) 2 /fX (6.55 ms) 2 /fX (26.2 ms) Setting prohibited 17 15 13 At fCC = 1.0 MHz Operation 2 /fCC (2.05 ms) 2 /fCC (8.19 ms) 2 /fCC (32.8 ms) 2 /fCC (131.1 ms) 17 15 13 11 Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) 122 User's Manual U14826EJ4V0UD CHAPTER 10 WATCHDOG TIMER 10.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at an interval specified by a preset count value. Select a count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of the timer clock selection register 2 (TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1. In interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable interrupts. The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to clear the interval timer before executing the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), interval timer mode is not set unless a RESET signal is input. 2. The interval time may be up to 0.8% shorter than the set time when WDTM has just been set. Table 10-5. Interval Time of Watchdog Timer TCL22 0 0 1 1 TCL21 0 1 0 1 Other than above TCL20 0 0 0 0 11 At fX = 5.0 MHz Operation 2 /fX (410 s) 2 /fX (1.64 ms) 2 /fX (6.55 ms) 2 /fX (26.2 ms) Setting prohibited 17 15 13 At fCC = 1.0 MHz Operation 2 /fCC (2.05 ms) 2 /fCC (8.19 ms) 2 /fCC (32.8 ms) 2 /fCC (131.1 ms) 17 15 13 11 Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) User's Manual U14826EJ4V0UD 123 CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.1 Power-on-Clear Circuit Functions The power-on-clear circuits include the following two circuits, which have the following functions. (1) Power-on-clear (POC) circuit * Compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an internal reset signal if VDD < VPOC. * The mask ROM versions can select a POC switching circuit, normally operating POC circuit, or normally halted POC circuit by using the mask option. When a POC switching circuit is selected, POC operation can be controlled by software (see CHAPTER 18 MASK OPTIONS). * This circuit can operate even in STOP mode. (2) Low-voltage detection (LVI) circuit * Compares the detection voltage (VLVI) with the power supply voltage (VDD) and generates an interrupt request signal (INTLVI1) if VDD < VLVI. * Eight levels of detection voltage can be selected using software. * This circuit stops operation in STOP mode. 11.2 Power-on-Clear Circuit Configuration Figures 11-1 and 11-2 show the block diagrams of the power-on-clear circuits. 124 User's Manual U14826EJ4V0UD CHAPTER 11 POWER-ON-CLEAR CIRCUITS Figure 11-1. Block Diagram of Power-on-Clear Circuit VDD VDD P-ch P-ch + - Internal reset signal Detection voltage source (VPOC) POCOF1 POCMK1 POCMK0 Power on clear register 1 (POCF1) Internal bus Figure 11-2. Block Diagram of Low-Voltage Detection Circuit VDD P-ch Low-voltage detection level selector VDD LVI stop signal (set during STOP instruction execution or reset signal generation) INTLVI1 N-ch Detection voltage source (VLVI) P-ch + - LVS12 LVS11 LVS10 Low-voltage detection level selection register 1 (LVIS1) Internal bus LVION1 LVF10 Low-voltage detection register 1 (LVIF1) User's Manual U14826EJ4V0UD 125 CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.3 Power-on-Clear Circuit Control Registers The following three registers control the power-on-clear circuits. * Power-on-clear register 1 (POCF1) * Low-voltage detection register 1 (LVIF1) * Low-voltage detection level selection register 1 (LVIS1) (1) Power-on-clear register 1 (POCF1) POCF1 controls POC circuit operation. This register is set with a 1-bit or 8-bit memory manipulation instruction. Figure 11-3. Format of Power-on-Clear Register 1 Symbol POCF1 7 0 6 0 5 0 4 0 3 0 <2> <1> <0> Address After reset FFDDH 00H Note R/W R/W POCOF1 POCMK1 POCMK0 POCOF1 0 1 POC output detection flag Non-generation of reset signal by POC or in cleared state due to a write operation to POCF1 Generation of reset signal by POC POCMK1 0 1 Generation of reset signal by POC enabled Generation of reset signal by POC disabled POC reset control POCMK0 0 1 POC operating POC halted POC operation control Note This value is 04H only after a power-on-clear reset. Caution For mask ROM versions, POCMK0 and POCMK1 are only valid when the POC switching circuit has been selected using a mask option. 126 User's Manual U14826EJ4V0UD CHAPTER 11 POWER-ON-CLEAR CIRCUITS (2) Low-voltage detection register 1 (LVIF1) LVIF1 controls the operation of the LVI circuit. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 11-4. Format of Low-Voltage Detection Register 1 Symbol LVIF1 <7> LVION1 6 0 5 0 4 0 3 0 2 0 1 0 <0> LVF10 Address After reset FFDEH 00H R/W R/W Note LVION1 0 1 LVI disabled LVI enabled LVI operation enable flag LVF10 0 1 LVI output detection flag Power supply voltage (VDD) > LVI detection voltage (VLVI) or operation disabled VDD < VLVI Note Bit 0 is read only. (3) Low-voltage detection level selection register 1 (LVIS1) LVIS1 selects the level of the detection voltage (VLVI). This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 11-5. Format of Low-Voltage Detection Level Selection Register 1 Symbol LVIS1 7 0 6 0 5 0 4 0 3 0 <2> LVS12 <1> LVS11 <0> LVS10 Address After reset FFDFH 00H R/W R/W LVS12 0 0 0 0 1 1 1 1 LVS11 0 0 1 1 0 0 1 1 LVS10 0 1 0 1 0 1 0 1 VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 Selection of detection voltage (VLVI) level Note Note See CHAPTER 20 ELECTRICAL SPECIFICATIONS for detection voltage specifications. Caution When changing the detection voltage level (VLVI), an operation stabilization time of about 2 ms is required in order for the LVI output to stabilize. Do not, therefore, set the LVI circuit to operation-enable until the operation has stabilized. User's Manual U14826EJ4V0UD 127 CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.4 Power-on-Clear Circuit Operation 11.4.1 Power-on-clear (POC) circuit operation The POC circuit compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an internal reset signal if VDD < VPOC. For mask ROM versions, it is possible to select a POC switching circuit, normally operating POC circuit, or normally halted POC circuit by using a mask option. When a POC switching circuit is selected, POC operation can be controlled by software. Only the POC switching circuit is available for the PD78E9860A and 78E9861A (selection cannot be made by mask option). Observe the following procedure when switching POC operation using the POC switching circuit. (1) Switching from POC stopped to POC operating <1> Check that POCMK1 = 1 <2> Clear POCMK0 to 0 to put the POC circuit into the operating state <3> Wait until the operation stabilization time has elapsed (because the output signal is unstable, generation of the reset signal via the POC circuit is set to disabled) <4> Clear POCMK1 to 0 to enable generation of the reset signal via the POC circuit (2) Switching from POC operating to POC stopped <1> Set POCMK1 to 1 to disable generation of the reset signal via the POC circuit <2> Set POCMK0 to 1 to put the POC circuit into the operation stopped state Generation of the reset signal via the POC circuit can be determined by reading the POCOF1 flag. When the reset signal is generated via the POC circuit, POCOF1 is set to 1. POCOF1 is cleared by writing 0 to POCF1Note. When using the POC circuit, clear POCOF1 beforehand. Note POCOF1 is cleared when data is written to any of bits 0 to 2 in the POCF1 register. Figures 11-6 to 11-8 show the timing of reset signal generation via the POC circuit. Figure 11-6. Timing of Internal Reset Signal Generation When POC Circuit Normally Operating Power supply voltage (VDD) Detection voltage (VPOC) 1.8 V Time Internal reset signal 128 User's Manual U14826EJ4V0UD CHAPTER 11 POWER-ON-CLEAR CIRCUITS Figure 11-7. Timing of Internal Reset Signal Generation When POC Circuit Normally Halted Power supply voltage (VDD) Detection voltage (VPOC) 1.8 V Time Internal reset signal "H" Figure 11-8. Timing of Internal Reset Signal Generation in POC Switching Circuit Power supply voltage (VDD) Detection voltage (VPOC) 1.8 V Time POCMK0 POCMK1 Wait Internal reset signal User's Manual U14826EJ4V0UD 129 CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.4.2 Operation of low-voltage detection (LVI) circuit The LVI circuit compares the detection voltage (VLVI) with the power supply voltage (VDD) and generates an interrupt request signal (INTLVI1) if VDD < VLVI (LVI circuit operating). As shown in Figure 11-2 Block Diagram of Low-Voltage Detection Circuit, the divided resistors and comparators of the LVI circuit turn OFF when the reset signal is generated or in STOP mode. After reset is released, LVI operation starts when LVION1 (bit 7 of low-voltage detection register 1 (LVIF1)) is set. At this time, approximately 2 ms are required until the LVI circuit operation is stabilized. Once the LVI operation is started, divided resistors and comparators cannot be OFF unless the STOP instruction or reset signal is generated, even LVION1 is cleared. Low-voltage detection is enabled immediately after LVION1 is set again. Caution The divider resistor and comparator of the LVI circuit are turned ON after reset is released. Use one of the following methods to constantly monitor low voltage. <1> Low-voltage monitoring by LVFI0 (bit 0 of low-voltage detection register 1 (LVIF1)) without using LVI detection interrupt. <2> Low-voltage monitoring using LVI detection interrupt. In this case, disable the LVI operation once, and then enable it (LVION1 = 0 1) before enabling interrupts (LVIMK1 = 0). An example of a program in which low voltage is constantly monitored using the LVI detection interrupt is shown below. (a) Processing when reset mode is released DI MOV SET1 SET1 CALL CLR1 CLR1 SET1 CLR1 EI (b) Processing when STOP mode is released SET1 STOP CALL CLR1 CLR1 SET1 CLR1 EI !WAIT; LVIIF1 LVION1; LVION1; LVIMK1; LVI operation disabled LVI operation enabled LVI interrupt enabled Total 2 ms wait, combined with oscillation stabilization time LVIMK1; LVI interrupt disabled LVIS1, #xxH; LVIMK1; LVION1; !WAIT_2ms; LVIIF1; LVION1; LVION1; LVIMK1; LVI operation disabled LVI operation enabled LVI interrupt enabled Setting LVI detection voltage LVI interrupt disabled LVI operation enabled 2 ms wait 130 User's Manual U14826EJ4V0UD CHAPTER 11 POWER-ON-CLEAR CIRCUITS (c) Processing to enable LVI interrupt again after LVI interrupt servicing SET1 CLR1 SET1 CLR1 EI LVIMK1; LVION1; LVION1; LVIMK1; LVI interrupt disabled LVI operation disabled LVI operation enabled LVI interrupt enabled Figure 11-9 shows the LVI circuit operation timing. Figure 11-9. LVI Circuit Operation Timing Power supply voltage (VDD) Detection voltage (VLVI) 1.8 V LVION1 2 ms Vectored interrupt IE INTLVI1 LVIIF1 LVIMK1 Vectored interrupt does not occur Caution The low-voltage detection interrupt request flag (LVIIF1) is set at the rising edge of the LVI circuit comparator output signal (INTLVI1). Therefore, the power supply voltage (VDD) becomes lower than the detection voltage (VLVI) during LVI operation, and if that state continues after INTLVI1 generation, LVIIF1 is not set. After low-voltage detection, when set as VDD > VLVI and then VDD < VLVI again, LVIIF1 is set. User's Manual U14826EJ4V0UD 131 CHAPTER 12 BIT SEQUENTIAL BUFFER 12.1 Bit Sequential Buffer Functions The PD789860, 789861 Subseries have an on-chip bit sequential buffer of 8 bits x 8 bits = 16 bits. The functions of the bit sequential buffer are shown below. * * * If the value of the bit sequential buffer 10 data register (BSFRL10, BSFRH10) is shifted 1 bit to the lower side, the LSB can be output to the port at the same time. It is possible to write to BSFRL10 and BSFRH10 using an 8-bit or 16-bit memory manipulation instruction (reading is not possible). Overwriting is enabled during a shift operation on the higher 8 bits (BSFRH10) only (the period in which shift clock is low level). 12.2 Bit Sequential Buffer Configuration The bit sequential buffer includes the following hardware. Table 12-1. Configuration of Bit Sequential Buffer Item Data register Control register Bit sequential buffer: 8 bits x 8 bits = 16 bits Bit sequential buffer output control register 10 (BSFC10) Port mode register 2 (PM2) Port 2 (P2) Configuration Figure 12-1. Block Diagram of Bit Sequential Buffer Internal bus Timer 40 match interrupt request signal BSFRH10 BSFRL10 BSFO/P20/ TMO BSFE10 Bit sequential buffer output control register 10 (BSFC10) Internal bus P20 output latch PM20 132 User's Manual U14826EJ4V0UD CHAPTER 12 BIT SEQUENTIAL BUFFER 12.3 Bit Sequential Buffer Control Register The bit sequential buffer is controlled by the following three registers. * Bit sequential buffer output control register 10 (BSFC10) * Port mode register 2 (PM2) * Port 2 (P2) (1) Bit sequential buffer output control register 10 (BSFC10) BSFC10 controls the operation of the bit sequential buffer. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 12-2. Format of Bit Sequential Buffer Output Control Register 10 Symbol BSFC10 7 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> BSFE10 Address After reset FF60H 00H R/W R/W BSFE10 0 1 Operation disabled Operation enabled Bit sequential buffer operation control (2) Port mode register 2 (PM2) PM2 sets port 2 to input/output in 1-bit units. When using the P20/TMO/BSFO pin as a data output of the bit sequential buffer, clear the PM20 and P20 output latch to 0. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 12-3. Format of Port Mode Register 2 Symbol PM2 7 1 6 1 5 1 4 1 3 1 2 1 1 PM21 0 PM20 Address After reset FF22H FFH R/W R/W PM20 0 1 Output mode (output buffer on) Input mode (output buffer off) P20 pin input/output mode User's Manual U14826EJ4V0UD 133 CHAPTER 12 BIT SEQUENTIAL BUFFER 12.4 Bit Sequential Buffer Operation Set as follows to operate the bit sequential buffer. <1> Set values to bit sequential buffer 10 data registers L and H (BSFRL10, BSFRH10) <2> Set the bit sequential buffer to operation enabled (BSFE10 = 1) If the LSB of BSFRL10 is being output at P20/BSFO/TMO, set P20 to output mode (PM20 = 0) and the output latch of P20 to 0 <3> Start the clock operation If the clock is input before the bit sequential buffer starts operation, the output time of the start bit may be shorter than one cycle of the clock when output commences, as shown in the figure below. Timer 40 match signal t0 BSFE10 BSFRL10, BSFRH10 Bit sequential buffer output t1 t1< t0 t2 t2 = t0 5555H 2AAAH 1555H 0AAAH Figure 12-4 shows the operation timing of the bit sequential buffer. Figure 12-4. Operation Timing of Bit Sequential Buffer Timer 40 match signal BSFE10 BSFRL10, Undefined BSFRH10 Bit sequential buffer output 5555H 2AAAH 1555H 0AAAH x555H x2AAH Cautions 1. Even if data is written to the data register while the bit sequential buffer is operating, the shift clock (timer 40 match signal) will not stop. Data should therefore be written to the data register when the shift clock is low level. 2. The value of the data register is undefined after a shift. Remark x: Undefined 134 User's Manual U14826EJ4V0UD CHAPTER 13 KEY RETURN CIRCUIT 13.1 Key Return Circuit Function In STOP mode, this circuit generates a key return interrupt (INTKR1) by inputting a P40/KR10 to P43/KR13 falling edge. Cautions 1. The key return interrupt is a non-maskable interrupt that is effective only in STOP mode. In addition, P40/KR10 to P43/KR13 key input cannot be performed by mask control. 2. The key return signal cannot be detected even if a falling edge is generated on the other key return pins while even one of the key return pins (P40/KR10 to P43/KR13) is low. 13.2 Key Return Circuit Configuration and Operation Figure 13-1 shows the block diagram of the key return circuit. Figure 13-2 shows the generation timing of the key return interrupt (INTKR1). Figure 13-1. Block Diagram of Key Return Circuit P40/KR10 P41/KR11 P42/KR12 P43/KR13 STOP mode Falling edge detector Key return interrupt (INTKR1) Figure 13-2. Generation Timing of Key Return Interrupt STOP signal P4n/KR1n INTKR1 Remark n = 0 to 3 User's Manual U14826EJ4V0UD 135 CHAPTER 14 INTERRUPT FUNCTIONS 14.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupts This interrupt is acknowledged unconditionally even if interrupts are disabled. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. There are one external source and one internal source of non-maskable interrupts. (2) Maskable interrupts These interrupts undergo mask control. If two or more interrupt requests are simultaneously generated, each interrupt has a predetermined priority as shown in Table 14-1. A standby release signal is generated. There are five internal sources of maskable interrupts. 136 User's Manual U14826EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS 14.2 Interrupt Sources and Configuration There are a total of 7 non-maskable and maskable interrupt sources (see Table 14-1). Table 14-1. Interrupt Sources Interrupt Type Priority Note 1 Interrupt Source Name Trigger Key return input falling edge detection INTWDT Watchdog timer overflow (when watchdog timer mode 1 is selected) Internal/External Vector Table Address Basic Configuration Type Note 2 Non-maskable interrupt - INTKR1 External 0002H (A) Internal 0004H Maskable interrupt 0 INTWDT Watchdog timer overflow (when interval timer mode is selected) (B) 1 INTTM30 Generation of match signal for 8-bit timer 30 0006H 2 INTTM40 Generation of match signal for 8-bit timer 40 0008H 3 4 INTLVI1 INTEE0 LVI interrupt request signal EEPROM write termination signal 000AH 000CH Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest and 4 is the lowest. 2. Basic configuration types (A) and (B) correspond to (A) and (B) in Figure 14-1. Remark There are two interrupt sources for the watchdog timer (INTWDT): non-maskable interrupts and maskable interrupts (internal). Either one (but not both) should be selected for actual use. User's Manual U14826EJ4V0UD 137 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (A) External/internal non-maskable interrupt Internal bus Interrupt request Vector table address generator Standby release signal (B) Internal maskable interrupt Internal bus MK IE Interrupt request IF Vector table address generator Standby release signal IF: IE: Interrupt request flag Interrupt enable flag MK: Interrupt mask flag 138 User's Manual U14826EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS 14.3 Interrupt Function Control Registers The interrupt functions are controlled by the following three types of registers. * Interrupt request flag register 0 (IF0) * Interrupt mask flag register 0 (MK0) * Program status word (PSW) Table 14-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags. Table 14-2. Interrupt Request Signals and Corresponding Flags Interrupt Request Signal INTWDT INTTM30 INTTM40 INTLVI1 INTEE0 TMIF4 TMIF30 TMIF40 LVIF1 EEIF0 Interrupt Request Flag TMMK4 TMMK30 TMMK40 LVIMK1 EEMK0 Interrupt Mask Flag (1) Interrupt request flag register 0 (IF0) An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the instruction is executed. It is cleared to 0 by executing an instruction when the interrupt request is acknowledged or when a RESET signal is input. IF0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears IF0 to 00H. Figure 14-2. Format of Interrupt Request Flag Register 0 Symbol IF0 7 0 6 0 5 0 <4> EEIF0 <3> LVIIF1 <2> TMIF40 <1> TMIF30 <0> TMIF4 Address FFE0H After reset 00H R/W R/W xxIFx 0 1 Interrupt request flag No interrupt request signal has been issued. An interrupt request signal has been issued; an interrupt request status. Cautions 1. Be sure to clear bits 5 to 7 to 0. 2. The TMIF4 flag can be read- and write-accessed only when the watchdog timer is being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. User's Manual U14826EJ4V0UD 139 CHAPTER 14 INTERRUPT FUNCTIONS (2) Interrupt mask flag register 0 (MK0) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 to FFH. Figure 14-3. Format of Interrupt Mask Flag Register 0 Symbol MK0 7 1 6 1 5 1 <4> EEMK0 <3> LVIMK1 <2> <1> <0> TMMK4 Address FFE4H After reset FFH R/W R/W TMMK40 TMMK30 xxMKx 0 1 Enables servicing servicing. Disables servicing servicing. Interrupt servicing control Cautions 1. Be sure to set bits 5 to 7 to 1. 2. The TMMK4 flag can be read- and write-accessed only when the watchdog timer is being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. (3) Program status word (PSW) The program status word is used to hold the instruction execution result and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW. PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically saved to a stack, and the IE flag is reset to 0. RESET input sets PSW to 02H. Figure 14-4. Program Status Word Configuration Symbol PSW 7 IE 6 Z 5 0 4 AC 3 0 2 0 1 1 0 CY After reset 02H Used in the execution of ordinary instructions IE 0 1 Disabled Enabled Whether to enable/disable interrupt acknowledgment 140 User's Manual U14826EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS 14.4 Interrupt Servicing Operation 14.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches. Figure 14-5 shows the flowchart from non-maskable interrupt request generation to acknowledgment. Figure 14-6 shows the timing of non-maskable interrupt request acknowledgment. operation if multiple non-maskable interrupts are generated. Caution The PD789860 and 789861 Subseries have two non-maskable interrupt sources. Therefore, during execution of a non-maskable interrupt servicing program, a new non-maskable interrupt request is not acknowledged until the RETI instruction is executed. Be sure to execute the RETI instruction after the interrupt servicing program has been executed. When using the watchdog timer as a non-maskable interrupt, push the address of restore destination before executing the RETI instruction. If the RETI instruction is executed without pushing the restore destination, the program will jump to an illegal address. example is shown below. User's Manual U14826EJ4V0UD 141 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-5. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment (INTWDT) Start WDTM4 = 1 (watchdog timer mode is selected) Yes No Interval timer WDT overflows Yes WDTM3 = 0 No (non-maskable interrupt is selected) Yes Interrupt request is generated Interrupt servicing is started No Reset processing WDTM: Watchdog timer mode register WDT: Watchdog timer Figure 14-6. Timing of Non-Maskable Interrupt Request Acknowledgment Saving PSW and PC, and jump to interrupt servicing CPU processing Instruction Instruction Interrupt servicing program WDTIF Figure 14-7. Acknowledgment of Non-Maskable Interrupt Request Main routing First interrupt servicing NMI request (first) NMI request (second) RETI instruction execution Second interrupt servicing RETI instruction execution 142 User's Manual U14826EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS 14.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1). The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in Table 14-3. See Figures 14-9 and 14-10 for the interrupt request acknowledgment timing. Table 14-3. Time from Generation of Maskable Interrupt Request to Servicing Minimum Time 9 clocks Maximum Time 19 clocks Note Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instruction. Remark 1 clock: 1 (fCPU: CPU clock) fCPU When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. A pending interrupt is acknowledged when a status in which it can be acknowledged is set. Figure 14-8 shows the algorithm of interrupt request acknowledgment. When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To return from interrupt servicing, use the RETI instruction. User's Manual U14826EJ4V0UD 143 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-8. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (Interrupt request generated) No xxMK = 0? Yes Interrupt request pending No IE = 1? Yes Vectored interrupt servicing Interrupt request pending xxIF: xxMK: IE: Interrupt request flag Interrupt mask flag Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable) Figure 14-9. Interrupt Request Acknowledgment Timing (Example of MOV A, r) 8 clocks Clock CPU MOV A, r Saving PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set before an instruction clock n (n = 4 to 10) under execution becomes n - 1, the interrupt is acknowledged after the instruction under execution is complete. Figure 14-9 shows an example of the interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A, r. Since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment processing is performed after the MOV A, r instruction is executed. 144 User's Manual U14826EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-10. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) 8 clocks Clock CPU NOP MOV A, r Saving PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set at the last clock of the instruction, the interrupt acknowledgment processing starts after the next instruction is executed. Figure 14-10 shows an example of the interrupt acknowledgment timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A, r instruction after the NOP instruction is executed, and then the interrupt acknowledgment processing is performed. Caution Interrupt requests will be held pending while interrupt request flag register 0 (IF0) or interrupt mask flag register 0 (MK0) is being accessed. User's Manual U14826EJ4V0UD 145 CHAPTER 14 INTERRUPT FUNCTIONS 14.4.3 Multiple interrupt servicing Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced can be performed using a priority order system. When two or more interrupts are generated at once, interrupt servicing is performed according to the priority assigned to each interrupt request in advance (see Table 14-1). Figure 14-11. Example of Multiple Interrupts Example 1. A multiple interrupt is acknowledged Main processing INTxx servicing INTyy servicing EI IE = 0 EI IE = 0 INTxx INTyy RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated. The EI instruction is issued before each interrupt request acknowledgment, and the interrupt request acknowledgment enable state is set. Example 2. Multiple interrupts are not generated because interrupts are not enabled Main processing INTxx servicing INTyy servicing EI IE = 0 INTyy RETI INTyy is held pending INTxx IE = 0 RETI Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request INTyy is not acknowledged, and multiple interrupts are not generated. acknowledged after the INTxx servicing is performed. IE = 0: Interrupt request acknowledgment disabled The INTyy request is held pending and 146 User's Manual U14826EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS 14.4.4 Interrupt request pending Some instructions may keep pending the acknowledgment of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution. instruction). * Manipulation instruction for interrupt request flag register 0 (IF0) * Manipulation instruction for interrupt mask flag register 0 (MK0) The following shows such instructions (interrupt request pending User's Manual U14826EJ4V0UD 147 CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function and Configuration 15.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes: (1) HALT mode This mode is set when the HALT instruction is executed. HALT mode stops the operation clock of the CPU. The system clock oscillator continues oscillating. This mode does not reduce the current consumption as much as STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) STOP mode This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock oscillator and stops the entire system. The current consumption of the CPU can be substantially reduced in this mode. The low voltage (VDD = 1.8 V max.) of the data memory can be retained. Therefore, this mode is useful for retaining the contents of the data memory at an extremely low current consumption. STOP mode can be released by an interrupt request, so that this mode can be used for intermittent operation. However, some time is required until the system clock oscillator stabilizes after STOP mode has been released. If processing must be resumed immediately by using an interrupt request, therefore, use the HALT mode. In both modes, the previous contents of the registers, flags, and data memory before setting standby mode are all retained. In addition, the statuses of the output latches of the I/O ports and output buffers are also retained. Caution To set STOP mode, be sure to stop the operations of the peripheral hardware, and then execute the STOP instruction. 148 User's Manual U14826EJ4V0UD CHAPTER 15 STANDBY FUNCTION 15.1.2 Standby function control register The wait time after STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time selection register (OSTS)Note. OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET release varies for each product not depending on the OSTS. PD789860: Oscillation stabilization time can be selected from 215/fX or 217/fX by mask option. PD78E9860A: Oscillation stabilization time is fixed to 215/fX and cannot be selected by mask option. PD789861, 78E9861A: Oscillation stabilization time is fixed to 27/fCC and cannot be selected by mask option. Note PD789860 Subseries only. There is no oscillation stabilization time selection register in the PD789861 Subseries. The oscillation stabilization time of the PD789861 Subseries is fixed at 27/fCC. Figure 15-1. Format of Oscillation Stabilization Time Selection Register Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 Address FFFAH After reset 04H R/W R/W OSTS2 0 0 1 OSTS1 0 1 0 OSTS0 0 0 0 212/fX (819 Oscillation stabilization time selection s) 215/fX (6.55 ms) 217/fX (26.2 ms) Setting prohibited Other than above Caution The wait time after STOP mode is released does not include the time from STOP mode release to clock oscillation start ("a" in the figure below), regardless of release by RESET input or by interrupt generation. STOP mode release X1 pin voltage waveform a Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U14826EJ4V0UD 149 CHAPTER 15 STANDBY FUNCTION 15.2 Standby Function Operation 15.2.1 HALT mode (1) HALT mode HALT mode is set by executing the HALT instruction. The operation statuses in HALT mode are shown in the following table. Table 15-1. Operation Statuses in HALT Mode Item System clock HALT Mode Operation Status System clock oscillation enabled Clock supply to CPU stopped CPU EEPROM Port (output latch) 8-bit timer TM30 TM40 Watchdog timer Power-on-clear circuit POC LVI Operation stopped Operation enabled Note 1 Remains in the state existing before HALT mode has been set Operation enabled Operation enabled Operation enabled Operation enabled Operation enabled Operation enabled Operation stopped Note 2 Bit sequential buffer Key return circuit Notes 1. HALT mode can be set after executing a write instruction. 2. If a POC switching circuit is selected by the mask option and the POC circuit is set to operation enabled by software or if POC circuit normally operating is selected by the mask option (see CHAPTER 18 MASK OPTIONS regarding mask options). 150 User's Manual U14826EJ4V0UD CHAPTER 15 STANDBY FUNCTION (2) Releasing HALT mode HALT mode can be released by the following three sources: (a) Releasing by unmasked interrupt request HALT mode is released by an unmasked interrupt request. disabled, the instruction at the next address is executed. Figure 15-2. Releasing HALT Mode by Interrupt HALT instruction Standby release signal Operating mode In this case, if interrupt request acknowledgment is enabled, vectored interrupt servicing is performed. If interrupt acknowledgment is Wait HALT mode Wait Oscillation Operating mode Clock Remarks 1. The broken lines indicate the case where the interrupt request that has released standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt servicing is performed: 9 to 10 clocks * When vectored interrupt servicing is not performed: 1 to 2 clocks (b) Releasing by non-maskable interrupt request HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt servicing is performed. User's Manual U14826EJ4V0UD 151 CHAPTER 15 STANDBY FUNCTION (c) Releasing by RESET input When HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution starts. Figure 15-3. Releasing HALT Mode by RESET Input HALT instruction RESET signal Operating mode Reset period Oscillation stop WaitNote HALT mode Oscillation Oscillation stabilization wait status Oscillation Operating mode Clock Note 15 17 In the PD789860, 2 /fX or 2 /fX can be selected by using the mask option. In the PD78E9860A, 215/fX: 6.55 ms (@fX = 5.0 MHz operation) In the PD789861 and 78E9861A, 27/fCC: 128 s (@fCC = 1.0 MHz operation) Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) Table 15-2. Operation After Releasing HALT Mode Releasing Source Maskable interrupt request MKxx 0 0 1 Non-maskable interrupt request RESET input - - IE 0 1 x x - Operation Executes next address instruction. Executes interrupt servicing. Retains HALT mode. Executes interrupt servicing. Reset processing x: don't care 152 User's Manual U14826EJ4V0UD CHAPTER 15 STANDBY FUNCTION 15.2.2 STOP mode (1) Setting and operation status of STOP mode STOP mode is set by executing the STOP instruction. Caution Because standby mode can be released by an interrupt request signal, standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. When STOP mode is set, therefore, HALT mode is set immediately after the STOP instruction has been executed, the oscillation stabilization time elapses, and then the operation mode is set. The operation statuses in STOP mode are shown in the following table. Table 15-3. Operation Statuses in STOP Mode Item System clock STOP Mode Operation Status System clock oscillation stopped Clock supply to CPU stopped CPU EEPROM Port (output latch) 8-bit timer TM30 TM40 Watchdog timer Power-on-clear circuit Bit sequential buffer Key return circuit POC LVI Operation stopped Operation stopped Remains in the state existing before STOP mode has been set Operation enabled Operation enabled Operation stopped Operation enabled Operation stopped Operation enabled Operation enabled Note 4 Note 3 Note 1 Note 2 Notes 1. Operation enabled only when cascade connected with TM40 (external clock selected for count clock) 2. Operation enabled only when external clock is selected for count clock 3. If a POC switching circuit is selected by the mask option and the POC circuit is set to operation enabled by software or if POC circuit normally operating is selected by the mask option (see CHAPTER 18 MASK OPTIONS regarding mask options). 4. Operation enabled only when external clock is selected for TM40 count clock and INTTM40 occurs User's Manual U14826EJ4V0UD 153 CHAPTER 15 STANDBY FUNCTION (2) Releasing STOP mode STOP mode can be released by the following two sources: (a) Releasing by unmasked interrupt request STOP mode is released by an unmasked interrupt request. In this case, vectored interrupt servicing is performed if interrupt acknowledgment is enabled after the oscillation stabilization time has elapsed. If interrupt acknowledgment is disabled, the instruction at the next address is executed. Figure 15-4. Releasing STOP Mode by Interrupt WaitNote (time set by OSTS) STOP instruction Standby release signal Operating mode Oscillation STOP mode Oscillation stop Oscillation stabilization wait status Oscillation Operating mode Clock Note There is no OSTS in the PD789861 Subseries, and the wait is fixed at 27/fCC. Remark The broken lines indicate the case where the interrupt request that has released standby mode is acknowledged. 154 User's Manual U14826EJ4V0UD CHAPTER 15 STANDBY FUNCTION (b) Releasing by RESET input When STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 15-5. Releasing STOP Mode by RESET Input STOP instruction RESET signal Operating mode Oscillation Reset period Oscillation stabilization wait status Oscillation Operating mode WaitNote STOP mode Oscillation stop Clock Note 15 17 In the PD789860, 2 /fX or 2 /fX can be selected by using the mask option. In the PD78E9860A, 215/fX: 6.55 ms (@fX = 5.0 MHz operation) In the PD789861 and 78E9861A, 27/fCC: 128 s (@fCC = 1.0 MHz operation) Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) Table 15-4. Operation After Releasing STOP Mode Releasing Source Maskable interrupt request MKxx 0 0 1 RESET input - IE 0 1 x - Operation Executes next address instruction. Executes interrupt servicing. Retains STOP mode. Reset processing x: don't care User's Manual U14826EJ4V0UD 155 CHAPTER 16 RESET FUNCTION The following three operations are available to generate reset signals. (1) (2) (3) External reset input by RESET signal input Internal reset by watchdog timer inadvertent program loop time detection Internal reset by comparison of POC circuit power supply voltage and detection voltage External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by reset signal input. When a low level is input to the RESET pin, the watchdog timer overflows, or POC circuit voltage is detected, a reset is applied and each hardware is set to the status shown in Table 16-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset clear. When a high level is input to the RESET pin, the reset is cleared and program execution is started after the oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared after reset, and program execution is started after the oscillation stabilization time has elapsed (see Figures 16-2 to 16-4). Cautions 1. For an external reset, input a low level of 10 s or more to the RESET pin. 2. When STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pins become high impedance. Figure 16-1. Block Diagram of Reset Function RESET Reset signal Reset controller POC circuit Count clock Watchdog timer Stop Overflow Interrupt function 156 User's Manual U14826EJ4V0UD CHAPTER 16 RESET FUNCTION Figure 16-2. Reset Timing by RESET Input X1, CL1 Normal operation Reset period (oscillation stops) Oscillation stabilization time wait Normal operation (reset processing) RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 16-3. Reset Timing by Watchdog Timer Overflow X1, CL1 Normal operation Watchdog timer overflow Reset period (oscillation continues) Oscillation stabilization time wait Normal operation (reset processing) Internal reset signal Port pin Hi-Z Figure 16-4. Reset Timing by RESET Input in STOP Mode X1, CL1 STOP instruction execution Stop status (oscillation Normal operation stops) RESET Reset period (oscillation stops) Oscillation stabilization time wait Normal operation (reset processing) Internal reset signal Delay Port pin Delay Hi-Z User's Manual U14826EJ4V0UD 157 CHAPTER 16 RESET FUNCTION Table 16-1. Status of Hardware After Reset Hardware Program counter (PC) Note 1 Status After Reset The contents of the reset vector table (0000H, 0001H) are set Stack pointer (SP) Program status word (PSW) EEPROM RAM Write control register (EEWC10) Data memory General-purpose registers Ports (P0, P2) (output latch) Port mode registers (PM0, PM2) Processor clock control register (PCC) Oscillation stabilization time selection register (OSTS) 8-bit timer Note 3 Undefined 02H 08H Undefined Undefined 00H FFH 02H 04H 00H Undefined 00H 00H 00H 00H 00H 00H 00H Undefined 00H 00H FFH Note 4 Note 2 Note 2 Timer counters (TM30, TM40) Compare registers (CR30, CR40, CRH40) Mode control registers (TMC30, TMC40) Carrier generator output control register (TCA40) Watchdog timer Timer clock selection register s (TCL2) Mode register (WDTM) Power-on-clear circuit Power-on-clear register (POCF1) Low-voltage detection register (LVIF1) Low-voltage detection level selection register (LVIS1) Bit sequential buffer Data registers (BSFRL10, BSFRH10) Output control register (BSFC10) Interrupts Request flag register (IF0) Mask flag register (MK0) Notes 1. While a reset signal is being input, and during the oscillation stabilization time wait, the contents of the PC will be undefined, while the remainder of the hardware will be the same as after the reset. 2. In standby mode, the RAM enters the hold state after a reset. 3. PD789860 Subseries only 4. This value is 04H only after a power-on-clear reset. 158 User's Manual U14826EJ4V0UD CHAPTER 17 PD78E9860A, 78E9861A EEPROM versions in the PD789860, 789861 Subseries include the PD78E9860A and 78E9861A. The PD78E9860A replaces the internal ROM of the PD789860 with EEPROM. The PD78E9861A replaces the internal ROM of the PD789861 with EEPROM. The differences between the PD78E9860A, 78E9861A and the mask ROM versions are shown in Table 17-1. Table 17-1. Differences Between PD78E9860A, 78E9861A and Mask ROM Versions Part Number Item Internal memory Program memory ROM structure ROM capacity Data memory High-speed RAM EEPROM System clock 32 bytes Ceramic/crystal oscillation IC pin VPP pin P40 to P43 pull-up resistor by mask option POC circuit selection by mask option Oscillation stabilization time after STOP mode is released by interrupt request Not provided Can select 2 /fX, 2 /fX, or 2 /fX by OSTS register Oscillation stabilization time after STOP mode release by RESET or reset release via POC circuit Power supply voltage (VDD) Electrical specifications 1.8 to 5.5 V 1.8 to 3.6 V 2 /fX 15 15 17 12 EEPROM Versions Mask ROM Versions PD78E9860A EEPROM PD78E9861A PD789860 Mask ROM PD789861 4 KB 128 bytes RC oscillation Ceramic/crystal oscillation Provided Not provided Provided RC oscillation Not provided Provided Not provided Provided 2 /fCC 7 Can select 2 /fX, 2 /fX, or 2 /fX by OSTS register 15 17 12 2 /fCC 7 2 /fCC 7 Can select 2 /fX or 2 /fX by mask option 1.8 to 5.5 V 17 15 2 /fCC 7 1.8 to 3.6 V Varies depending on EEPROM or mask ROM version. Caution There are differences in noise immunity and noise radiation between the EEPROM and mask ROM versions. When pre-producing an application set with the EEPROM version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. User's Manual U14826EJ4V0UD 159 CHAPTER 17 PD78E9860A, 78E9861A 17.1 EEPROM Features (Program Memory) The on-chip program memory in the PD78E9860A and 78E9861A is EEPROM. This chapter describes the functions of the EEPROM incorporated in the program memory area. For the EEPROM incorporated in data memory, see CHAPTER 5 EEPROM (DATA MEMORY). EEPROM can be written with the PD78E9860A and 78E9861A mounted on the target system (on-board). Connect the dedicated flash writer (Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the host machine and target system to write to EEPROM. Remark FL-PR3 and FL-PR4 are products of Naito Densei Machida Mfg. Co., Ltd (TEL +81-45-475-4191). Programming using EEPROM has the following advantages. * Software can be modified after the microcontroller is solder-mounted on the target system. * Distinguishing software facilities small-quantity, varied model production * Easy data adjustment when starting mass production 17.1.1 Programming environment The following shows the environment required for PD78E9860A, 78E9861A EEPROM programming. When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1). For details, refer to the manuals for Flashpro III/Flashpro IV. Remark USB is supported by Flashpro IV only. Figure 17-1. Environment for Writing Program to EEPROM (Program Memory) VPP RS-232C USB Dedicated flash programmer Host machine VDD VSS RESET Pseudo 3-wire PD78E9860A, PD78E9861A 160 User's Manual U14826EJ4V0UD CHAPTER 17 PD78E9860A, 78E9861A 17.1.2 Communication mode Use the communication mode shown in Table 17-2 to perform communication between the dedicated flash programmer and PD78E9860A, 78E9861A. Table 17-2. Communication Mode List Communication Mode COMM PORT Pseudo 3-wire Port A (Pseudo3 wire) 100 Hz to 1 kHz SIO Clock TYPE Setting Note 1 Pins Used Note 1 Number of VPP Pulses CPU CLOCK In Flashpro 1, 2, 4, 5 MHz Notes 2, 3 Multiple Rate 1.0 P02 (serial data input) P01 (serial data output) P00 (serial clock input) On Target Board 1 to 5 MHz Note 2 12 Notes 1. Be sure to use In Flashpro (system clock is supplied from a dedicated flash writer) with the PD78E9861A. 2. The possible setting range differs depending on the voltage. ELECTRICAL SPECIFICATIONS. 3. 2 or 4 MHz only with Flashpro III Figure 17-2. Communication Mode Selection Format 10 V VPP VDD VSS VPP pulse 1 2 n For details, see CHAPTER 20 VDD RESET VSS User's Manual U14826EJ4V0UD 161 CHAPTER 17 PD78E9860A, 78E9861A Figure 17-3. Example of Connection with Dedicated Flash Programmer (a) Pseudo 3-wire (PD78E9860A) Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLKNote GND VPP VDD RESET P00 (serial clock) P02 (serial input) P01 (serial output) X1 VSS PD78E9860A (b) Pseudo 3-wire (PD78E9861A) Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLK GND VPP VDD RESET P00 (serial clock) P02 (serial input) P01 (serial output) P03 VSS PD78E9861A Note When supplying the system clock from a dedicated flash writer, connect the CLK and X1 pins and cut off the resonator on the board. When using the clock oscillated by the on-board resonator, do not connect the CLK pin. Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. When using the power supply connected to the VDD pin, supply voltage before starting programming. 162 User's Manual U14826EJ4V0UD CHAPTER 17 PD78E9860A, 78E9861A If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, the following signals are generated for the PD78E9860A, 78E9861A. For details, refer to the manual of Flashpro III/Flashpro IV. Table 17-3. Pin Connection List Signal Name VPP1 VPP2 VDD GND CLK I/O - Output I/O Output - Write voltage - VDD voltage generation/voltage monitoring Ground Clock output VDD VSS X1 (PD78E9860A) P03 (PD78E9861A) RESET SI SO SCK HS Output Input Output Output Input Reset signal Receive signal Transmit signal Transfer clock Handshake signal RESET P01 P02 P00 - x Pin Function VPP - x Note Pin Name Pseudo 3-Wire Note VDD voltage must be supplied before programming is started. Remark x: : Pin must be connected. : If the signal is supplied on the target board, pin does not need to be connected. Pin does not need to be connected. User's Manual U14826EJ4V0UD 163 CHAPTER 17 PD78E9860A, 78E9861A 17.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and EEPROM programming mode may be required in some cases. A VPP pin connection example is shown below. Figure 17-4. VPP Pin Connection Example PD78E9860A, 78E9861A Connection pin of dedicated flash programmer VPP Pull-down resistor (RVPP) Serial Interface Pseudo 3-wire Pins Used P02, P01, P00 When connecting the dedicated flash programmer to a serial interface pin that is connected to another device onboard, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken with such connections. 164 User's Manual U14826EJ4V0UD CHAPTER 17 PD78E9860A, 78E9861A (1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status. Figure 17-5. Signal Conflict (Input Pin of Serial Interface) PD78E9860A, 78E9861A Signal conflict Input pin Other device Output pin Connection pin of dedicated flash programmer In the EEPROM programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict; therefore, isolate the signal of the other device. (2) Abnormal operation of other device If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the signals input to the other device are ignored. Figure 17-6. Abnormal Operation of Other Device PD78E9860A, 78E9861A Connection pin of dedicated flash programmer Other device Input pin Pin If the signal output by the PD78E9860A, 78E9861A affects another device in the EEPROM programming mode, isolate the signals of the other device. PD78E9860A, 78E9861A Connection pin of dedicated flash programmer Other device Input pin Pin If the signal output by the dedicated flash programmer affects another device in the EEPROM programming mode, isolate the signals of the other device. User's Manual U14826EJ4V0UD 165 CHAPTER 17 PD78E9860A, 78E9861A PD78E9860A, 78E9861A Therefore, do not input other than reset signals from the dedicated flash Signal conflict RESET Connection pin of dedicated flash programmer Reset signal generator Output pin The signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the EEPROM programming mode, so isolate the signal of the reset signal generator. 166 User's Manual U14826EJ4V0UD CHAPTER 17 PD78E9860A, 78E9861A 17.1.4 Connection of adapter for EEPROM writing The following figures show the examples of recommended connection when the adapter for EEPROM writing is used. Figure 17-8. Wiring Example for EEPROM Writing Adapter with Pseudo 3-Wire (1/2) (a) PD78E9860A VDD (2.7 to 5.5 V) GND 1 2 3 PD78E9860A 20 19 18 17 16 15 14 13 12 11 GND VDD VDD2 (LVDD) 4 5 6 7 8 9 10 SI SO SCK CLKOUT RESET VPP RESERVE/HS User's Manual U14826EJ4V0UD 167 CHAPTER 17 PD78E9860A, 78E9861A Figure 17-8. Wiring Example for EEPROM Writing Adapter with Pseudo 3-Wire (2/2) (b) PD78E9861A VDD (2.7 to 3.6 V) GND 1 2 3 PD78E9861A 20 19 18 17 16 15 14 13 12 11 GND VDD VDD2 (LVDD) 4 5 6 7 8 9 10 SI SO SCK CLKOUT RESET VPP RESERVE/HS 168 User's Manual U14826EJ4V0UD CHAPTER 18 MASK OPTIONS The PD789860 and 789861 have the following mask options. * P40 to P43 mask options On-chip pull-up resistors can be selected in bit units. <1> Specify on-chip pull-up resistors <2> Do not specify on-chip pull-up resistors * POC circuit mask options The POC circuit can be selected. <1> Select POC switching circuit (POC circuit operation control by software is possible) <2> Select POC circuit normally operating <3> Select POC circuit normally halted * Oscillation stabilization wait time (PD789860 only) The oscillation stabilization wait time after the release of STOP mode by RESET or the release of reset via the POC circuit can be selected. <1> 215/fX <2> 217/fX User's Manual U14826EJ4V0UD 169 CHAPTER 19 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the PD789860, 789861 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E). 19.1 Operation 19.1.1 Operand identifiers and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). described as they are. Each symbol has the following meaning. * #: * !: * $: * [ ]: Immediate data specification Absolute address specification Relative address specification Indirect address specification When there are two or more description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are key words and are In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 19-1. Operand Identifiers and Description Methods Identifier r rp sfr saddr saddrp addr16 addr5 word byte bit Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even addresses only) 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) 0040H to 007FH Immediate data or labels (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label Remark For symbols of special function registers, see Table 4-3 Special Function Registers. 170 User's Manual U14826EJ4V0UD CHAPTER 19 INSTRUCTION SET OVERVIEW 19.1.2 Description of "Operation" column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: IE: NMIS: ( ): xH, xL: : : : : addr16: jdisp8: A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicating non-maskable interrupt servicing in progress Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16-bit register Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) Inverted data 16-bit immediate data or label Signed 8-bit data (displacement value) 19.1.3 Description of "Flag" column (Blank): 0: 1: x: R: Unchanged Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is stored User's Manual U14826EJ4V0UD 171 CHAPTER 19 INSTRUCTION SET OVERVIEW 19.2 Operation List Mnemonic Operand Bytes Clocks Operation Z MOV r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A XCH A, X A, r A, saddr A, sfr A, [DE] A, [HL] A, [HL, byte] Note 2 Note 1 Flag AC CY 3 3 3 2 2 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 2 2 2 1 1 2 6 6 6 4 4 4 4 4 4 8 8 6 4 4 6 6 6 6 6 6 4 6 6 6 8 8 8 r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A AX Ar A (saddr) A sfr A (DE) A (HL) A (HL + byte) x x x x x x Note 1 Notes 1. Except r = A. 2. Except r = A, X. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 172 User's Manual U14826EJ4V0UD CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Z Flag AC CY MOVW rp, #word AX, saddrp saddrp, AX AX, rp rp, AX Note 3 2 2 1 1 1 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 6 6 8 4 4 8 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 rp word AX (saddrp) (saddrp) AX AX rp rp AX AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Note XCHW ADD AX, rp A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] Note ADDC A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] SUB A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U14826EJ4V0UD 173 CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Z Flag AC CY x x x x x x x x x x x x x x SUBC A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) x x x x x x x x x x x x x x x x x x x x x x x x x x x x AND A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] OR A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] XOR A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 174 User's Manual U14826EJ4V0UD CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Z Flag AC CY x x x x x x x x x x x x x x x x x x x x x x x x CMP A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] 2 3 2 2 3 1 2 3 3 3 2 2 2 2 1 1 1 1 1 1 3 3 2 3 2 3 3 2 3 2 1 1 1 4 6 4 4 8 6 6 6 6 6 4 4 4 4 4 4 2 2 2 2 6 6 4 6 10 6 6 4 6 10 2 2 2 A - byte (saddr) - byte A-r A - (saddr) A - (addr16) A - (HL) A - (HL + byte) AX, CY AX + word AX, CY AX - word AX - word rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am-1 Am) x 1 (CY, A0 A7, Am+1 Am) x 1 (CY A0, A7 CY, Am-1 Am) x 1 (CY A7, A0 CY, Am+1 Am) x 1 (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (HL).bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY x x x x x x x x x x x x x x ADDW SUBW CMPW INC AX, #word AX, #word AX, #word r saddr DEC r saddr INCW DECW ROR ROL RORC ROLC SET1 rp rp A, 1 A, 1 A, 1 A, 1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x x x x x x CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x x SET1 CLR1 NOT1 CY CY CY 1 0 x Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U14826EJ4V0UD 175 CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Z Flag AC CY CALL !addr16 3 6 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 4 + jdisp8 if PSW.bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW.bit = 0 B B - 1, then PC PC + 2 + jdisp8 if B 0 C C - 1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode R R R R R R CALLT [addr5] 1 8 RET RETI 1 1 6 8 PUSH PSW rp 1 1 1 1 2 2 3 2 1 2 2 2 2 4 4 3 4 4 4 3 4 2 2 3 2 4 4 6 8 6 6 6 6 6 6 6 6 10 10 8 10 10 10 8 10 6 6 8 POP PSW rp MOVW SP, AX AX, SP BR !addr16 $addr16 AX BC BNC BZ BNZ BT $saddr16 $saddr16 $saddr16 $saddr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 BF saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 DBNZ B, $addr16 C, $addr16 saddr, $addr16 NOP EI DI HALT STOP 1 3 3 1 1 2 6 6 2 2 Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 176 User's Manual U14826EJ4V0UD CHAPTER 19 INSTRUCTION SET OVERVIEW 19.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote MOV XCHNote ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP INC DEC B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV PUSH POP [DE] [HL] [HL + byte] MOV MOV MOV MOV MOV DBNZ INC DEC DBNZ ROR ROL RORC ROLC #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 1 None Note Except r = A. User's Manual U14826EJ4V0UD 177 CHAPTER 19 INSTRUCTION SET OVERVIEW (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word AX rp Note saddrp SP None 1st Operand AX ADDW SUBW CMPW rp MOVW MOVW Note MOVW XCHW MOVW MOVW INCW DECW PUSH POP saddrp sp MOVW MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand 1st Operand A.bit BT BF sfr.bit BT BF saddr.bit BT BF PSW.bit BT BF [HL].bit SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 CY SET1 CLR1 NOT1 $addr16 None 178 User's Manual U14826EJ4V0UD CHAPTER 19 INSTRUCTION SET OVERVIEW (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand 1st Operand Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ AX !addr16 [addr5] $addr16 (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User's Manual U14826EJ4V0UD 179 CHAPTER 20 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol VDD VPP Input voltage Output voltage Output current, high VI VO IOH Per pin Total of all pins Output current, low IOL Per pin Total of all pins Operating ambient temperature Storage temperature TA Tstg Conditions Ratings -0.3 to +6.5 Unit V V V V mA mA mA mA C C PD78E9860A, 78E9861A only, Note -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -10 -30 30 80 -40 to +85 -40 to +125 Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the EEPROM (program memory) is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the operating voltage range of VDD (see b in the figure below). 1.8 V 0V a b VDD VPP 1.8 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum rating are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions the ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 180 User's Manual U14826EJ4V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS System Clock Oscillator Characteristics Ceramic or crystal oscillation (PD789860, 78E9860A) (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fX) Note 1 Conditions VDD = Oscillation voltage range MIN. 1.0 TYP. MAX. 5.0 Unit MHz VSS X2 X1 Oscillation stabilization time Note 2 After VDD reaches oscillation voltage range MIN. 4 ms Crystal resonator VSS X2 X1 Oscillation frequency (fX) Note 1 1.0 5.0 MHz Oscillation stabilization time External clock Note 2 30 ms X1 X2 X1 input frequency (fX) Note 1 1.0 5.0 MHz X1 input high-/lowlevel width(tXH,tXL) 85 500 ns Notes. 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Caution When using a ceramic or crystal oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross with other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant of the PD78E9860A, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. User's Manual U14826EJ4V0UD 181 CHAPTER 20 ELECTRICAL SPECIFICATIONS Recommended Oscillator Constant Ceramic Resonator (TA = -40 to +85C) (Mask ROM version) Manufacturer Part Number Frequency (MHz) Recommended Circuit Constant (pF) C1 Murata Mfg. Co., Ltd. CSBLA1M00J58-B0 CSBFB1M00J58-B0 CSTLS2M00G56-B0 2.0 1.0 100 100 - - 4.0 - - 4.19 - - 4.91 - - 5.0 - - C2 100 100 - - - - - - - - - - MIN. 2.1 2.1 1.8 Oscillation Voltage Range (VDD) MAX. 5.5 5.5 5.5 On-chip capacitor CSTCC2M00G56-B0 1.8 5.5 On-chip capacitor CSTLS4M00G53-B0 1.8 5.5 On-chip capacitor CSTCR4M00G53-R0 1.8 5.5 On-chip capacitor CSTLS4M19G53-B0 1.8 5.5 On-chip capacitor CSTCR4M19G53-R0 1.8 5.5 On-chip capacitor CSTLS4M91G53-B0 1.9 5.5 On-chip capacitor CSTCR4M91G53-R0 1.8 5.5 On-chip capacitor CSTLS5M00G53-B0 1.9 5.5 On-chip capacitor CSTCR5M00G53-R0 1.8 5.5 On-chip capacitor Remark Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 182 User's Manual U14826EJ4V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS RC oscillation (PD789861, 78E9861A) (TA = -40 to +85C, VDD = 1.8 to 3.6 V) Resonator RC oscillator Recommended Circuit CL1 CL2 Parameter Conditions MIN. TYP. MAX. Unit Oscillation frequency (fCC) Notes 1,2 VDD = Oscillation voltage range 0.85 1.15 MHz External clock CL1 CL2 CL1 input frequency (fCC) Note 1 1.0 5.0 MHz CL1 input high-/lowlevel width (tXH,tXL) 85 500 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Variations due to external resistance and external capacitance are not included. Caution When using an RC oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross with other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. User's Manual U14826EJ4V0UD 183 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (PD789860, 78E9860A) (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Output current, low Symbol IOL Per pin All pins Output current, high IOH Per pin All pins Input voltage, high VIH1 P00 to P07 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIH2 RESET, P20, P21, P40 to P43 VIH3 Input voltage, low VIL1 X1, X2 P00 to P07 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIL2 RESET, P20, P21, P40 to P43 VIL3 Output voltage, high VOH1 VOH2 Output voltage, low VOL1 VOL2 Input leakage current, high ILIH1 X1, X2 P00 to P07, P20, P21 P00 to P07, P20, P21 VI = VDD IOH = -100 A IOH = -500 A IOL = 400 A IOL = 2 mA Pins other than X1, X2 ILIH2 Input leakage current, low ILIL1 VI = 0 V X1, X2 Pins other than X1, X2 ILIL2 Output leakage current, high ILOH VO = VDD P00 to P07, P20, P21 Output leakage current, low Note Conditions MIN. TYP. MAX. 3 7.5 -0.75 -7.5 Unit mA mA mA mA V V V V V V V V V V V V 0.7VDD 0.9VDD 0.8VDD 0.9VDD VDD - 0.1 0 0 0 0 0 VDD - 0.5 VDD - 0.7 VDD VDD VDD VDD VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 2.7 VDD 5.5 V 1.8 VDD < 2.7 V 2.7 VDD 5.5 V 1.8 VDD < 2.7 V 0.5 0.7 3 V V A A A A A A k 20 -3 X1, X2 -20 3 ILOL VO = 0 V P00 to P07, P20, P21 -3 Mask-option pull-up resistor R VIN = 0 V P40 to P43 50 100 200 Note PD789860 only. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 184 User's Manual U14826EJ4V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (PD789861, 78E9861A) (TA = -40 to +85C, VDD = 1.8 to 3.6 V) Parameter Output current, low Symbol IOL Per pin All pins Output current, high IOH Per pin All pins Input voltage, high VIH1 P00 to P07 2.7 VDD 3.6 V 1.8 VDD < 2.7 V VIH2 RESET, P20, P21, P40 to P43 VIH3 Input voltage, low VIL1 CL1, CL2 P00 to P07 2.7 VDD 3.6 V 1.8 VDD < 2.7 V VIL2 RESET, P20, P21, P40 to P43 VIL3 Output voltage, high VOH1 VOH2 Output voltage, low VOL1 VOL2 Input leakage current, high ILIH1 CL1, CL2 P00 to P07, P20, P21 P00 to P07, P20, P21 VI = VDD IOH = -100 A IOH = -500 A IOL = 400 A IOL = 2 mA Pins other than CL1, CL2 ILIH2 Input leakage current, low ILIL1 VI = 0 V CL1, CL2 Pins other than CL1, CL2 ILIL2 Output leakage current, high ILOH VO = VDD P00 to P07, P20, P21 Output leakage current, low Note Conditions MIN. TYP. MAX. 2 5.0 -0.5 -5.0 Unit mA mA mA mA V V V V V V V V V V V V 0.7VDD 0.9VDD 0.8VDD 0.9VDD VDD - 0.1 0 0 0 0 0 VDD - 0.5 VDD - 0.7 VDD VDD VDD VDD VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 2.7 VDD 3.6 V 1.8 VDD < 2.7 V 2.7 VDD 3.6 V 1.8 VDD < 2.7 V 0.5 0.7 3 V V A A A A A A k 20 -3 CL1, CL2 -20 3 ILOL VO = 0 V P00 to P07, P20, P21 -3 Mask-option pull-up resistor R VIN = 0 V P40 to P43 50 100 200 Note PD789861 only. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14826EJ4V0UD 185 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V (PD789860)) Parameter Power supply current Note Symbol IDD1 5.0 MHz Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% MIN. TYP. 1.1 MAX. 2.2 Unit mA Ceramic/crystal oscillation crystal oscillation operating mode (EEPROM halted) C1 = C2 = 22 pF IDD2 5.0 MHz crystal oscillation operating mode (EEPROM halted) C1 = C2 = 22 pF IDD3 5.0 MHz crystal oscillation HALT mode (EEPROM halted) C1 = C2 = 22 pF IDD4 STOP mode (POC operating) 0.3 0.6 mA 0.8 1.6 mA 0.5 1.0 mA 1.5 3.0 mA 0.6 1.2 mA VDD = 5.0 V TA = -40 to +85C VDD = 3.0 V 10% TA = -40 to +85C VDD = 5.0 V TA = -20 to +75C VDD = 3.0 V 10% TA = -20 to +75C 1.2 4.0 A A A A A A A 1.0 2.5 1.2 3.0 1.0 1.5 IDD5 STOP mode (POC operation halted) VDD = 5.0 V TA = -40 to +85C VDD = 3.0 V 10% TA = -40 to +85C VDD = 5.0 V TA = 25C 3.0 0.7 0.9 Note Port current (including current flowing in on-chip pull-up resistors) is not included. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 186 User's Manual U14826EJ4V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V (PD789861)) Parameter Power supply current RC oscillation Note Symbol IDD1 1.0 MHz Conditions VDD = 3.0 V 10% MIN. TYP. 0.4 MAX. 0.8 Unit mA RC oscillation operating mode (EEPROM halted) R = 24 k, C = 30 pF IDD2 1.0 MHz RC oscillation operating mode (EEPROM halted) R = 24 k, C = 30 pF IDD3 1.0 MHz RC oscillation HALT mode (EEPROM halted) R = 24 k, C = 30 pF IDD4 STOP mode (POC operating) VDD = 3.0 V 10% TA = -40 to +85C VDD = 3.0 V 10% TA = -20 to +75C IDD5 STOP mode (POC operation halted) VDD = 3.0 V 10% TA = -40 to +85C 0.7 1.0 1.5 1.0 2.5 VDD = 3.0 V 10% 0.3 0.6 mA VDD = 3.0 V 10% 0.5 1.0 mA A A A Note Port current (including current flowing in on-chip pull-up resistors) is not included. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14826EJ4V0UD 187 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V (PD78E9860A), VDD = 1.8 to 3.6 V (PD78E9861A)) Parameter Power supply current Ceramic/crystal oscillation: Note Symbol IDD1 Conditions 5.0 MHz crystal oscillation operating mode (EEPROM halted) C1 = C2 = 22 pF 5.0 MHz crystal oscillation operating mode (EEPROM halted) C1 = C2 = 22 pF VDD = 3.0 V 10% MIN. TYP. 2.5 MAX. 5.0 Unit mA PD78E9860A IDD2 VDD = 3.0 V 10% 3.0 6.0 mA IDD3 4.19 MHz VDD = 3.0 V 10% crystal oscillation HALT mode (EEPROM halted) C1 = C2 = 22 pF STOP mode (POC operating) VDD = 5.0 V TA = -40 to +85C VDD = 3.0 V 10% TA = -40 to +85C VDD = 5.0 V TA = -20 to +75C VDD = 3.0 V 10% TA = -20 to +75C 1.6 3.2 mA IDD4 1.2 1.0 4.0 2.5 3.0 A A A A A A A mA 1.0 2.0 3.0 1.5 0.9 IDD5 STOP mode (POC operation halted) VDD = 5.0 V TA = -40 to +85C VDD = 3.0 V 10% TA = -40 to +85C VDD = 5.0 V TA = 25C Power supply current RC oscillation: Note IDD1 PD78E9861A IDD2 VDD = 3.0 V 10% 1.0 MHz RC oscillation operating mode (EEPROM halted) R = 24 k, C = 30 pF VDD = 3.0 V 10% 1.0 MHz RC oscillation operating mode (EEPROM halted) R = 24 k, C = 30 pF 1.0 MHz RC oscillation HALT mode (EEPROM halted) R = 24 k, C = 30 pF STOP mode (POC operating) VDD = 3.0 V 10% 0.8 1.6 1.0 2.0 mA IDD3 0.7 1.4 mA IDD4 VDD = 3.0 V 10% TA = -40 to +85C VDD = 3.0 V 10% TA = -20 to +75C 1.0 1.0 2.5 2.0 1.5 A A A IDD5 STOP mode (POC operation halted) VDD = 3.0 V 10% Note Port current (including current flowing in on-chip pull-up resistors) is not included. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 188 User's Manual U14826EJ4V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS AC Characteristics (1) Basic operation (a) PD789860, 78E9860A (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time (minimum instruction execution time) Ceramic/crystal oscillation TMI input input frequency TMI high-/low-level width Key return input pin low-level width RESET low-level width tRSL 10 tTIH, tTIL tKRIL fTI 2.7 VDD 5.5 V 1.8 VDD < 2.7 V 2.7 VDD 5.5 V 1.8 VDD < 2.7 V KR10 to KR13 0 0 0.1 1.0 10 4.0 500 MHz kHz 1.8 VDD < 2.7 V 1.6 8 Symbol TCY Conditions 2.7 VDD 5.5 V MIN. 0.4 TYP. MAX. 8 Unit s s s s s s TCY vs. VDD (System Clock: Ceramic/Crystal Oscillation) 60 20 10 Cycle time TCY [ s] Guaranteed operation range 2.0 1.0 0.5 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD (V) User's Manual U14826EJ4V0UD 189 CHAPTER 20 ELECTRICAL SPECIFICATIONS (b) PD789861, 78E9861A (TA = -40 to +85C, VDD = 1.8 to 3.6 V) Parameter Cycle time (minimum instruction execution time) RC oscillation TMI input input frequency TMI high-/low-level width Key return input pin low-level width RESET low-level width tRSL 10 tTIH, tTIL tKRIL fTI 2.7 VDD 3.6 V 1.8 VDD < 2.7 V 2.7 VDD 3.6 V 1.8 VDD < 2.7 V KR10 to KR13 0 0 0.1 1.0 10 4.0 500 MHz kHz 1.8 VDD < 2.7 V 1.6 9.42 Symbol TCY Conditions 2.7 VDD 3.6 V MIN. 0.4 TYP. MAX. 9.42 Unit s s s s s s TCY vs. VDD (System Clock: RC Oscillation) 60 20 10 Cycle time TCY [s] Guaranteed operation range 2.0 1.0 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD (V) (2) RC frequency oscillation characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V) Parameter Symbol fCC Conditions R = 24 k, C = 30 pF MIN. 0.85 TYP. 1.00 MAX. 1.15 Unit MHz Oscillation frequency Note Note Variations due to external resistance and external capacitance are not included. 190 User's Manual U14826EJ4V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS AC Timing Measurement Points (Excluding X1, CL1 Input) 0.8VDD 0.2VDD Points of measurement 0.8VDD 0.2VDD Clock Timing 1/fCLK tXL tXH VIH3 (MIN.) VIL3 (MAX.) X1 (CL1) input Remark TMI Timing fCLK: fX or fCC 1/fTI tTIL tTIH TMI Key Return Input Timing tKRIL KR10 to KR13 RESET Input Timing tRSL RESET User's Manual U14826EJ4V0UD 191 CHAPTER 20 ELECTRICAL SPECIFICATIONS Power-on-Clear Circuit Characteristics (1) POC (a) DC characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V (PD789860, 78E9860A), VDD = 1.8 to 3.6 V (PD789861, 78E9861A)) Parameter Detection voltage Symbol VPOC Response time Conditions Note 1 MIN. 1.8 Note 2 TYP. 1.9 Note 2 MAX. 2.0 Unit V : 2 ms Notes 1. Time from detecting voltage until output reverses and time until stable operation after transition from halted state to operating state. 2. Note that the POC detection voltage may be lower than the operating voltage range of these products. (b) AC characteristics (TA = -40 to +85C) Parameter Power rise time Symbol TPth1 TPth2 TPth3 Conditions POC selector used POC normal operation POC normal operation VDD: 0 1.8 V VDD: 0 1.8 V VDD: 0 1.8 V TA = +25C MIN. 0.01 0.01 10 TYP. MAX. 100 100 Unit ms ms s (2) LVI (a) DC characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V (PD789860, 78E9860A), VDD = 1.8 to 3.6 V (PD789861, 78E9861A)) Parameter Symbol VLVI7 VLVI6 VLVI5 VLVI4 VLVI3 VLVI2 VLVI1 VLVI0 Response time Response time Response time Response time Response time Response time Response time Response time Conditions Note 1 MIN. 2.4 TYP. 2.6 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 MAX. 2.8 Unit V V V V V V V LVI7 detection voltage LVI6 detection voltage LVI5 detection voltage LVI4 detection voltage LVI3 detection voltage LVI2 detection voltage LVI1 detection voltage LVI0 detection voltage : 2 ms : 2 ms : 2 ms : 2 ms : 2 ms : 2 ms : 2 ms : 2 ms Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 3 2.0 2.2 V Notes 1. Time from detecting voltage until output reverses and time until stable operation after transition from halted state to operating state 2. Relative relationship: VLVI7 > VLVI6 > VLVI5 > VLVI4 > VLVI3 > VLVI2 > VLVI1 > VLVI0 3. VPOC < VLVI0 192 User's Manual U14826EJ4V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS EEPROM Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V (PD789860, 78E9860A), VDD = 1.8 to 3.6 V (PD789861, 78E9861A)) Parameter Write time Note 1 Symbol Conditions MIN. 3.3 TYP. MAX. 6.6 10 Unit ms 10,000 times Number of overwrites 32 bytes Note 2 Per byte 4 KB Per byte 100 times Notes 1. Write time = T x 145 (T = time of 1 clock cycle selected by EWCS100 to EWCS102) 2. PD78E9860A, 78E9861A only. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention power supply voltage Release signal set time tSREL Symbol VDDDR Conditions MIN. 1.8 1.8 10 TYP. MAX. 5.5 3.6 Unit V V PD789860, 78E9860A PD789861, 78E9861A STOP release by RESET pin s Data Retention Timing Internal reset operation HALT mode STOP mode Data retention mode Operation mode VDD VDDDR STOP instruction execution tSREL RESET tWAIT HALT mode STOP mode Data retention mode Operation mode VDD VDDDR STOP instruction execution tSREL Standby release signal (interrupt request) tWAIT User's Manual U14826EJ4V0UD 193 CHAPTER 20 ELECTRICAL SPECIFICATIONS Oscillation Stabilization Wait Time (a) Ceramic/crystal oscillator (TA = -40 to 85C, VDD = 1.8 to 5.5 V) (PD789860, 78E9860A) Parameter Oscillation wait time Note 1 Symbol TWAIT Conditions STOP release by RESET or reset release by POC Release by interrupt MIN. TYP. Note 2 MAX. Unit s Note 3 s Notes 1. Time required to stabilize oscillation after a reset or STOP mode release. 2. This is fixed to 215/fX in the PD78E9860A. In the PD789860, 215/fX or 217/fX can be selected by a mask option. 3. 212/fX, 215/fX, or 217/fX can be selected using bits 0 to 2 of the oscillation stabilization time selection register (OSTS0 to OSTS2). (b) RC oscillation (TA = -40 to +85C, VDD = 1.8 to 3.6 V) (PD789861, 78E9861A) Parameter Oscillation wait time Note Symbol TWAIT Conditions STOP release by RESET or reset release by POC Release by interrupt MIN. TYP. 2 /fCC 7 7 MAX. Unit s 2 /fCC s Note Time required to stabilize oscillation after a reset or STOP mode release. 194 User's Manual U14826EJ4V0UD CHAPTER 21 EXAMPLE OF RC OSCILLATION FREQUENCY CHARACTERISTICS (REFERENCE VALUES) fCC vs. VDD (RC Oscillation: PD789861, R = 24 k, C = 30 pF) (TA = 25C) CL1 CL2 24 k 30 pF 1.05 Sample A 1.0 Sample B Sample C 1.10 System clock frequency fCC [MHz] 0.95 0.90 1.5 2.0 3.0 Supply voltage VDD [V] 4.0 User's Manual U14826EJ4V0UD 195 CHAPTER 22 PACKAGE DRAWING 20-PIN PLASTIC SSOP (7.62 mm (300)) 20 11 detail of lead end F G T P E 1 A H I S 10 L U J N C D NOTE S K M M B ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 6.650.15 0.475 MAX. 0.65 (T.P.) 0.24+0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S20MC-65-5A4-2 Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 196 User's Manual U14826EJ4V0UD CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS The PD789860, 789861, 78E9860A, and 78E9861A should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index/html) Table 23-1. Surface Mounting Type Soldering Conditions (1/2) PD789860MC-xxx-5A4: 20-pin plastic SSOP (7.62 mm (300)) PD789861MC-xxx-5A4: 20-pin plastic SSOP (7.62 mm (300)) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: three times or less VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: three times or less Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 300C max. Time: 3 seconds max. (per pin row) - WS60-00-1 VP15-00-3 IR35-00-3 Caution Do not use different soldering method together (except for partial heating). User's Manual U14826EJ4V0UD 197 CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS Table 23-1. Surface Mounting Type Soldering Conditions (2/2) PD78E9860AMC-5A4: PD78E9861AMC-5A4: Soldering Method 20-pin plastic SSOP (7.62 mm (300)) 20-pin plastic SSOP (7.62 mm (300)) Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 3 days at 125C for 10 hours) Note IR35-103-2 (after that, prebake VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less, Exposure limit: 3 days 125C for 10 hours) Note VP15-103-2 (after that, prebake at Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature), Exposure limit: 3 days Note WS60-103-1 (after that, prebake at 125C for 10 hours) - Partial heating Pin temperature: 300C max. Time: 3 seconds max. (per pin row) Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering method together (except for partial heating). 198 User's Manual U14826EJ4V0UD APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the PD789860, 789861 Subseries. Figure A-1 shows development tools. * Compatibility with PC98-NX series Unless stated otherwise, products which are supported by IBM PC/ATTM and compatibles can also be used with the PC98-NX series. When using the PC98-NX series, therefore, refer to the explanations for IBM PC/AT and compatibles. * Windows Unless stated otherwise, "Windows" refers to the following operating systems. * Windows 3.1 * Windows 95, 98, 2000 * Windows NTTM Ver. 4.0 User's Manual U14826EJ4V0UD 199 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Software package * Software package Language processing software * Assembler package * C compiler package * Device file * C library source fileNote 1 Debugging software * Integrated debugger * System simulator Control software * Project Manager (Windows version only)Note 2 Host machine (PC or EWS) Interface adapter Power supply unit Flash memory writing environment Flash programmer In-circuit emulator Flash memory writing adapter Emulation board Flash memory Emulation probe Conversion socket or conversion adapter Target system Notes 1. A C library source file is not included in the software package. 2. The Project Manager is included in the assembler package. The Project Manager is used only in the Windows environment. 200 User's Manual U14826EJ4V0UD APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S Software package This is a package that bundles the software tools required for development of the 78K/0S Series. The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files Part number: SxxxxSP78K0S Remark xxxx in the part number differs depending on the operating system to be used. SxxxxSP78K0S xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows English Windows Supply Medium CD-ROM A.2 Language Processing Software RA78K0S Assembler package Program that converts program written in mnemonic into object code that can be executed by microcontroller. In addition, automatic functions to generate symbol table and optimize branch instructions are also provided. Used in combination with optional device file (DF789861). Note 1 File containing the information inherent to the device. Used in combination with other optional tools (RA78K0S, CC78K0S, ID78K0S-NS, or SM78K0S). Part number: SxxxxDF789861 CC78K0S-L Note 2 Source file of functions constituting object library included in C compiler package. Necessary for changing object library included in C compiler package according to customer's specifications. Since this is the source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0S-L C library source file Notes 1. DF789861 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S. 2. CC78K0S-L is not included in the software package (SP78K0S). User's Manual U14826EJ4V0UD 201 APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and operating system to be used. SxxxxRA78K0S SxxxxCC78K0S xxxx AB13 BB13 AB17 BB17 3P17 3K17 HP9000 series 700 SPARCstation TM TM Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows English Windows Japanese Windows English Windows HP-UX TM Supply Media 3.5" 2HD FD CD-ROM (Rel.10.10) (Rel.4.1.4), (Rel.2.5.1) SunOS Solaris TM TM SxxxxDF789861 SxxxxCC78K0S-L xxxx AB13 BB13 3P16 3K13 3K15 Host Machine PC-9800 series, IBM PC/AT and compatibles HP9000 series 700 SPARCstation OS Japanese Windows English Windows HP-UX (Rel.10.10) SunOS (Rel.4.1.4), Solaris (Rel.2.5.1) DAT 3.5" 2HD FD 1/4" CGMT Supply Media 3.5" 2HD FD A.3 Control Software Project Manager This is control software designed so that the user program can be efficiently developed in the Windows environment. With this software, a series of user program development operations, including starting the editor, build, and starting the debugger, can be executed on the Project Manager. A.4 EEPROM (Program Memory) Writing Tools Flashpro III (FL-PR3, PG-FP3) Flashpro IV (FL-PR4, PG-FP4) Flash programmer FA-20MC Flash memory (EEPROM) writing adapter Flash memory (EEPROM) writing adapter. Used in connection with Flashpro III or Flashpro IV. Flash programmer dedicated to the microcontrollers incorporating a flash memory (EEPROM) Remark FL-PR3, FL-PR4, and FA-20MC are products of Naito Densei Machida Mfg. Co., Ltd. For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191) 202 User's Manual U14826EJ4V0UD APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator In-circuit emulator for debugging hardware and software of application system using 78K/0S Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-78K0S-NS-A In-circuit emulator This in-circuit emulator has a coverage function in addition to the functions of the IE-78K0SNS, and enhanced debugging functions such as an enhanced tracer function and timer function. IE-70000-MC-PS-B AC adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter IE-789860-NS-EM1 Emulation board NP-20GS Emulation probe EV-9500GS-20 Conversion adapter Adapter required when using a PC-9800 series (except notebook type) as the host machine (C bus supported). PC card and interface cable required when using a notebook type PC as the host machine (PCMCIA socket supported). Adapter required when using IBM PC/AT and compatibles as the host machine (ISA bus supported). Adapter required when using a personal computer incorporating the PCI bus is used as the host machine. Emulation board for emulating the peripheral hardware inherent to the device. Used in combination with in-circuit emulator. Board for connecting in-circuit emulator and target system. Used in combination with EV-9500GS-20. Conversion adapter for connecting target system board for mounting 20-pin plastic SSOP and NP-20GS. Adapter for supplying power from 100 to 240 VAC outlet. Remark NP-20GS is a product of Naito Densei Machida Mfg. Co., Ltd. For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191) User's Manual U14826EJ4V0UD 203 APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS Integrated debugger This debugger supports the in-circuit emulators for the 78K/0S Series, IE-78K0S-NS and IE78K0S-NS-A. ID78K0S-NS is Windows-based software. This debugger has enhanced debugging functions supporting C language. By using its window integration function that associates the source program, disassemble display, and memory display with trace results, the trace results can be displayed corresponding to the source program. It is used with a device file (DF789861) (sold separately). Part number: SxxxxID78K0S-NS SM78K0S System simulator This is a system simulator for the 78K/0S series. SM78K0S is Windows-based software. This simulator can execute C-source-level or assembler-level debugging while simulating the operations of the target system on the host machine. By using SM78K0S, the logic and performance of the application can be verified independently of hardware development. Therefore, the development efficiency can be enhanced and the software quality can be improved. This simulator is used with a device file (DF789861) (sold separately). Part number: SxxxxSM78K0S DF789861 Device file Note This is a file that has device-specific information. It is used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (all sold separately). Part number: SxxxxDF789861 Note DF789861 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S. Remark xxxx in the part number differs depending on the operating system to be used and the supply medium. SxxxxID78K0S-NS SxxxxSM78K0S xxxx AB13 BB13 AB17 BB17 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows English Windows Japanese Windows English Windows CD-ROM Supply Medium 3.5" 2HD FD 204 User's Manual U14826EJ4V0UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion connector and conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Figure B-1. Connection Condition of Target In-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Emulation board IE-789860-NS-EM1 185 mm Target system CN1 Emulation probe NP-20GS Conversion socket: EV-9500GS-20 Emulation board IE-789860-NS-EM1 45 mm 10 mm 43 mm Emulation probe NP-20GS Target system Conversion connector: EV-9500GS-20 30 mm 1 pin 15 mm 100 mm Remark The NP-20GS is a product made by Naito Densei Machida Mfg. Co., Ltd. User's Manual U14826EJ4V0UD 205 APPENDIX C REGISTER INDEX C.1 Register Name Index (in Alphabetical Order) [B] Bit sequential buffer 10 data registers L, H (BSFRL10, BSFRH10).............................................................................132 Bit sequential buffer output control register 10 (BSFC10) ...........................................................................................133 [C] Carrier generator output control register 40 (TCA40) ....................................................................................................91 [E] EEPROM write control register 10 (EEWC10) ..............................................................................................................58 8-bit compare register 30 (CR30) ..................................................................................................................................87 8-bit compare register 40 (CR40) ..................................................................................................................................87 8-bit compare register H40 (CRH40).............................................................................................................................87 8-bit timer counter 30 (TM30)........................................................................................................................................87 8-bit timer counter 40 (TM40)........................................................................................................................................87 8-bit timer mode control register 30 (TMC30)................................................................................................................89 8-bit timer mode control register 40 (TMC40)................................................................................................................90 [I] Interrupt mask flag register 0 (MK0) ............................................................................................................................140 Interrupt request flag register 0 (IF0)...........................................................................................................................139 [L] Low-voltage detection level selection register 1 (LVIS1) .............................................................................................127 Low-voltage detection register 1 (LVIF1).....................................................................................................................127 [O] Oscillation stabilization time selection register (OSTS) ...............................................................................................149 [P] Port 0 (P0).....................................................................................................................................................................64 Port 2 (P2).....................................................................................................................................................................65 Port 4 (P4).....................................................................................................................................................................66 Port mode register 0 (PM0) ...........................................................................................................................................67 Port mode register 2 (PM2) .............................................................................................................................67, 92, 133 Power-on-clear register 1 (POCF1).............................................................................................................................126 Processor clock control register (PCC) ...................................................................................................................70, 77 [T] Timer clock selection register 2 (TCL2).......................................................................................................................120 [W] Watchdog timer mode register (WDTM)......................................................................................................................121 206 User's Manual U14826EJ4V0UD APPENDIX C REGISTER INDEX C.2 Register Symbol Index (in Alphabetical Order) [B] BSFC10: BSFRL10, BSFRH10: Bit sequential buffer 10 data registers L, H .............................................................................................132 Bit sequential buffer output control register 10 ........................................................................................133 [C] CR30: CR40: CRH40: 8-bit compare register 30 ..........................................................................................................................87 8-bit compare register 40 ..........................................................................................................................87 8-bit compare register H40........................................................................................................................87 [E] EEWC10: EEPROM write control register 10.............................................................................................................58 [I] IF0: Interrupt request flag register 0 ...............................................................................................................139 [L] LVIF1: LVIS1: Low-voltage detection register 1..............................................................................................................127 Low-voltage detection level selection register 1 ......................................................................................127 [M] MK0: Interrupt mask flag register 0...................................................................................................................140 [O] OSTS: Oscillation stabilization time selection register ........................................................................................149 [P] P0: P2: P4: PCC: PM0: PM2: POCF1: Port 0.........................................................................................................................................................64 Port 2.........................................................................................................................................................65 Port 4.........................................................................................................................................................66 Processor clock control register ..........................................................................................................70, 77 Port mode register 0..................................................................................................................................67 Port mode register 2.................................................................................................................... 67, 92, 133 Power-on-clear register 1 ........................................................................................................................126 [T] TCA40: TCL2: TM30: TM40: TMC30: TMC40: Carrier generator output control register 40 ..............................................................................................91 Timer clock selection register 2 ...............................................................................................................120 8-bit timer counter 30 ................................................................................................................................87 8-bit timer counter 40 ................................................................................................................................87 8-bit timer mode control register 30...........................................................................................................89 8-bit timer mode control register 40...........................................................................................................90 [W] WDTM: Watchdog timer mode register ................................................................................................................121 User's Manual U14826EJ4V0UD 207 APPENDIX D REVISION HISTORY Revisions up to this edition are shown below. The "Applied to" column indicates the chapter in each edition to which the revision was applied. (1/2) Edition 2nd Description Change of PD789860, 789861 Subseries status from under development to development completed Modification of INTTMn0 timing in Figure 9-12 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M)) Modification of Figure 11-2 Block Diagram of Low-Voltage Detection Circuit Modification of internal reset signal timing in Figure 11-8 Timing of Internal Reset Signal Generation in POC Switching Circuit Revision of description in 11.4.2 Operation of low-voltage detection (LVI) circuit Modification of Caution in 14.4.1 Non-maskable interrupt request acknowledgement operation Modification of Figure 14-7 Acknowledgement of Non-Maskable Interrupt Request Addition of Note 1 for pins used in Table 17-2 Communication Mode CHAPTER 17 PD78E9860, 78E9861 Addition of IE-78K0S-NS-A, IE-70000-PCI-IF-A, and EV-9500GS-20 in A.3.1 Hardware 3rd Change of PD78E9860 and 78E9861 to PD78E9860A and 78E9861A Change of supply voltage of PD789860 and 78E9860A Modification of Related Documents to latest version Update of series lineup chart to latest version INTRODUCTION CHAPTER 1 GENERAL (PD789860 SUBSERIES) CHAPTER 2 GENERAL (PD789861 SUBSERIES) Change of processing of VPP pin in 3.2.9 VPP (PD78E9860A and 78E9861A only) and Table 3-1 Types of Pin I/O Circuits and Recommended Connection of Unused Pins Addition of Caution to 13.1 Key Return Circuit Function Modification of Figure 13-1 Block Diagram of Key Return Circuit Modification of figure of releasing stop mode in Figure 15-1 Format of Oscillation Stabilization Time Selection Register Total revision of descriptions on EEPROM (program memory) CHAPTER 13 KEY RETURN CIRCUIT CHAPTER 15 STANDBY FUNCTION CHAPTER 17 CHAPTER 3 PIN FUNCTIONS APPENDIX A DEVELOPMENT TOOLS Throughout CHAPTER 14 INTERRUPT FUNCTIONS CHAPTER 11 POWER-ONCLEAR CIRCUIT CHAPTER 9 8-BIT TIMER Applied to Throughout PD78E9860A, 78E9861A Total revision of descriptions of development tools Deletion of embedded software APPENDIX A DEVELOPMENT TOOLS 208 User's Manual U14826EJ4V0UD APPENDIX D REVISION HISTORY (2/2) Edition 4th Description * Update of 1.5 78K/0S Series Lineup and 2.5 78K/0S Series Lineup to latest version Applied to CHAPTER 1 GENERAL (PD789860 SUBSERIES) CHAPTER 2 GENERAL (PD789861 SUBSERIES) * Modification of description of 3.2.9 VPP (PD78E9860A, 78E9861A only) * Addition of description of timer input of P21 to 9.3 (4) Port mode register 2 (PM2) * Modification of Figure 11-1 Block Diagram of Power-on-Clear Circuit and Figure 11-2 Block Diagram of Low-Voltage Detection Circuit * Addition of Caution to 11.4.2 Operation of low-voltage detection (LVI) circuit * Modification of Figure 11-9 LVI Circuit Operation Timing * Addition of 12.3 (2) Port mode register 2 (PM2) * Addition of description of power supply voltage and OSTS oscillation stabilization time to Table 17-1 Differences Between PD78E9860A, 78E9861A and Mask ROM Versions Addition of chapter CHAPTER 20 ELECTRICAL SPECIFICATIONS CHAPTER 21 EXAMPLE OF RC OSCILLATION FREQUENCY CHARACTERISTICS (REFERENCE VALUES) CHAPTER 22 PACKAGE DRAWING CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS APPENDIX B NOTES ON TARGET SYSTEM DESIGN CHAPTER 12 BIT SEQUENTIAL BUFFER CHAPTER 17 CHAPTER 3 PIN FUNCTIONS CHAPTER 9 8-BIT TIMERS 30 AND 40 CHAPTER 11 POWER-ONCLEAR CIRCUITS PD78E9860A, 78E9861A User's Manual U14826EJ4V0UD 209 |
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