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| User's Manual PD789026 Subseries 8-Bit Single-Chip Microcontrollers PD789022 PD789024 PD789025 PD789026 PD78F9026A Document No. U11919EJ3V0UMJ1 (3rd edition) Date Published October 2000 N CP(K) (c) Printed in Japan 1998 1999 1996, [MEMO] 2 User's Manual U11919EJ3V0UM00 SUMMARY OF CONTENTS CHAPTER 1 CHAPTER 2 CHAPTER 3 CHAPTER 4 CHAPTER 5 CHAPTER 6 CHAPTER 7 CHAPTER 8 CHAPTER 9 GENERAL ....................................................................................................................................23 PIN FUNCTIONS..........................................................................................................................33 CPU ARCHITECTURE.................................................................................................................41 PORT FUNCTIONS......................................................................................................................69 CLOCK GENERATION CIRCUIT ................................................................................................85 16-BIT TIMER ..............................................................................................................................93 8-BIT TIMER/EVENT COUNTER...............................................................................................105 WATCHDOG TIMER ..................................................................................................................115 SERIAL INTERFACE 00............................................................................................................121 CHAPTER 10 INTERRUPT FUNCTIONS .........................................................................................................149 CHAPTER 11 STANDBY FUNCTION...............................................................................................................167 CHAPTER 12 RESET FUNCTION ....................................................................................................................175 CHAPTER 13 PD78F9026A............................................................................................................................179 CHAPTER 14 INSTRUCTION SET ...................................................................................................................185 APPENDIX A DEVELOPMENT TOOLS ...........................................................................................................195 APPENDIX B EMBEDDED SOFTWARE..........................................................................................................205 APPENDIX C REGISTER INDEX .....................................................................................................................207 APPENDIX D REVISION HISTORY .................................................................................................................211 User's Manual U11919EJ3V0UM00 3 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. MS-DOS, Windows, and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. OSF/Motif is a trademark of Open Software Foundation, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. 4 User's Manual U11919EJ3V0UM00 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: PD78F9026A The customer must judge the need for license: PD789022, PD789024, PD789025, PD789026 * The information in this document is current as of October, 1999. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 User's Manual U11919EJ3V0UM00 5 Major Revision in This Edition Page Throughout Description Completion of development of PD789022 and PD789024 Change of part number from PD78F9026 to PD78F9026A Deletion of following products: PD789022CU-xxx, 789024CU-xxx Addition of GB-8ES type package to all models p.39 p.99 p.106 p.109 p.111 p.112 pp.180 to 183 p.183 p.205 Change of circuit type and recommended connection of unused pins in Table 2-1 Addition of cautions on rewriting CR20 to Section 6.4.1 Addition of cautions on rewriting CR00 to Section 7.2 (1) Addition of description of operation to Section 7.4.1 Addition of description of operation to Section 7.4.2 Addition of description of operation to Section 7.4.3 Change of flash writer from Flashpro II to Flashpro III Addition of setting example to Section 13.1.4 Addition of part number of MX78K0S to Appendix B The mark shows the major revised points. 6 User's Manual U11919EJ3V0UM00 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7 User's Manual U11919EJ3V0UM00 7 [MEMO] 8 User's Manual U11919EJ3V0UM00 INTRODUCTION Readers This manual is intended for user engineers who understand the functions of the PD789026 Subseries to design and develop its application systems and programs. The target subseries is the PD789026 Subseries, which consists of the PD789022, PD789024, PD789025, PD789026, and PD78F9026A. Purpose This manual is designed to deepen your understanding of the following functions described in the following organization. Organization Two manuals are available for the PD789026 Subseries: Instruction Manual (common to the 78K/0S Series). this manual and PD789026 Subseries User's Manual * Pin functions * Internal block functions * Interrupt * Other internal peripheral functions How to Read This Manual 78K/0S Series User's Manual Instruction * CPU function * Instruction set * Instruction description It is assumed that the readers of this manual have general knowledge on electric engineering, logic circuits, and microcontrollers. To understand the overall functions of the PD789026 Subseries Read this manual in the order of the TABLE OF CONTENTS. How to read register formats The name of a bit whose number is encircled is reserved for the assembler and is defined for the C compiler by the header file sfrbit.h. To learn the detailed functions of a register whose register name is known See APPENDEX C. To learn the details of the instruction functions of the 78K/0S Series Refer to 78K/0S Series User's Manual Instruction (U11047E) separately available. Legend Data significance Active low Note Caution Remark : : : : : Left: higher digit, right: lower digit xxx (top bar over pin or signal name) Description of text marked Note Important information Supplement Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Numerical representation : User's Manual U11919EJ3V0UM00 9 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Related Documents Document Name Document No. English Japanese U11715J U14356J U11919J U11047J PD789022, 789024, 789025, 789026 Data Sheet PD78F9026A Data Sheet PD789026 Subseries User's Manual 78K/0S Series User's Manual Instruction U11715E U14356E This manual U11047E Documents for Development Tool (User's Manual) Document Name Document No. English RA78K0S Assembler Package Operation Assembly Language Structured Assembly Language CC78K0S C Compiler Operation Language SM78K0S System Simulator Windows Based SM78K Series System Simulator TM Japanese U11622J U11599J U11623J U11816J U11817J U11489J U10092J U11622E U11599E U11623E U11816E U11817E U11489E U10092E Reference External Part User Open Interface Specifications Reference ID78K0S Integrated Debugger Windows Based IE-78K0S-NS In-Circuit Emulator IE-789026-NS-EM1 Emulation Board U12901E U13549E To be created U12901J U13549J To be created Document for Embedded Software (User's Manual) Document Name Document No. English 78K/0S Series OS MX78K0S Fundamental U12938E Japanese U12938J Caution The related documents listed above are subject to change without notice. Be sure to use the latest documents for designing, etc. 10 User's Manual U11919EJ3V0UM00 Other Related Documents Document Name Document No. English SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Device Quality Control/Reliability Handbook Guide for products Related to Microcomputer: Other Companies X13769X C10535E C11531E C10983E C11892E - - C10535J C11531J C10983J C11892J C12769J U11416J Japanese Caution The related documents listed above are subject to change without notice. Be sure to use the latest documents for designing, etc. User's Manual U11919EJ3V0UM00 11 [MEMO] 12 User's Manual U11919EJ3V0UM00 TABLE OF CONTENTS CHAPTER 1 GENERAL.............................................................................................................................23 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features ......................................................................................................................................23 Applications................................................................................................................................23 Ordering Information .................................................................................................................24 Pin Configuration (Top View)....................................................................................................25 Development of 78K/0S Series..................................................................................................28 Block Diagram ............................................................................................................................30 Outline of Functions ..................................................................................................................31 CHAPTER 2 PIN FUNCTIONS ..................................................................................................................33 2.1 2.2 List of Pin Functions..................................................................................................................33 Description of Pin Functions ....................................................................................................35 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 P00 to P07 (Port 0)......................................................................................................................35 P10 to P17 (Port 1)......................................................................................................................35 P20 to P22 (Port 2)......................................................................................................................35 P30 to P32 (Port 3)......................................................................................................................36 P40 to P47 (Port 4)......................................................................................................................36 P50 to P53 (Port 5)......................................................................................................................37 RESET.........................................................................................................................................37 X1, X2..........................................................................................................................................37 NC ...............................................................................................................................................37 VDD...............................................................................................................................................37 VSS ...............................................................................................................................................37 VPP (PD78F9026A only) ............................................................................................................37 IC (mask ROM model only) .........................................................................................................38 2.3 Pin Input/Output Circuits and Connection of Unused Pins ...................................................39 CHAPTER 3 CPU ARCHITECTURE .........................................................................................................41 3.1 Memory Space ............................................................................................................................41 3.1.1 3.1.2 3.1.3 3.1.4 Internal program memory space..................................................................................................46 Internal data memory (internal high-speed RAM) space .............................................................47 Special function register (SFR) area ...........................................................................................47 Data memory addressing ............................................................................................................48 Control registers ..........................................................................................................................53 General-purpose registers...........................................................................................................56 Special function register (SFR)....................................................................................................57 Relative addressing .....................................................................................................................60 3.2 Processor Registers ..................................................................................................................53 3.2.1 3.2.2 3.2.3 3.3 Instruction Address Addressing ..............................................................................................60 3.3.1 User's Manual U11919EJ3V0UM00 13 3.3.2 3.3.3 3.3.4 Immediate addressing .................................................................................................................61 Table indirect addressing ............................................................................................................62 Register addressing ....................................................................................................................62 Direct addressing ........................................................................................................................63 Short direct addressing ...............................................................................................................64 Special function register (SFR) addressing.................................................................................65 Register addressing ....................................................................................................................66 Register indirect addressing........................................................................................................67 Based addressing........................................................................................................................68 Stack addressing.........................................................................................................................68 3.4 Operand Address Addressing .................................................................................................. 63 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 CHAPTER 4 PORT FUNCTIONS .............................................................................................................. 69 4.1 4.2 Functions of Ports ..................................................................................................................... 69 Port Configuration ..................................................................................................................... 71 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 Port 0...........................................................................................................................................71 Port 1...........................................................................................................................................72 Port 2...........................................................................................................................................73 Port 3...........................................................................................................................................76 Port 4...........................................................................................................................................77 Port 5...........................................................................................................................................78 4.3 4.4 Port Function Control Registers .............................................................................................. 81 Operation of Port Functions ..................................................................................................... 83 4.4.1 4.4.2 4.4.3 Writing to I/O port ........................................................................................................................83 Reading from I/O port ..................................................................................................................83 Arithmetic operation of I/O port....................................................................................................83 CHAPTER 5 CLOCK GENERATION CIRCUIT......................................................................................... 85 5.1 5.2 5.3 5.4 Function of Clock Generation Circuit ...................................................................................... 85 Configuration of Clock Generation Circuit.............................................................................. 85 Register Controlling Clock Generation Circuit ....................................................................... 86 System Clock Oscillation Circuits............................................................................................ 87 5.4.1 5.4.2 System clock oscillation circuit ....................................................................................................87 Divider circuit...............................................................................................................................89 5.5 5.6 Operation of Clock Generation Circuit .................................................................................... 90 Changing Setting of System Clock and CPU Clock ............................................................... 91 5.6.1 5.6.2 Time required for switching between system clock and CPU clock ............................................91 Switching CPU clock ...................................................................................................................91 CHAPTER 6 16-BIT TIMER ....................................................................................................................... 93 6.1 6.2 6.3 6.4 16-Bit Timer Functions .............................................................................................................. 93 16-Bit Timer Configuration........................................................................................................ 94 Registers Controlling 16-Bit Timer........................................................................................... 96 16-Bit Timer Operation .............................................................................................................. 99 6.4.1 Operation as timer interrupt.........................................................................................................99 14 User's Manual U11919EJ3V0UM00 6.4.2 6.4.3 6.4.4 Operation as timer output ..........................................................................................................101 Capture operation......................................................................................................................102 16-bit timer counter 20 readout .................................................................................................103 CHAPTER 7 8-BIT TIMER/EVENT COUNTER .......................................................................................105 7.1 7.2 7.3 7.4 8-Bit Timer/Event Counter Functions.....................................................................................105 8-Bit Timer/Event Counter Configuration ..............................................................................106 8-Bit Timer/Event Counter Control Registers........................................................................107 8-Bit Timer/Event Counter Operation.....................................................................................109 7.4.1 7.4.2 7.4.3 Operation as interval timer ........................................................................................................109 Operation as external event counter .........................................................................................111 Operation as square wave output..............................................................................................112 7.5 Notes on Using 8-Bit Timer/Event Counters .........................................................................114 CHAPTER 8 WATCHDOG TIMER...........................................................................................................115 8.1 8.2 8.3 8.4 Watchdog Timer Functions.....................................................................................................115 Watchdog Timer Configuration .............................................................................................. 116 Watchdog Timer Control Registers........................................................................................117 Operation of Watchdog Timer.................................................................................................119 8.4.1 8.4.2 Operation as watchdog timer.....................................................................................................119 Operation as interval timer ........................................................................................................120 CHAPTER 9 SERIAL INTERFACE 00.....................................................................................................121 9.1 9.2 9.3 9.4 Serial Interface 00 Functions ..................................................................................................121 Serial Interface 00 Configuration ............................................................................................121 Serial Interface 00 Control Register .......................................................................................125 Serial Interface 00 Operation...................................................................................................132 9.4.1 9.4.2 9.4.3 Operation stop mode .................................................................................................................132 Asynchronous serial interface (UART) mode ............................................................................134 3-wire serial I/O mode ...............................................................................................................145 CHAPTER 10 INTERRUPT FUNCTIONS................................................................................................ 149 10.1 10.2 10.3 10.4 Interrupt Function Types.........................................................................................................149 Interrupt Sources and Configuration .....................................................................................149 Interrupt Function Control Registers .....................................................................................152 Interrupt Processing Operation ..............................................................................................158 10.4.1 10.4.2 10.4.3 10.4.4 Non-maskable interrupt request acceptance operation.............................................................158 Maskable interrupt request acceptance operation.....................................................................161 Nesting processing ....................................................................................................................163 Interrupt request reserve ...........................................................................................................165 CHAPTER 11 STANDBY FUNCTION .....................................................................................................167 11.1 Standby Function and Configuration.....................................................................................167 11.1.1 Standby function........................................................................................................................167 User's Manual U11919EJ3V0UM00 15 11.1.2 11.2.1 11.2.2 Standby function control register...............................................................................................168 HALT mode ...............................................................................................................................169 STOP mode...............................................................................................................................172 11.2 Operation of Standby Function .............................................................................................. 169 CHAPTER 12 RESET FUNCTION........................................................................................................... 175 CHAPTER 13 PD78F9026A .................................................................................................................. 179 13.1 Flash Memory Programming................................................................................................... 180 13.1.1 13.1.2 13.1.3 13.1.4 Selecting communication mode.................................................................................................180 Flash memory programming function ........................................................................................181 Connection Example of Flashpro III ..........................................................................................181 Setting example when using Flashpro III (PG-FP3) ..................................................................183 CHAPTER 14 INSTRUCTION SET.......................................................................................................... 185 14.1 Operation .................................................................................................................................. 185 14.1.1 14.1.2 14.1.3 Operand identifiers and writing methods ...................................................................................185 Description of "Operation" column.............................................................................................186 Description of "Flag" column .....................................................................................................186 14.2 Operation List........................................................................................................................... 187 14.3 Instructions Listed by Addressing Type ............................................................................... 192 APPENDIX A DEVELOPMENT TOOLS.................................................................................................. 195 A.1 A.2 A.3 Language Processing Software.............................................................................................. 197 Flash Memory Writing Tools ................................................................................................... 198 Debugging Tools...................................................................................................................... 199 A.3.1 A.3.2 Hardware ...................................................................................................................................199 Software ....................................................................................................................................200 A.4 A.5 Conversion Socket (EV-9200G-44) Drawing and Recommended Footprint....................... 201 Conversion Adapter (TGB-044SAP) Drawing........................................................................ 203 APPENDIX B EMBEDDED SOFTWARE ................................................................................................ 205 APPENDIX C REGISTER INDEX ............................................................................................................ 207 C.1 C.2 Register Name Index................................................................................................................ 207 Register Symbol Index ............................................................................................................ 209 APPENDIX D REVISION HISTORY ........................................................................................................ 211 16 User's Manual U11919EJ3V0UM00 LIST OF FIGURES (1/3) Figure No. 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 5-1 5-2 5-3 5-4 5-5 Title Page List of Pin Input/Output Circuits................................................................................................................. 40 Memory Map (PD789022) ....................................................................................................................... 41 Memory Map (PD789024) ....................................................................................................................... 42 Memory Map (PD789025) ....................................................................................................................... 43 Memory Map (PD789026) ....................................................................................................................... 44 Memory Map (PD78F9026A) .................................................................................................................. 45 Data Memory Addressing (PD789022) ................................................................................................... 48 Data Memory Addressing (PD789024) ................................................................................................... 49 Data Memory Addressing (PD789025) ................................................................................................... 50 Data Memory Addressing (PD789026) ................................................................................................... 51 Data Memory Addressing (PD78F9026A)............................................................................................... 52 Program Counter Configuration ................................................................................................................ 53 Program Status Word Configuration ......................................................................................................... 53 Stack Pointer Configuration ...................................................................................................................... 55 Data to be Saved to Stack Memory .......................................................................................................... 55 Data to be Restored from Stack Memory .................................................................................................. 55 General-Purpose Register Configuration .................................................................................................. 56 Port Types................................................................................................................................................. 69 Block Diagram of P00 to P07 .................................................................................................................... 71 Block Diagram of P10 to P17 .................................................................................................................... 72 Block Diagram of P20 ............................................................................................................................... 73 Block Diagram of P21 ............................................................................................................................... 74 Block Diagram of P22 ............................................................................................................................... 75 Block Diagram of P30 to P32 .................................................................................................................... 76 Block Diagram of P40 to P47 .................................................................................................................... 77 Block Diagram of P50 ............................................................................................................................... 78 Block Diagram of P51 ............................................................................................................................... 79 Block Diagram of P52 and P53 ................................................................................................................. 80 Port Mode Register Format ....................................................................................................................... 82 Pull-Up Resistor Option Register Format .................................................................................................. 82 Block Diagram of Clock Generation Circuit............................................................................................... 85 Processor Clock Control Register Format................................................................................................. 86 External Circuit of System Clock Oscillation Circuit .................................................................................. 87 Incorrect Examples of Resonator Connection........................................................................................... 88 Switching CPU Clock ................................................................................................................................ 91 User's Manual U11919EJ3V0UM00 17 LIST OF FIGURES (2/3) Figure No. 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 8-1 8-2 8-3 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 10-1 10-2 10-3 Title Page Block Diagram of 16-Bit Timer 20 ..............................................................................................................94 16-Bit Timer Mode Control Register 20 Format .........................................................................................97 Port Mode Register 5 Format.....................................................................................................................98 Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation ......................................99 Timer Interrupt Operation Timing .............................................................................................................100 Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation .......................................101 Timer Output Timing ................................................................................................................................101 Setting Contents of 16-Bit Timer Mode Control Register 20 during Capture Operation...........................102 Capture Operation Timing (Both Edges of CPT2 Pin are Specified) .......................................................102 16-Bit Timer Counter 20 Readout Timing ................................................................................................103 Block Diagram of 8-Bit Timer/Event Counter 00 ......................................................................................106 8-Bit Timer Mode Control Register 00 Format .........................................................................................107 Port Mode Register 5 Format...................................................................................................................108 Interval Timer Operation Timing...............................................................................................................110 External Event Counter Operation Timing (with Rising Edge Specified) .................................................111 Square Wave Output Timing....................................................................................................................113 8-Bit Timer Counter 00 Start Timing ........................................................................................................114 External Event Counter Operation Timing ...............................................................................................114 Block Diagram of Watchdog Timer ..........................................................................................................116 Timer Clock Select Register 2 Format .....................................................................................................117 Watchdog Timer Mode Register Format ..................................................................................................118 Block Diagram of Serial Interface 00........................................................................................................122 Block Diagram of Baud Rate Generator...................................................................................................123 Serial Operation Mode Register 00 Format .............................................................................................125 Asynchronous Serial Interface Mode Register 00 Format .......................................................................126 Asynchronous Serial Interface Status Register 00 Format ......................................................................128 Baud Rate Generator Control Register 00 Format...................................................................................129 Asynchronous Serial Interface Transmit/Receive Data Format ...............................................................139 Asynchronous Serial Interface Transmission Completion Interrupt Timing .............................................141 Asynchronous Serial Interface Reception Completion Interrupt Timing...................................................142 Receive Error Timing ...............................................................................................................................143 3-Wire Serial I/O Mode Timing.................................................................................................................148 Basic Configuration of Interrupt Function.................................................................................................151 Interrupt Request Flag Register Format...................................................................................................153 Interrupt Mask Flag Register Format .......................................................................................................154 18 User's Manual U11919EJ3V0UM00 LIST OF FIGURES (3/3) Figure No. 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 11-1 11-2 11-3 11-4 11-5 12-1 12-2 12-3 12-4 13-1 13-2 13-3 13-4 A-1 A-2 A-3 A-4 Title Page External Interrupt Mode Register 0 Format ............................................................................................. 155 Program Status Word Configuration ....................................................................................................... 156 Key Return Mode Register 00 Format..................................................................................................... 157 Falling Edge Detection Circuit................................................................................................................. 157 Flowchart from Non-Maskable Interrupt Request Generation to Acceptance ......................................... 159 Non-Maskable Interrupt Request Acceptance Timing............................................................................. 159 Accepting Non-Maskable Interrupt Request ........................................................................................... 160 Interrupt Request Acceptance Program Algorithm.................................................................................. 162 Interrupt Request Acceptance Timing (Example of MOV A,r)................................................................. 163 Interrupt Request Acceptance Timing (When Interrupt Request Flag Generates at the Last Clock during Instruction Execution)..................... 163 Example of Nesting ................................................................................................................................. 164 Oscillation Settling Time Select Register Format.................................................................................... 168 Releasing HALT Mode by Interrupt......................................................................................................... 170 Releasing HALT Mode by RESET Input ................................................................................................. 171 Releasing STOP Mode by Interrupt ........................................................................................................ 173 Releasing STOP Mode by RESET Input................................................................................................. 174 Block Diagram of Reset Function............................................................................................................ 175 Reset Timing by RESET Input ................................................................................................................ 176 Reset Timing by Overflow in Watchdog Timer ........................................................................................ 176 Reset Timing by RESET Input in STOP Mode........................................................................................ 176 Communication Mode Selection Format ................................................................................................. 180 Connection Example of Flashpro III in 3-Wire Serial I/O Mode............................................................... 181 Connection Example of Flashpro III in UART Mode................................................................................ 182 Connection Example of Flashpro III in Pseudo 3-Wire Mode (When using P0)...................................... 182 Development Tools ................................................................................................................................. 196 EV-9200G-44 Package Drawing (Reference) ......................................................................................... 201 EV-9200G-44 Recommended Footprint (Reference).............................................................................. 202 TGB-044SAP Package Drawing (Reference) ......................................................................................... 203 User's Manual U11919EJ3V0UM00 19 LIST OF TABLES (1/2) Table No. 2-1 3-1 3-2 3-3 3-4 4-1 4-2 4-3 5-1 5-2 6-1 6-2 6-3 7-1 7-2 7-3 7-4 7-5 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 9-4 9-5 9-6 9-7 10-1 Title Page Type of Input/Output Circuit of Each Pin and Handling of Unused Pins ....................................................39 Internal ROM Capacity...............................................................................................................................46 Vector Table...............................................................................................................................................46 Internal High-Speed RAM Capacity ...........................................................................................................47 Special Function Registers ........................................................................................................................58 Port Functions ............................................................................................................................................70 Port Configuration ......................................................................................................................................71 Port Mode Register and Output Latch Settings when Using Alternate Functions......................................81 Configuration of Clock Generation Circuit..................................................................................................85 Maximum Time Required for Switching CPU Clock ...................................................................................91 Configuration of 16-Bit Timer 20 ................................................................................................................94 Interval Time of 16-Bit Timer 20.................................................................................................................99 Setting Contents of Capture Edge ...........................................................................................................102 Interval Time of 8-Bit Timer/Event Counter 00.........................................................................................105 Square Wave Output Range of 8-Bit Timer/Event Counter 00 ................................................................105 Configuration of 8-Bit Timer/Event Counter 00 ........................................................................................106 Interval Time of 8-Bit Timer/Event Counter 00.........................................................................................109 Square Wave Output Range of 8-Bit Timer/Event Counter 00 ................................................................112 Inadvertent Loop Detection Time of Watchdog Timer..............................................................................115 Interval Time ............................................................................................................................................115 Configuration of Watchdog Timer ............................................................................................................116 Inadvertent Loop Detection Time of Watchdog Timer..............................................................................119 Interval Time of Interval Timer .................................................................................................................120 Configuration of Serial Interface 00 .........................................................................................................121 Serial Interface 00 Operating Mode Settings ...........................................................................................127 Example of Relationship between System Clock and Baud Rate............................................................130 Relationship between ASCK Pin Input Frequency and Baud Rate (When BRGC00 is Set to 80H) ........131 Example of Relationship between System Clock and Baud Rate............................................................138 Relationship between ASCK Pin Input Frequency and Baud Rate (When BRGC00 is Set to 80H) .......138 Receive Error Causes ..............................................................................................................................143 Interrupt Source List.................................................................................................................................150 20 User's Manual U11919EJ3V0UM00 LIST OF TABLES (2/2) Table No. 10-2 10-3 11-1 11-2 11-3 11-4 12-1 13-1 13-2 13-3 13-4 14-1 Title Page Flags Corresponding to Interrupt Request Signal Name ........................................................................ 152 Time from Generation of Maskable Interrupt Request to Processing ..................................................... 161 HALT Mode Operating Status ................................................................................................................. 169 Operation after Release of HALT Mode .................................................................................................. 171 STOP Mode Operating Status................................................................................................................. 172 Operation after Release of STOP Mode ................................................................................................. 174 Hardware Status after Reset................................................................................................................... 177 Differences between PD78F9026A and Mask ROM Models ................................................................ 179 Communication Modes ........................................................................................................................... 180 Major Flash Memory Programming Functions ........................................................................................ 181 Setting Example When Using PG-FP3.................................................................................................... 183 Operand Identifiers and Writing Methods................................................................................................ 185 User's Manual U11919EJ3V0UM00 21 [MEMO] 22 User's Manual U11919EJ3V0UM00 CHAPTER 1 GENERAL 1.1 Features * ROM and RAM capacity Item Part Number Program Memory Data Memory PD789022 PD789024 PD789025 PD789026 PD78F9026A ROM 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 256 bytes 512 bytes Flash memory 16 Kbytes * Variable minimum instruction execution time - from high speed (0.4 s: with 5.0-MHz system clock) to slow (1.6 s: with 5.0-MHz system clock) * I/O port: 34 lines * Serial interface: 1 channel 3-wire serial I/O mode/UART mode selection * Timer: 3 channels * * * 16-bit timer Watchdog timer : 1 channel : 1 channel 8-bit timer/event counter : 1 channel * Vectored interrupt: 10 * Supply voltage: VDD = 1.8 to 5.5 V * Operating ambient temperature: TA = -40C to +85C 1.2 Applications Home appliances, car accessories, air conditioners, game machines, etc. User's Manual U11919EJ3V0UM00 23 CHAPTER 1 GENERAL 1.3 Ordering Information Part Number Package 44-pin plastic QFP (10 x 10 mm, resin thickness 2.7 mm) 44-pin plastic LQFP (10 x 10 mm, resin thickness 1.4 mm) 44-pin plastic QFP (10 x 10 mm, resin thickness 2.7 mm) 44-pin plastic LQFP (10 x 10 mm, resin thickness 1.4 mm) 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (10 x 10 mm, resin thickness 2.7 mm) 44-pin plastic LQFP (10 x 10 mm, resin thickness 1.4 mm) 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (10 x 10 mm, resin thickness 2.7 mm) 44-pin plastic LQFP (10 x 10 mm, resin thickness 1.4 mm) 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (10 x 10 mm, resin thickness 2.7 mm) 44-pin plastic LQFP (10 x 10 mm, resin thickness 1.4 mm) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Flash memory Flash memory Flash memory PD789022GB-xxx-3BS-MTX PD789022GB-xxx-8ES PD789024GB-xxx-3BS-MTX PD789024GB-xxx-8ES PD789025CU-xxx PD789025GB-xxx-3BS-MTX PD789025GB-xxx-8ES PD789026CU-xxx PD789026GB-xxx-3BS-MTX PD789026GB-xxx-8ES PD78F9026ACU PD78F9026AGB-3BS-MTX PD78F9026AGB-8ES Remark xxx indicates ROM code suffix. 24 User's Manual U11919EJ3V0UM00 CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) * 42-pin plastic shrink DIP (600 mil) PD789025CU-xxx PD789026CU-xxx PD78F9026ACU VDD0 RESET P53 P52 P51/TO2 P50/TI0/TO0 P32/INTP2/CPT2 P31/INTP1 P30/INTP0 P22/RxD/SI0 P21/TxD/SO0 P20/ASCK/SCK0 P07 P06 P05 P04 P03 P02 P01 P00 VDD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS0 X1 X2 IC (VPP) P40/KR0 P41/KR1 P42/KR2 P43/KR3 P44/KR4 P45/KR5 P46/KR6 P47/KR7 P10 P11 P12 P13 P14 P15 P16 P17 VSS1 Caution Remark Connect the IC pin directly to VSS0 or VSS1. An item in parentheses applies to the PD78F9026A only. User's Manual U11919EJ3V0UM00 25 CHAPTER 1 GENERAL * 44-pin plastic QFP (10 x 10 mm, resin thickness 2.7 mm) PD789022GB-xxx-3BS-MTX PD789024GB-xxx-3BS-MTX PD789025GB-xxx-3BS-MTX PD789026GB-xxx-3BS-MTX PD78F9026AGB-3BS-MTX * 44-pin plastic LQFP (10 x 10 mm, resin thickness 1.4 mm) PD789022GB-xxx-8ES PD789024GB-xxx-8ES PD789025GB-xxx-8ES PD789026GB-xxx-8ES PD78F9026AGB-8ES VDD1 VSS1 P13 P14 P15 P16 P17 P00 P01 P02 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 P12 P11 P10 P47/KR7 P46/KR6 P45/KR5 P44/KR4 P43/KR3 P42/KR2 P41/KR1 P40/KR0 1 2 3 4 5 6 7 8 9 10 11 P03 P04 P05 P06 P07 P20/ASCK/SCK0 P21/TxD/SO0 P22/RxD/SI0 P30/INTP0 P31/INTP1 P32/INTP2/CPT2 RESET P53 NC P52 P51/TO2 Caution Remark Connect the IC pin directly to VSS0 or VSS1. An item in parentheses applies to the PD78F9026A only. 26 User's Manual U11919EJ3V0UM00 P50/TI0/TO0 NC IC (VPP) VDD1 VSS0 X2 X1 CHAPTER 1 GENERAL ASCK CPT2 IC INTP0 to INTP2 KR0 to KR7 NC P00 to P07 P10 to P17 P20 to P22 P30 to P32 P40 to P47 P50 to P53 : Asynchronous Serial Clock : Capture Trigger Input : Internally Connected : Interrupt from Peripherals : Key Return : Non-connection : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 RESET RxD SCK0 SI0 SO0 TI0 TO0, TO2 TxD VDD0, VDD1 VPP VSS0, VSS1 X1, X2 : Reset : Receive Data : Serial Clock : Serial Input : Serial Output : Timer Input : Timer Output : Transmit Data : Power Supply : Programming Power Supply : Ground : Crystal User's Manual U11919EJ3V0UM00 27 CHAPTER 1 GENERAL 1.5 Development of 78K/0S Series The following shows the history of 78K/0S Series product development. Subseries names are shown inside frames. In production Under development For small-scale, generalpurpose applicationns 44-pin 42/44-pin 28-pin PD789046 PD789026 PD789014 Device developed by adding the subsystem clock to the PD789026 Device developed by enhancing the timers of the PD789014 and expanding ROM and RAM With built-in UART bus and capable of low-voltage (1.8 V) operation For small-scale, general-purpose applications and A/D function 44/48-pin 44/48-pin 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin PD789217AY PD789197AY PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A RC oscillation of the PD789197AY With built-in EEPROMTM and SMB in the PD789177 Device developed by enhancing the A/D function of the PD789167 Device developed by enhancing the timers of the PD789104A Device developed by enhancing the A/D function of the PD789146 With built-in EEPROM in the PD789104A Device developed by enhancing the A/D function of the PD789124A RC oscillation of the PD789104A Device developed by enhancing the A/D function of the PD789104A Device developed by adding the A/D function and multiplier to the PD789026 For inverter control 44-pin 78K/0S Series 88-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin PD789842 With built-in inverter control circuit and UART bus For LCD driving PD789830 PD789417A PD789407A PD789457 PD789447 PD789437 PD789427 PD789316 PD789306 For ASSP With built-in UART bus and dot LCD Device developed by enhancing the A/D function of the PD789407A Device developed by enhancing the I/O of the PD789457 Device developed by enhancing the A/D function of the PD789447 RC oscillation of the PD789427 Device developed by enhancing the A/D funciton of the PD789427 Device developed by adding the A/D function of the PD789306 RC oscillation of the PD789306 Basic subseries for LCD driving 44-pin 44-pin 20-pin 20-pin PD789800 PD789840 PD789861 PD789860 Device for a PC keyboard, with a built-in USB function Device for a keypad, with a built-in POC RC oscillation of the PD789860 Device for a keyless entry, with built-in POC and key return circuit For IC card 5-pin PD789810 With built-in EEPROM and security circuit 28 User's Manual U11919EJ3V0UM00 CHAPTER 1 GENERAL The following lists the main functional differences between subseries products. Function ROM Capacity Subseries Name General compact 8-Bit Timer 16-Bit Watch WDT 8-Bit A/D 10-Bit A/D Serial Interface I/O VDD MIN. Value 16 K 4 K to 16 K 2 K to 4 K 2 ch 3 ch - 1 ch 1 ch 1 ch - 8 ch 2 ch UART : 1 ch SMB : 1 ch 1 ch 1 ch 1 ch - 22 31 1.8 V RC oscillation, EEPROM on chip 1 ch - - 1 ch (UART: 1 ch) 34 1.8 V - Remark PD789046 PD789026 PD789014 General compact + A/D PD789217AY 16 K to 24 K PD789197AY PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A Inverter control LCD drive 2 K to 8 K 8 K to 16 K 1 ch - 8 ch - 4 ch - 4 ch - 4 ch 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch - 4 ch - 4 ch - 4 ch - - 1 ch (UART: 1 ch) 30 4.0 V 20 EEPROM on chip 1 ch (UART: 1 ch) - EEPROM on chip RC oscillation - PD789842 PD789830 PD789417A PD789407A PD789457 PD789447 PD789437 PD789427 PD789316 PD789306 - 24 K 12 K to 24 K 1 ch 3 ch 1 ch 1 ch 1 ch - - 7 ch 1 ch (UART: 1 ch) 30 43 25 2.7 V 1.8 V - 7 ch 16 K to 24 K 2 ch - 4 ch - 4 ch 8 K to 16 K - - 4 ch 2 ch (UART: 1 ch) - 4 ch - RC oscillation - 23 RC oscillation - ASSP PD789800 PD789840 PD789861 PD789860 8K 2 ch 1 ch - 1 ch - 4 ch - 2 ch (USB: 1 ch) 1 ch - 31 29 14 4.0 V 2.8 V 1.8 V - 4K - - RC oscillation - IC card PD789810 6K - - - 1 ch - - - 1 2.7 V EEPROM on chip User's Manual U11919EJ3V0UM00 29 CHAPTER 1 GENERAL 1.6 Block Diagram TI0/TO0/P50 8-bit TIMER EVENT/COUNTER 00 PORT0 P00 to P07 TO2/P51 CPT2/INTP2/P32 PORT1 16-bit TIMER 20 78K/0S CPU CORE ROM PORT2 P10 to P17 P20 to P22 WATCHDOG TIMER PORT3 P30 to P32 SCK0/ASCK/P20 SO0/TxD/P21 SI0/RxD/P22 PORT4 SERIAL INTERFACE 00 RAM PORT5 P40 to P47 P50 to P53 INTP0/P30 to INTP2/ CPT2/P32 KR0/P40 to KR7/P47 INTERRUPT CONTROL VDD0 VDD1 VSS0 VSS1 IC (VPP) SYSTEM CONTROL RESET X1 X2 Remarks 1. The internal ROM and internal high-speed RAM capacities differ depending on the product. 2. An item in parentheses applies to the PD78F9026A only. 30 User's Manual U11919EJ3V0UM00 CHAPTER 1 GENERAL 1.7 Outline of Functions Part Number Item Internal memory ROM Mask ROM 4 Kbytes High-speed RAM Minimum instruction execution time Instruction set 256 bytes 8 Kbytes 12 Kbytes 512 bytes 16 Kbytes Flash Memory 16 Kbytes PD789022 PD789024 PD789025 PD789026 PD78F9026A 0.4/1.6 s (when operated at 5.0 MHz with system clock) * 16-bit operations * Bit manipulations (set, reset, test), etc. Total : 34 * CMOS input/output : 34 * 3-wire serial I/O mode/UART mode selectable: 1 channel * 16-bit timer : 1 channel * 8-bit timer/event counter : 1 channel * Watchdog timer : 1 channel 2 I/O port Serial interface Timer Timer output Vectored interrupt source Power supply voltage Operating ambient temperature Package Maskable Non-maskable Internal: 5, External: 4 Internal: 1 VDD = 1.8 to 5.5 V TA = -40C to +85C * 44-pin plastic QFP (10 x 10 mm, resin thickness 2.7 mm) * 44-pin plastic LQFP (10 x 10 mm, resin thickness 1.4 mm) * 42-pin plastic shrink DIP (600 mil) * 44-pin plastic QFP (10 x 10 mm, resin thickness 2.7 mm) * 44-pin plastic LQFP (10 x 10 mm, resin thickness 1.4 mm) The outline of the timer is as follows. 16-Bit Timer 20 - - 1 output 1 input 1 8-Bit Timer/Event Counter 00 1 channel 1 channel 1 output - 1 Watchdog Timer Operating mode Function Interval timer External event counter Timer output Capture Interrupt source 1 channel - - - 1 Note Note Watchdog timer has a watchdog timer and interval timer functions. Select one of them. User's Manual U11919EJ3V0UM00 31 [MEMO] 32 User's Manual U11919EJ3V0UM00 CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions (1) Port pins Input/Output Input/output Function Port 0 8-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. Port 1 8-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. Port 2 3-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. Port 3 3-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. Port 4 8-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. Port 5 4-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. After Reset Alternate Function Input - Pin Name P00 to P07 P10 to P17 Input/output Input - P20 P21 P22 Input/output Input SCK0/ASCK SO0/TxD SI0/RxD P30 P31 P32 Input/output Input INTP0 INTP1 INTP2/CPT2 P40 to P47 Input/output Input KR0 to KR7 P50 P51 P52, P53 Input/output Input TI0/TO0 TO2 - User's Manual U11919EJ3V0UM00 33 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Input/Output Input Function External interrupt request input for which the active edge (rising edge, falling edge, or both) can be specified After Reset Alternate Function Input P30 P31 P32/CPT2 Input Input Output Input/output Input Input Output Output Input Input Output Input - Input - - - - - - - System reset input Not connected internally. Connect this pin directly to the VSS pin (it can also be left open). Positive power supply for ports Positive power supply (except for ports) Ground potential for ports Ground potential (except for ports) Internally connected. Connect this pin directly to the VSS0 or VSS1 pin. Flash memory programming mode setting. Apply high voltage during program write/verify. Connect this pin directly to the VSS pin in normal operating mode. Key return signal detection 3-wire serial interface serial data input 3-wire serial interface serial data output 3-wire serial interface serial clock input/output Asynchronous serial interface serial clock input Asynchronous serial interface serial data input Asynchronous serial interface serial data output 16-bit timer (TM20) output 16-bit timer capture edge input External count clock input to 8-bit timer (TM00) 8-bit timer (TM00) output System clock oscillation crystal connection Input Input Input Input Input Input Input Input Input Input Input - - Input - - - - - - - P40 to P47 P22/RxD P21/TxD P20/ASCK P20/SCK0 P22/SI0 P21/SO0 P51 P32/INTP2 P50/TO0 P50/TI0 - - - - - - - - - - Pin Name INTP0 INTP1 INTP2 KR0 to KR7 SI0 SO0 SCK0 ASCK RxD TxD TO2 CPT2 TI0 TO0 X1 X2 RESET NC VDD0 VDD1 VSS0 VSS1 IC VPP 34 User's Manual U11919EJ3V0UM00 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port and can be set in the input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used in the pull-up resistor option register (PUO). This port can drive LEDs directly. 2.2.2 P10 to P17 (Port 1) These pins constitute an 8-bit I/O port. Can be set in the input or output port mode in 1-bit units by using port mode register 1 (PM1). When these pins are used as an input port, an on-chip pull-up resistor can be used in the pull-up resistor option register (PUO). This port can drive LEDs directly. 2.2.3 P20 to P22 (Port 2) These pins constitute a 3-bit I/O port. In addition, these pins provide the function to input/output the data and clock of the serial interface. This port can drive LEDs directly. Port 2 can be specified in the following operation modes in bit-wise. (1) Port mode In this mode, port 2 functions as a 3-bit I/O port. Port 2 can be set in the input or output mode in 1-bit units by using the port mode register 2 (PM2). When the port is used as an input port, an on-chip pull-up resistor can be used in the pull-up resistor option register (PUO). (2) Control mode In this mode, port 2 functions as the data input/output and the clock input/output of the serial interface. (a) SI0, SO0 These are the serial data I/O pins of the serial interface. (b) SCK0 This is the serial clock I/O pin of the serial interface. (c) RxD, TxD These are the serial data I/O pins of asynchronous serial interface. (d) ASCK This is the serial clock input pin of asynchronous serial interface. Caution When using port 2 as serial interface pins, the input/output mode and output latch must be set according to the functions to be used. For details of the setting, see Table 9-2. User's Manual U11919EJ3V0UM00 35 CHAPTER 2 PIN FUNCTIONS 2.2.4 P30 to P32 (Port 3) These pins constitute a 3-bit I/O port. In addition, they also function as external interrupt input and capture edge input. This port can drive LEDs directly. Port 3 can be specified in the following operation modes in bit-wise. (1) Port mode In this mode, port 3 functions as a 3-bit I/O port. Port 3 can be set in the input or output mode in 1-bit units by using the port mode register 3 (PM3). When the port is used as an input port, an on-chip pull-up resistor can be used in the pull-up resistor option register (PUO). (2) Control mode In this mode, port 3 functions as the external interrupt input. (a) INTP0 to INTP2 These pins input external interrupt for which effective edges (rising edge, falling edge, and both the rising and falling edges) can be specified. (b) CPT2 This is a capture edge input pin. 2.2.5 P40 to P47 (Port 4) These pins constitute an 8-bit I/O port. In addition, they also function as key return signal detection. This port can drive LEDs directly. Port 4 can be set in the following operation modes in bit-wise. (1) Port mode In this mode, port 4 functions as an 8-bit I/O port which can be set in the input or output mode in 1-bit units by using the port mode register 4 (PM4). When used as an input port, an on-chip pull-up resistor can be used in the pull-up resistor option register (PUO). (2) Control mode In this mode, the pins of port 4 can be used as key return signal detection pin (KR0 to KR7). 36 User's Manual U11919EJ3V0UM00 CHAPTER 2 PIN FUNCTIONS 2.2.6 P50 to P53 (Port 5) These pins constitute a 4-bit I/O port. In addition, these pins provide the function for performing input/output to/from the timer. This port can drive LEDs directly. Port 5 can be specified in the following operation modes in bit-wise. (1) Port mode In this mode, port 5 functions as a 4-bit I/O port. Port 5 can be set in the input or output mode in 1-bit units by using the port mode register 5 (PM5). When the port is used as an input port, an on-chip pull-up resistor can be used in the pull-up resistor option register (PUO). (2) Control mode In this mode, port 5 functions as the timer input/output. (a) TI0 This is the external clock input pin for 8-bit timer/event counter. (b) TO0 This is an 8-bit timer output pin. (C) TO2 This is a 16-bit timer output pin. 2.2.7 RESET This pin inputs an active-low system reset signal. 2.2.8 X1, X2 These pins are used to connect a crystal resonator for system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 2.2.9 NC The NC (Non-connection) pin is not connected internally. Connect this pin directly to the VSS pin (it can also be left open). 2.2.10 VDD Positive power supply pins 2.2.11 VSS Ground potential pins 2.2.12 VPP (PD78F9026A only) A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Directly connect this pin to the VSS0 or VSS1 pin in the normal operating mode. User's Manual U11919EJ3V0UM00 37 CHAPTER 2 PIN FUNCTIONS 2.2.13 IC (mask ROM model only) The IC (Internally Connected) pin is used to set the PD789026 Subseries in the test mode in testing before shipment. In the normal operating mode, directly connect the IC pin to the VSS0 or VSS1 pin with as short a wire as possible. If a potential difference is generated between the IC pin and VSS0 or VSS1 pin due to a long wiring length between these pins, or external noise is superimposed on the IC pin, the user program may not run correctly. * Connect the IC pin directly to the VSS0 or VSS1 pin. VSS0 or VSS1 IC Keep short 38 User's Manual U11919EJ3V0UM00 CHAPTER 2 PIN FUNCTIONS 2.3 Pin Input/Output Circuits and Connection of Unused Pins Types of input/output circuits for pins and recommended connection of unused pins are shown in Table 2-1. For the configuration of each type of input/output circuit, see Figure 2-1. Table 2-1. Type of Input/Output Circuit of Each Pin and Handling of Unused Pins Pin Name P00 to P07 P10 to P17 P20/ASCK/SCK0 P21/TxD/SO0 P22/RxD/SI0 P30/INTP0 P31/INTP1 P32/INTP2/CPT2 P40/KR0 to P47/KR7 P50/TI0/TO0 P51/TO2 P52, P53 RESET NC 2 - Input - - Connect this pin directly to the VSS0 or VSS1 pin (possible to leave open). Connect these pins directly to the VSS0 or VSS1 pin. 5-X 8-J 5-X 8-J I/O Circuit Type 5-X Input/Output Input/output Input: Recommended Connection for Unused Pins Connect these pins to the VDD0, VDD1, VSS0, or VSS1 pin via respective resistors. Output: Leave these pins open. IC (mask ROM model) VPP (PD78F9026A) User's Manual U11919EJ3V0UM00 39 CHAPTER 2 PIN FUNCTIONS Figure 2-1. List of Pin Input/Output Circuits Type 2 Type 8-J VDD Pullup enable VDD0 P-ch IN/OUT Output disable N-ch VSS0 P-ch IN Output data Schmitt-triggered input with hysteresis characteristics Type 5-X VDD0 Pullup enable Output data VDD0 P-ch P-ch IN/OUT Output disable N-ch Port read 40 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The PD789026 Subseries can access 64 Kbytes of memory space. Figures 3-1 through 3-5 show the memory maps. Figure 3-1. Memory Map (PD789022) FFFFH Special Function Registers 256 x 8 bits FF00H FEFFH Internal High-Speed RAM 256 x 8 bits FE00H FDFFH Data Memory Space 1000H 0FFFH Reserved 0FFFH Program Area Program Memory Space Internal ROM 4,096 x 8 bits 0080H 007FH 0040H 003FH 002CH 002BH CALLT Table Area Program Area Vector Table Area 0000H 0000H User's Manual U11919EJ3V0UM00 41 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD789024) FFFFH Special Function Registers 256 x 8 bits FF00H FEFFH Internal High-Speed RAM 256 x 8 bits FE00H FDFFH Data Memory Space 2000H 1FFFH Reserved 1FFFH Program Area Program Memory Space Internal ROM 8,192 x 8 bits 0080H 007FH 0040H 003FH 002CH 002BH CALLT Table Area Program Area Vector Table Area 0000H 0000H 42 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD789025) FFFFH Special Function Registers 256 x 8 bits FF00H FEFFH Internal High-Speed RAM 512 x 8 bits FD00H FCFFH Data Memory Space 3000H 2FFFH Reserved 2FFFH Program Area Program Memory Space Internal ROM 12,288 x 8 bits 0080H 007FH 0040H 003FH 002CH 002BH CALLT Table Area Program Area Vector Table Area 0000H 0000H User's Manual U11919EJ3V0UM00 43 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (PD789026) FFFFH Special Function Registers 256 x 8 bits FF00H FEFFH Internal High-Speed RAM 512 x 8 bits FD00H FCFFH Data Memory Space 4000H 3FFFH Reserved 3FFFH Program Area Program Memory Space Internal ROM 16,384 x 8 bits 0080H 007FH 0040H 003FH 002CH 002BH CALLT Table Area Program Area Vector Table Area 0000H 0000H 44 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map (PD78F9026A) FFFFH Special Function Registers 256 x 8 bits FF00H FEFFH Internal High-Speed RAM 512 x 8 bits FD00H FCFFH Data Memory Space 4000H 3FFFH Reserved 3FFFH Program Area Program Memory Space Internal Flash Memory 16,384 x 8 bits 0080H 007FH 0040H 003FH 002CH 002BH CALLT Table Area Program Area Vector Table Area 0000H 0000H User's Manual U11919EJ3V0UM00 45 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The PD789026 Subseries provides the internal ROMs (or flash memory) containing the following capacities on each product. Table 3-1. Internal ROM Capacity Part Number Structure Internal ROM Capacity 4,096 x 8 bits 8,192 x 8 bits 12,288 x 8 bits 16,384 x 8 bits Flash memory 16,384 x 8 bits PD789022 PD789024 PD789025 PD789026 PD78F9026A Mask ROM The following areas are allocated to the internal program memory space: (1) Vector table area A 44-byte area of addresses 0000H to 002BH is reserved as a vector table area. This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation. Of a 16bit program address, the low-order 8 bits are stored in an even address, and the high-order 8 bits are stored in an odd address. Table 3-2. Vector Table Vector Table Address 0000H 0004H 0006H 0008H 000AH Interrupt Request RESET input INTWDT INTP0 INTP1 INTP2 Vector Table Address 000CH 000EH 0010H 0014H 002AH Interrupt Request INTSR/INTCSI0 INTST INTTM0 INTTM2 INTKR (2) CALLT instruction table area In a 64-byte area of addresses 0040H to 007FH, the subroutine entry address of a 1-byte call instruction (CALLT) can be stored. 46 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory (internal high-speed RAM) space The PD789026 Subseries provides internal high-speed RAM containing the following capacity on each product. The internal high-speed RAM can also be used as a stack memory. Table 3-3. Internal High-Speed RAM Capacity Part Number Capacity 256 x 8 bits PD789022 PD789024 PD789025 PD789026 PD78F9026A 512 x 8 bits 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to an area of FF00H to FFFFH (see Table 3-4). User's Manual U11919EJ3V0UM00 47 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing The PD789026 Subseries provides a variety of addressing modes which take account of memory manipulability, etc. Especially at address corresponding to data memory area (FE00H to FFFFH FFFFH Note 2 Note 1 , FD00H to ), particular addressing modes are possible to meet the functions of the special function registers (SFR) and other registers. Figures 3-6 through 3-10 show the data memory addressing modes. Notes 1. With PD789022 or PD789024 2. With PD789025, PD789026, or PD78F9026A Figure 3-6. Data Memory Addressing (PD789022) FFFFH Special Function Registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short Direct Addressing SFR Addressing Internal High-Speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct Addressing Register Indirect Addressing Based Addressing Reserved 1000H 0FFFH Internal ROM 4,096 x 8 bits 0000H 48 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Data Memory Addressing (PD789024) FFFFH Special Function Registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short Direct Addressing SFR Addressing Internal High-Speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct Addressing Register Indirect Addressing Based Addressing Reserved 2000H 1FFFH Internal ROM 8,192 x 8 bits 0000H User's Manual U11919EJ3V0UM00 49 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing (PD789025) FFFFH Special Function Registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short Direct Addressing SFR Addressing Internal High-Speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH Direct Addressing Register Indirect Addressing Based Addressing Reserved 3000H 2FFFH Internal ROM 12,288 x 8 bits 0000H 50 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Memory Addressing (PD789026) FFFFH Special Function Registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short Direct Addressing SFR Addressing Internal High-Speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH Direct Addressing Register Indirect Addressing Based Addressing Reserved 4000H 3FFFH Internal ROM 16,384 x 8 bits 0000H User's Manual U11919EJ3V0UM00 51 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing (PD78F9026A) FFFFH Special Function Registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short Direct Addressing SFR Addressing Internal High-Speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH Direct Addressing Register Indirect Addressing Based Addressing Reserved 4000H 3FFFH Internal Flash Memory 16,384 x 8 bits 0000H 52 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The PD789026 Subseries provides the following on-chip processor registers: 3.2.1 Control registers The control registers contains special functions to control the program sequence statuses and stack memory. A program counter, a program status word, and a stack pointer are control registers. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents is set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-11. Program Counter Configuration 15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions. RESET input sets PSW to 02H. Figure 3-12. Program Status Word Configuration 7 PSW IE Z 0 AC 0 0 1 0 CY User's Manual U11919EJ3V0UM00 53 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. interrupt are disabled. When IE = 1, the interrupt enabled (EI) status is set and interrupt request acknowledgement is controlled with an interrupt mask flag for each interrupt source. This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases. (c) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all other cases. (d) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. All interrupt requests except non-maskable 54 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-13. Stack Pointer Configuration 15 0 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-14 and 3-15. Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before instruction execution. Figure 3-14. Data to be Saved to Stack Memory PUSH rp Instruction CALL, CALLT Instructions SP SP SP _ 2 SP _ 2 SP _ 1 SP Lower Half Register Pairs Upper Half Register Pairs SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 SP _ 3 SP _ 3 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 PSW Interrupt Figure 3-15. Data to be Restored from Stack Memory POP rp Instruction RET Instruction RETI Instruction SP SP + 1 SP SP + 2 Lower Half Register Pairs Upper Half Register Pairs SP SP SP + 1 SP + 2 PC7 to PC0 PC15 to PC8 SP SP + 1 SP + 2 SP SP + 3 PC7 to PC0 PC15 to PC8 PSW User's Manual U11919EJ3V0UM00 55 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL). They can be written in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 3-16. General-Purpose Register Configuration (a) Absolute Names 16-Bit Processing 8-Bit Processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 (b) Functional Names 16-Bit Processing 8-Bit Processing H HL L D DE E B BC C A AX X 15 0 7 0 56 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function register (SFR) Unlike a general-purpose register, each special function register has a special function. It is allocated in the 256-byte area FF00H to FFFFH. The special function register can be manipulated, like the general-purpose register, with the operation, transfer, and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Writes a symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). manipulation can also be specified with an address. * 8-bit manipulation Writes a symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Writes a symbol reserved with assembler for the 16-bit manipulation instruction operand. When specifying an address, write an even address. Table 3-4 lists the special function register. The meanings of the symbols in this table are as follows: * Symbol Indicates the addresses of the incorporated special function registers. The symbols shown in this column are the reserved words of the assembler, and have already been defined in the header file called "sfrbit.h" of C compiler. Therefore, these symbols can be used as instruction operands if assembler or integrated debugger is used. * R/W Indicates whether the special function register can be read or written. R/W R W : Read/write : Read only : Write only This * Bit units for manipulation Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated. * After reset Indicates the status of the special function register when the RESET signal is input. User's Manual U11919EJ3V0UM00 57 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit FF00H FF01H FF02H FF03H FF04H FF05H FF10H Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Transmit shift register 00 Receive buffer register 00 FF16H FF17H FF18H FF19H FF1AH FF1BH FF20H FF21H FF22H FF23H FF24H FF25H FF42H FF50H FF51H FF53H FF5BH FF70H Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 4 Port mode register 5 Timer clock select register 2 8-bit compare register 00 8-bit timer counter 00 8-bit timer mode control register 00 16-bit timer mode control register 20 Asynchronous serial interface mode register 00 Asynchronous serial interface status register 00 Serial operation mode register 00 Baud rate generator control register 00 PM0 PM1 PM2 PM3 PM4 PM5 TCL2 CR00 TM00 TMC00 TMC20 ASIM00 W R R/W R/W - - - - - - - - - - - - - - - - - - - 00H Undefined 00H FFH 16-bit capture register 20 TCP20 - Note 1 After Reset 8 Bits Note 1 16 Bits - - - - - - - - Note 2 P0 P1 P2 P3 P4 P5 TXS00 SIO00 RXB00 CR20 R/W 00H W R W - - - FFH Undefined FFFFH 16-bit compare register 20 16-bit timer counter 20 TM20 R - Note 1 Note 2 0000H Note 2 Undefined FF71H ASIS00 R FF72H FF73H CSIM00 BRGC00 R/W Notes 1. CR20, TM20, and TCP20 are designed for 16-bit access. They can also be accessed in 8-bit mode, however. In 8-bit access mode, use direct addressing. 2. 16-bit access is allowed only with short direct addressing. 58 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit FFE0H FFE1H FFE4H FFE5H FFECH FFF5H FFF7H FFF9H FFFAH FFFBH Interrupt request flag register 0 Interrupt request flag register 1 Interrupt mask flag register 0 Interrupt mask flag register 1 External interrupt mode register 0 Key return mode register 00 Pull-up resistor option register Watchdog timer mode register Oscillation settling time select register Processor clock control register IF0 IF1 MK0 MK1 INTM0 KRM00 PUO WDTM OSTS PCC R/W - - 8 Bits 16 Bits - - - - - - - - - - 04H 02H 00H FFH 00H After Reset User's Manual U11919EJ3V0UM00 59 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (For details of each instruction, refer to 78K/0S Series User's Manual Instruction (U11047E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the "BR $addr16" instruction or a conditional branch instruction is executed. [Illustration] 15 PC + 15 8 7 S jdisp8 15 PC When S = 0, indicates all bits "0". When S = 1, indicates all bits "1". 0 6 0 0 ... PC is the start address of the next instruction of a BR instruction. 60 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces. [Illustration] In case of CALL !addr16 or BR !addr16 instruction 7 CALL or BR Low Addr. High Addr. 0 15 PC 87 0 User's Manual U11919EJ3V0UM00 61 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the low-order-5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces. [Illustration] 7 Instruction Code 0 6 1 5 ta4-0 1 0 0 15 Effective Address 0 0 0 0 0 0 0 8 0 7 0 6 1 5 10 0 7 Memory (Table) Low Addr. 0 Effective Address + 1 High Addr. 15 PC 8 7 0 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp A 0 7 X 0 15 PC 8 7 0 62 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Label or 16-bit immediate data Description [Example] MOV A, !FE00H; When setting !addr16 to FE00H Instruction Code 0 0 1 0 1 0 0 1 OP Code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 OP Code addr16 (Low) addr16 (High) 0 Memory User's Manual U11919EJ3V0UM00 63 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal highspeed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of all SFR areas. In this area, ports which are frequently accessed in a program and a compare register of the timer/event counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration]. [Operand format] Identifier saddr saddrp Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data (even address only) Description [Example] MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H Instruction Code 1 1 1 1 0 1 0 1 OP Code 0 0 1 1 0 0 0 0 30H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] 7 OP Code saddr-offset 0 Short Direct Memory 15 Effective Address 1 1 1 1 1 1 1 8 0 When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1. 64 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can also be accessed with short direct addressing. [Operand format] Identifier sfr Special function register name Description [Example] MOV PM0, A; When selecting PM0 for sfr Instruction Code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [Illustration] 7 OP Code sfr-offset 0 SFR 15 Effective Address 1 1 1 1 1 1 1 87 1 0 User's Manual U11919EJ3V0UM00 65 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] The general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with register specification code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format] Identifier r rp X, A, C, B, E, D, L, H AX, BC, DE, HL Description 'r' and 'rp' can be written with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Example] MOV A, C; When selecting the C register for r Instruction Code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 Register Specification Code INCW DE; When selecting the DE register pair for rp Instruction Code 1 0 0 0 1 0 0 0 Register Specification Code 66 User's Manual U11919EJ3V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specification code in the instruction code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [DE], [HL] Description [Example] MOV A, [DE]; When selecting register pair [DE] Instruction Code 0 0 1 0 1 0 1 1 [Illustration] 15 DE D 7 The contents of addressed memory are transferred 7 A 0 87 E 0 Memory address specified by register pair DE 0 User's Manual U11919EJ3V0UM00 67 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [HL+byte] Description [Example] MOV A, [HL+10H]; When setting byte to 10H Instruction Code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN instructions are executed or the register is saved/restored upon generation of an interrupt request. Stack addressing enables to access the internal high-speed RAM area only. [Example] In the case of PUSH DE Instruction Code 1 0 1 0 1 0 1 0 68 User's Manual U11919EJ3V0UM00 CHAPTER 4 PORT FUNCTIONS 4.1 Functions of Ports The PD789026 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. Alternate functions are provided in addition to the digital I/O port function. alternate functions, see Chapter 2. Figure 4-1. Port Types For more information on these P20 Port 2 P22 P00 Port 0 P30 Port 3 P32 P40 Port 4 P47 P50 Port 5 P53 P17 P07 P10 Port 1 User's Manual U11919EJ3V0UM00 69 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Pin Name P00 to P07 Input/Output Input/output Function Port 0 8-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. Port 1 8-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. Port 2 3-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. Port 3 3-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. Port 4 8-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. Port 5 4-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO). LEDs can be driven directly. After Reset Alternate Function Input - P10 to P17 Input/output Input - P20 P21 P22 Input/output Input SCK0/ASCK SO0/TxD SI0/RxD P30 P31 P32 Input/output Input INTP0 INTP1 INTP2/CPT2 P40 to P47 Input/output Input KR0 to KR7 P50 P51 P52, P53 Input/output Input TI0/TO0 TO2 - 70 User's Manual U11919EJ3V0UM00 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports have the following hardware configuration. Table 4-2. Port Configuration Parameter Control register Port mode register (PMm: m = 0 to 5) Pull-up resistor option register (PUO) Total: 34 (input/output: 34) Total: 34 (on-chip pull-up resistor can be connected by software) Configuration Port Pull-up resistor 4.2.1 Port 0 This is an 8-bit I/O port with output latch. Port 0 can be specified in the input or output mode in 1-bit units by using the port mode register 0 (PM0). When using P00 to P07 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using the pull-up resistor option register (PUO). RESET input sets port 0 to input mode. Figure 4-2 shows the block diagram of port 0. Figure 4-2. Block Diagram of P00 to P07 VDD0 WRPUO PUO0 RD P-ch Internal Bus WRPORT Output Latch (P00 to P07) WRPM Selector P00 to P07 PM00 to PM07 PUO : Pull-up resistor option register PM RD : Port mode register : Port 0 read signal WR : Port 0 write signal User's Manual U11919EJ3V0UM00 71 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is an 8-bit I/O port with output latch. Port 1 can be specified in the input or output mode in 1-bit units by using the port mode register 1 (PM1). When using P10 to P17 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using the pull-up resistor option register (PUO). RESET input sets port 1 to input mode. Figure 4-3 shows the block diagram of port 1. Figure 4-3. Block Diagram of P10 to P17 VDD0 WRPUO PUO1 RD P-ch Internal Bus WRPORT Output Latch (P10 to P17) WRPM Selector P10 to P17 PM10 to PM17 PUO : Pull-up resistor option register PM RD : Port mode register : Port 1 read signal WR : Port 1 write signal 72 User's Manual U11919EJ3V0UM00 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 This is a 3-bit I/O port with output latch. Port 2 can be specified in the input or output mode in 1-bit units by using the port mode register 2 (PM2). When using P20 to P22 pins as input port pins, on-chip pull-up resistors can be connected in 3-bit units by using the pull-up resistor option register (PUO). The pins of this port are also used as the data I/O and clock I/O pins of the serial interface. RESET input sets port 2 to input mode. Figures 4-4 through 4-6 show the block diagrams of port 2. Caution When using the pins of port 2 as the serial interface, the I/O mode and output latch must be set according to the function to be used. For details of the settings, see Table 9-2. Figure 4-4. Block Diagram of P20 VDD0 WRPUO PUO2 P-ch Alternate Function RD Internal Bus WRPORT Output Latch (P20) WRPM Selector P20/ASCK/SCK0 PM20 Alternate Function PUO : Pull-up resistor option register PM RD : Port mode register : Port 2 read signal WR : Port 2 write signal User's Manual U11919EJ3V0UM00 73 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 VDD0 WRPUO PUO2 P-ch RD Internal Bus WRPORT Output Latch (P21) WRPM Selector P21/TxD/SO0 PM21 Alternate Function PUO : Pull-up resistor option register PM RD : Port mode register : Port 2 read signal WR : Port 2 write signal 74 User's Manual U11919EJ3V0UM00 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 VDD0 WRPUO PUO2 P-ch Alternate Function RD Selector Internal Bus WRPORT Output Latch (P22) WRPM P22/RxD/SI0 PM22 PUO : Pull-up resistor option register PM RD : Port mode register : Port 2 read signal WR : Port 2 write signal User's Manual U11919EJ3V0UM00 75 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 This is a 3-bit I/O port with output latch. It can be specified in input or output mode in 1-bit units by using the port mode register 3 (PM3). When using P30 to P32 pins as input port pins, on-chip pull-up resistors can be connected in 3-bit units by using the pull-up resistor option register (PUO). The pins of this port are also used as the external interrupt input and capture edge input. RESET input sets port 3 to input mode. Figure 4-7 shows the block diagram of port 3. Figure 4-7. Block Diagram of P30 to P32 VDD0 WRPUO PUO3 P-ch Alternate Function RD Internal Bus WRPORT Output Latch (P30 to P32) WRPM Selector P30/INTP0 P31/INTP1 P32/INTP2/ CPT2 PM30 to PM32 PUO : Pull-up resistor option register PM RD : Port mode register : Port 3 read signal WR : Port 3 write signal 76 User's Manual U11919EJ3V0UM00 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 This is an 8-bit I/O port with output latch. Port 4 can be specified in the input or output mode in 1-bit units by using port mode register 4 (PM4). When using P40 to P47 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using the pull-up resistor option register (PUO). The pins of this port are also used as the key return input. RESET input sets port 4 to input mode. Figure 4-8 shows the block diagram of port 4. Caution When using port 4 for the key return function, it is necessary to set key return mode register 00. For details of the settings, see Section 10.3 (5). Figure 4-8. Block Diagram of P40 to P47 VDD0 WRPUO PUO4 RD P-ch WRKRM00 KRM000 to KRM007 Internal Bus WRPORT Output Latch (P40 to P47) WRPM P40/KR0 to P47/KR7 PM40 to PM47 Alternate Function KRM00 : Key return mode register 00 PUO PM RD WR : Pull-up resistor option register : Port mode register : Port 4 read signal : Port 4 write signal Selector User's Manual U11919EJ3V0UM00 77 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 This is a 4-bit I/O port with output latch. Port 5 can be specified in the input or output mode in 1-bit units by using the port mode register 5 (PM5). When using P50 to P53 pins as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using the pull-up resistor option register (PUO). The pins of this port are also used as the data I/O pins of the timer. RESET input sets port 5 to input mode. Figures 4-9 through 4-11 show the block diagrams of port 5. Figure 4-9. Block Diagram of P50 VDD0 WRPUO PUO5 P-ch Alternate Function RD Internal Bus WRPORT Output Latch (P50) WRPM Selector P50/TI0/TO0 PM50 Alternate Function PUO : Pull-up resistor option register PM RD : Port mode register : Port 5 read signal WR : Port 5 write signal 78 User's Manual U11919EJ3V0UM00 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P51 VDD0 WRPUO PUO5 P-ch RD Internal Bus WRPORT Output Latch (P51) WRPM Selector P51/TO2 PM51 Alternate Function PUO : Pull-up resistor option register PM RD : Port mode register : Port 5 read signal WR : Port 5 write signal User's Manual U11919EJ3V0UM00 79 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P52 and P53 VDD0 WRPUO PUO5 RD P-ch Internal Bus WRPORT Ouput Latch (P52, P53) WRPM Selector P52, P53 PM52, PM53 PUO : Pull-up resistor option register PM RD : Port mode register : Port 5 read signal WR : Port 5 write signal 80 User's Manual U11919EJ3V0UM00 CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following two types of registers control the ports. * Port mode registers (PM0 to PM5) * Pull-up resistor option register (PUO) (1) Port mode registers (PM0 to PM5) These registers are used to set port input/output in 1-bit units. Port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register and output latch according to Table 4-3. Caution As port 3 has an alternate function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. Table 4-3. Port Mode Register and Output Latch Settings when Using Alternate Functions Pin Name Alternate Function Name P30 P31 P32 INTP0 INTP1 INTP2 CPT2 P40 to P47 P50 Note PMxx Input/Output Input Input Input Input Input Input Output Output 1 1 1 1 1 1 0 0 Pxx x x x x x x 0 0 KR0 to KR7 TI0 TO0 P51 TO2 Note When an alternate function is used, set the key return mode register 00 (KRM00) to 1 (see Section 10.3 (5)). Caution When Port 2 is used for serial interface pin, the I/O mode and output latch must be set according to its function. For details of the settings, see Table 9-2. Remark x Pxx : Don't care : Output latch of port PMxx : Port mode register User's Manual U11919EJ3V0UM00 81 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Port Mode Register Format Symbol PM0 7 PM07 6 PM06 5 PM05 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00 Address FF20H After Reset FFH R/W R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W PM2 1 1 1 1 1 PM22 PM21 PM20 FF22H FFH R/W PM3 1 1 1 1 1 PM32 PM31 PM30 FF23H FFH R/W PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FF24H FFH R/W PM5 1 1 1 1 PM53 PM52 PM51 PM50 FF25H FFH R/W PMmn Pmn Pin Input/Output Mode Selection m = 0, 1, 4 : n = 0 to 7 m = 2, 3 : n = 0 to 2 m=5 : n = 0 to 3 Output mode (output buffer ON) Input mode (output buffer OFF) 0 1 (2) Pull-up resistor option register (PUO) The pull-up resistor option register (PUO) sets whether an on-chip pull-up resistor on each port is used or not. On the port which is specified to use the on-chip pull-up resistor in the PUO, the pull-up resistor can be internally used only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output mode in spite of setting the PUO. On-chip pull-up resistors cannot be used either when the pins are used as the alternate-function output pins. PUO is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears PUO to 00H. Figure 4-13. Pull-Up Resistor Option Register Format Symbol PUO 7 0 6 0 <5> PUO5 <4> PUO4 <3> PUO3 <2> PUO2 <1> PUO1 <0> PUO0 Address FFF7H After Reset 00H R/W R/W PUOm 0 1 On-chip pull-up resistor not used On-chip pull-up resistor used Port m On-Chip Pull-Up Resistor Selection (m = 0 to 5) 82 User's Manual U11919EJ3V0UM00 CHAPTER 4 PORT FUNCTIONS 4.4 Operation of Port Functions The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port. The data once written to the output latch is retained until new data is written to the output latch. (2) In input mode A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is not changed because the output buffer is OFF. The data once written to the output latch is retained until new data is written to the output latch. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 4.4.2 Reading from I/O port (1) In output mode The contents of an output latch can be read by using a transfer instruction. The contents of the output latch are not changed. (2) In input mode The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed. 4.4.3 Arithmetic operation of I/O port (1) In output mode An arithmetic operation can be performed with the contents of an output latch. The result of the operation is written to the output latch. The contents of the output latch are output from the port pins. The data once written to the output latch is retained until new data is written to the output latch. (2) In input mode The contents of the output latch become undefined. However, the status of the pin is not changed because the output buffer is OFF. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. User's Manual U11919EJ3V0UM00 83 [MEMO] 84 User's Manual U11919EJ3V0UM00 CHAPTER 5 CLOCK GENERATION CIRCUIT 5.1 Function of Clock Generation Circuit The clock generation circuit generates the clock to be supplied to the CPU and peripheral hardware. The system clock oscillator consists of the following type. * System clock oscillator This circuit oscillates at frequencies of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction. 5.2 Configuration of Clock Generation Circuit The clock generation circuit consists of the following hardware. Table 5-1. Configuration of Clock Generation Circuit Item Control register Oscillator Processor clock control register (PCC) System clock oscillator Configuration Figure 5-1. Block Diagram of Clock Generation Circuit Prescaler X1 X2 System Clock Oscillator Clock to Peripheral Hardware fX Prescaler fX 22 Selector STOP Standby Control Circuit Wait Control Circuit CPU Clock (fCPU) PCC1 Processor Clock Control Register (PCC) Internal Bus User's Manual U11919EJ3V0UM00 85 CHAPTER 5 CLOCK GENERATION CIRCUIT 5.3 Register Controlling Clock Generation Circuit The clock generation circuit is controlled by the following register: * Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC sets CPU clock selection and the ratio of division. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 02H. Figure 5-2. Processor Clock Control Register Format Symbol PCC 7 0 6 0 5 0 4 0 3 0 2 0 1 PCC1 0 0 Address FFFBH After Reset 02H R/W R/W PCC1 0 1 fX (0.2 s) fX/22 (0.8 s) CPU Clock (fCPU) Selection Caution Be sure to set bit 0 and bits 2 to 7 to 0. Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to opration at fX = 5.0 MHz. 3. Minimum instruction execution time: 2 fCPU * When fCPU = 0.2 s : 0.4 s * When fCPU = 0.8 s : 1.6 s 86 User's Manual U11919EJ3V0UM00 CHAPTER 5 CLOCK GENERATION CIRCUIT 5.4 System Clock Oscillation Circuits 5.4.1 System clock oscillation circuit The system clock oscillation circuit is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the reversed signal to the X2 pin. Figure 5-3 shows the external circuit of the system clock oscillation circuit. Figure 5-3. External Circuit of System Clock Oscillation Circuit (a) Crystal or ceramic oscillation VSS0, VSS1 X1 External Clock (b) External clock X1 X2 Crystal or Ceramic Resonator X2 Caution When using the system clock oscillator circuit, to avoid influence of wiring capacity, etc., wire the portion enclosed by the broken line in Figure 5-3 as follows: * Keep the wiring length as short as possible. * Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground of the capacitor of the oscillation circuit at the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. Figure 5-4 shows incorrect examples of resonator connection. User's Manual U11919EJ3V0UM00 87 CHAPTER 5 CLOCK GENERATION CIRCUIT Figure 5-4. Incorrect Examples of Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 5) VSS0, VSS1 X1 X2 VSS0, VSS1 X1 X2 88 User's Manual U11919EJ3V0UM00 CHAPTER 5 CLOCK GENERATION CIRCUIT Figure 5-4. Incorrect Examples of Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillation circuit (potential at points A, B, and C fluctuates) VDD Pmn VSS0, VSS1 X1 X2 VSS0, VSS1 High Current X1 X2 A B High Current C (e) Signal is extracted VSS0, VSS1 X1 X2 5.4.2 Divider circuit The divider circuit divides the output of the system clock oscillation circuit (fX) to generate various clocks. User's Manual U11919EJ3V0UM00 89 CHAPTER 5 CLOCK GENERATION CIRCUIT 5.5 Operation of Clock Generation Circuit The clock generation circuit generates the following clocks and controls operation modes of the CPU, such as the standby mode: * System clock * CPU clock fX fCPU * Clock to peripheral hardware The operation of the clock generation circuit is determined by the processor clock control register (PCC), as follows: (a) The slow mode 2 fCPU (1.6 s: at 5.0-MHz operation) of the system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is stopped . (b) Two types of CPU clocks fCPU (0.2 s and 0.8 s: at 5.0-MHz operation) can be selected by the PCC setting. (c) (d) Two standby modes, STOP and HALT, can be used. The clock to the peripheral hardware is supplied by dividing the system clock. operation). The other peripheral hardware is stopped when the system clock is stopped (except, however, the external clock input 90 User's Manual U11919EJ3V0UM00 CHAPTER 5 CLOCK GENERATION CIRCUIT 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (see Table 5-2). Table 5-2. Maximum Time Required for Switching CPU Clock Set Value before Switching PCC1 Set Value after Switching PCC1 0 0 1 2 clocks PCC1 1 4 clocks Remark Two clocks are the minimum instruction execution time of the CPU clock before switching. 5.6.2 Switching CPU clock The following figure illustrates how the CPU clock switches. Figure 5-5. Switching CPU Clock VDD RESET CPU Clock Slow Operation High-Speed Operation Wait (6.55 ms: at 5.0-MHz operation) Internal Reset Operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during which oscillation settles (215/fX) is automatically secured. After that, the CPU starts instruction execution at the slow speed of the system clock (1.6 s: at 5.0-MHz operation). <2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the high speed has elapsed, the processor clock control register (PCC) is rewritten so that the high speed can be selected. User's Manual U11919EJ3V0UM00 91 [MEMO] 92 User's Manual U11919EJ3V0UM00 CHAPTER 6 16-BIT TIMER 6.1 16-Bit Timer Functions 16-bit timer 20 has the following functions. * Timer interrupt * Timer output * Count value capture (1) Timer interrupt An interrupt is generated when a count value and compare value matches. (2) Timer output Timer output control is possible when a count value and compare value matches. (3) Count value capture A TM20 count value is latched synchronizing with the capture trigger and retained. User's Manual U11919EJ3V0UM00 93 CHAPTER 6 16-BIT TIMER 6.2 16-Bit Timer Configuration 16-bit timer 20 is configured in the following hardware. Table 6-1. Configuration of 16-Bit Timer 20 Item Timer counter Register 16 bits x 1 (TM20) Compare register : 16 bits x 1 (CR20) Capture register : 16 bits x 1 (TCP20) 1 (TO20) 16-bit timer mode control register 20 (TMC20) Port mode register 5 (PM5) Configuration Timer output Control register Figure 6-1. Block Diagram of 16-Bit Timer 20 Internal Bus 16-Bit Timer Mode Control Register 20 (TMC20) TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 P51 Output Latch PM51 16-Bit Compare Register 20 (CR20) Match fX/22 fX/26 F/F TOD20 16-Bit Timer Mode Control Register 20 TO2/P51 INTTM2 Selector 16-Bit Timer Counter 20 (TM20) OVF CPT2/P32/ INTP2 Edge Detection Circuit 16-Bit Capture Register 20 (TCP20) 16-Bit Counter Read Buffer Internal Bus 94 User's Manual U11919EJ3V0UM00 CHAPTER 6 16-BIT TIMER (1) 16-bit compare register 20 (CR20) This register compares the value set to CR20 with the count value of 16-bit timer counter 20 (TM20), and when they match, generates an interrupt request (INTTM2). CR20 is set with a 16-bit memory manipulation instruction. The 0000H to FFFFH values can be set. RESET input sets this register to FFFFH. Cautions 1. This register is manipulated with a 16-bit memory manipulation instruction, however an 8-bit memory manipulation instruction can be used. When manipulated with an 8bit memory manipulation instruction, accessing method should be direct addressing. This register can be accessed only in short direct addressing mode when a 16-bit memory manipulation instruction is used. 2. When rewriting CR20 during count operation, set CR20 to interrupt disable from interrupt mask flag register 0 (MK0) beforehand. Beside, set the timer output data to inversion disable by 16-bit timer mode control register 20 (TMC20). If CR20 is rewritten with the interrupt enabled, an interrupt request may be issued immediately. (2) 16-bit timer counter 20 (TM20) This is a 16-bit register that counts count pulses. TM20 is read with a 16-bit memory manipulation instruction. This register is in free running during count clock input. RESET input clears this register to 0000H and after that to be in free running. Cautions 1. The count value after releasing stop becomes undefined because the count operation is executed during the oscillation settling time. 2. This register is manipulated with a 16-bit memory manipulation instruction, however an 8-bit memory manipulation instruction can be used. When manipulated with an 8bit memory manipulation instruction, accessing method should be direct addressing. This register can be accessed only in short direct addressing mode when a 16-bit memory manipulation instruction is used. 3. When manipulated with an 8-bit memory manipulation instruction, readout should be performed in the order from low-order byte to high-order byte and must be in pairs. (3) 16-bit capture register 20 (TCP20) This is a 16-bit register that captures the contents of 16-bit timer counter 20 (TM20). TCP20 is set with a 16-bit memory manipulation instruction. RESET input makes this register undefined. Caution This register is manipulated with a 16-bit memory manipulation instruction, however an 8bit memory manipulation instruction can be used. When manipulated with an 8-bit memory manipulation instruction, accessing method should be direct addressing. This register can be accessed only in short direct addressing mode when a 16-bit memory manipulation instruction is used. (4) 16-bit counter read buffer This buffer latches a counter value and retains a count value of 16-bit timer counter 20 (TM20). User's Manual U11919EJ3V0UM00 95 CHAPTER 6 16-BIT TIMER 6.3 Registers Controlling 16-Bit Timer The following two types of registers control 16-bit timer 20. * 16-bit timer mode control register 20 (TMC20) * Port mode register 5 (PM5) (1) 16-bit timer mode control register 20 (TMC20) 16-bit timer mode control register 20 (TMC20) controls the setting of a count clock, capture edge, etc. TMC20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC20 to 00H. 96 User's Manual U11919EJ3V0UM00 CHAPTER 6 16-BIT TIMER Figure 6-2. 16-Bit Timer Mode Control Register 20 Format 7 TOD20 <6> TOF20 5 4 3 2 1 TCL200 <0> TOE20 Symbol TMC20 Address FF5BH After Reset 00H R/W R/WNote CPT201 CPT200 TOC20 TCL201 TOD20 0 1 Timer output data is 0. Timer output data is 1. Timer Output Data TOF20 0 1 Clear by reset and software Set by overflow of 16-bit timer Overflow Flag Set CPT201 CPT200 0 0 1 1 0 1 0 1 Capture operation disabled Rising edge of CPT2 Falling edge of CPT2 Both edges of CPT2 Capture Edge Selection TOC20 0 1 Inverse disabled Inverse enabled Timer Output Data Inverse Control TCL201 TCL200 0 0 0 1 fX/2 (1.25 MHz) fX/26 (78.1 kHz) Setting prohibited 2 16-bit Timer Counter 20 Count Clock Selection Other than above TOE20 0 1 Output disabled (port mode) Output enabled 16-bit Timer 20 Output Control Note Bit 7 is read-only. Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U11919EJ3V0UM00 97 CHAPTER 6 16-BIT TIMER (2) Port mode register 5 (PM5) This register sets the input/output of port 5 in 1-bit units. To use the P51/TO2 pin for timer output, set the output latch of PM51 and P51 to 0. PM5 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM5 to FFH. Figure 6-3. Port Mode Register 5 Format Symbol PM5 7 1 6 1 5 1 4 1 3 PM53 2 PM52 1 PM51 0 PM50 Address After Reset FF25H FFH R/W R/W PM51 0 1 Output mode (output buffer on) Input mode (output buffer off) P51 Pin Input/Output Selection 98 User's Manual U11919EJ3V0UM00 CHAPTER 6 16-BIT TIMER 6.4 16-Bit Timer Operation 6.4.1 Operation as timer interrupt In the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200. To operate the 16-bit timer as a timer interrupt, the following settings are required. * Set count values in CR20 * Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 6-4. Figure 6-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TMC20 0/1 0/1 0/1 0/1 0 0/1 0/1 Setting of Count Clock (see Table 6-2) Caution If 0 is set both to CPT201 and CPT200 flags, capture edge becomes setting prohibited. When the count value of 16-bit timer counter 20 (TM20) coincides with the value set to CR20, counting of TM20 continues and an interrupt request signal (INTTM2) is generated. Table 6-2 shows interval time, and Figure 6-5 shows timing of timer interrupt operation. Caution Perform the following processing when rewriting CR20 during count operation. <1> Disable the interrupt (TMMK20 (bit 7 of interrupt mask flag register 0 (MK0)) = 1). <2> Disable inversion control of timer output data (TOC20 = 0). If CR20 is rewritten with the interrupt enabled, an interrupt request may be issued immediately. Table 6-2. Interval Time of 16-Bit Timer 20 TCL201 0 0 Other than above TCL200 0 1 2 /fX (0.8 s) 2 Count Clock 18 Interval Time 2 /fX (52.4 ms) 2 /fX (838.9 ms) 22 2 /fX (12.8 s) 6 Setting prohibited Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U11919EJ3V0UM00 99 CHAPTER 6 16-BIT TIMER Figure 6-5. Timer Interrupt Operation Timing t Count Clock TM20 Count Value CR20 INTTM2 Interrupt Accepted TO20 TOF20 Overflow Flag Set Interrupt Accepted 0000H N 0001H N N FFFFH 0000H 0001H N N N FFFFH N Remark N = 0000H to FFFFH 100 User's Manual U11919EJ3V0UM00 CHAPTER 6 16-BIT TIMER 6.4.2 Operation as timer output Timer outputs are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200. To operate the 16-bit timer as a timer output, the following settings are required. * Set P51 to output mode (PM51 = 0). * Set 0 to the output latch of P51. * Set the count value in CR20. * Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 6-6. Figure 6-6. Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TMC20 0/1 0/1 0/1 1 0 0/1 1 TO20 Output Enable Setting of Count Clock (see Table 6-2) Inverse Enable of Timer Output Data Caution If both CPT201 flag and CPT200 flag are set to 0, the capture edge becomes operation prohibited. When the count value of 16-bit timer counter 20 (TM20) matches the value set in CR20, the output status of the TO2/P51 pin is inverted. This enables timer output. At that time, TM20 count is continued and an interrupt request signal (INTTM2) is generated. Figure 6-7 shows the timing of timer output (see Table 6-2 for the interval time of the 16-bit timer). Figure 6-7. Timer Output Timing t Count Clock TM20 Count Value CR20 INTTM2 Interrupt Accepted TO20Note TOF20 Overflow Flag Set Interrupt Accepted 0000H N 0001H N N FFFFH 0000H 0001H N N N FFFFH N Note The TO20 initial value becomes low level during output enable (TOE20 = 1). Remark N = 0000H to FFFFH User's Manual U11919EJ3V0UM00 101 CHAPTER 6 16-BIT TIMER 6.4.3 Capture operation The capture operation functions to capture and latch the count value of 16-bit timer counter 20 (TM20) synchronizing with a capture trigger. Set as shown in Figure 6-8 to allow the 16-bit timer to start the capture operation. Figure 6-8. Setting Contents of 16-Bit Timer Mode Control Register 20 during Capture Operation TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TMC20 0/1 0/1 0/1 0/1 0 0/1 0/1 Count Clock Selection Capture Edge Selection (see Table 6-3) 16-bit capture register 20 (TCP20) starts capture operation after being detected a CPT20 capture trigger edge, and latches and retains the count value of 16-bit timer counter 20. TCP20 fetches count value within 2 clocks and retains the count value until the next capture edge detection. Table 6-3 and Figure 6-9 show the setting contents of capture edge and capture operation timing, respectively. Table 6-3. Setting Contents of Capture Edge CPT201 0 0 1 1 CPT200 0 1 0 1 Capture Edge Selection Capture operation prohibited CPT2 pin rising edge CPT2 pin falling edge CPT2 pin both edges Caution Because TCP20 is rewritten when a capture trigger edge is detected during TCP20 read, disable the capture trigger detection during TCP20 read. Figure 6-9. Capture Operation Timing (Both Edges of CPT2 Pin are Specified) Count Clock TM20 Count Read Buffer TCP20 0000H 0000H 0001H 0001H Undefined Capture Start CPT2 Capture Edge Detection Capture Edge Detection N N N M-1 M M M Capture Start 102 User's Manual U11919EJ3V0UM00 CHAPTER 6 16-BIT TIMER 6.4.4 16-bit timer counter 20 readout The count value of 16-bit timer counter 20 (TM20) is read out by a 16-bit manipulation instruction. TM20 readout is performed through a counter read buffer. The counter read buffer latches the TM20 count value. And buffer operation is pended at the CPU clock falling edge after the read signal of the TM20 lower byte rises and the count value is retained. The counter read buffer value at the retention state can be read out as the count value. Cancellation of pending is performed at the CPU clock falling edge after the read signal of TM20 higher byte falls. RESET input clears TM20 to 0000H and starts freerunning. Figure 6-10 shows the timing of 16-bit timer counter 20 readout. Cautions 1. The count value after releasing stop becomes undefined because the count operation is executed during oscillation settling time. 2. Though TM20 is a dedicated register of a 16-bit transfer instruction, an 8-bit transfer instruction can be used. When using the 8-bit transfer instruction, execute by direct addressing. 3. When using the 8-bit transfer instruction, execute in the order from lower byte to higher byte in pairs. If the only lower byte is read, the pending state of the counter read buffer is not canceled, and if the only higher byte is read, an undefined count value is read. Figure 6-10. 16-Bit Timer Counter 20 Readout Timing CPU Clock Count Clock TM20 Count Read Buffer TM20 Read Signal Read Signal Latch Prohibited Period 0000H 0000H 0001H 0001H N N N+1 User's Manual U11919EJ3V0UM00 103 [MEMO] 104 User's Manual U11919EJ3V0UM00 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.1 8-Bit Timer/Event Counter Functions 8-bit timer/event counter 00 (TM00) has the following functions: * Interval timer * External event counter * Square wave output (1) 8-bit interval timer When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at any time intervals set in advance. Table 7-1. Interval Time of 8-Bit Timer/Event Counter 00 Minimum Interval Time 1/fX (200 ns) 2 /fX (6.4 s) 5 8 Maximum Interval Time 2 /fX (51.2 s) 2 /fX (1.64 ms) 13 Resolution 1/fX (200 ns) 2 /fX (6.4 s) 5 Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square wave output A square wave of arbitrary frequency can be output. Table 7-2. Square Wave Output Range of 8-Bit Timer/Event Counter 00 Minimum Pulse Width 1/fX (200 ns) 2 /fX (6.4 s) 5 8 Maximum Pulse Width 2 /fX (51.2 s) 2 /fX (1.64 ms) 13 Resolution 1/fX (200 ns) 2 /fX (6.4 s) 5 Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U11919EJ3V0UM00 105 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.2 8-Bit Timer/Event Counter Configuration The 8-bit timer/event counter consists of the following hardware configuration. Table 7-3. Configuration of 8-Bit Timer/Event Counter 00 Item Timer counter Register Timer output Control register 8 bits x 1 (TM00) Compare register: 8 bits x 1 (CR00) 1 (TO0) 8-bit timer mode control register 00 (TMC00) Port mode register 5 (PM5) Configuration Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 00 Internal Bus 8-Bit Compare Register 00 (CR00) Match fX P50 Output Latch PM50 INTTM0 Selector fX/25 TI0/P50/TO0 8-Bit Timer Counter 00 (TM00) Clear Selector F/F TO0/P50/TI0 2 TCE00 TCL001 TCL000 TOE00 8-Bit Timer Mode Control Register 1 Internal Bus (1) 8-bit compare register 00 (CR00) This is an 8-bit register to compare the value set to CR00 with the 8-bit timer register 00 (TM00) count value, and if they match, generates an interrupt request (INTTM0). CR00 is set with an 8-bit memory manipulation instruction. The 00H to FFH values can be set. RESET input makes CR00 undefined. Caution Before rewriting CR00, stop the timer operation. immediately. If CR00 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated (2) 8-bit timer counter 00 (TM00) This is an 8-bit register to count pulses. TM00 is read with an 8-bit memory manipulation instruction. RESET input clears TM00 to 00H. 106 User's Manual U11919EJ3V0UM00 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.3 8-Bit Timer/Event Counter Control Registers The following two types of registers are used to control the 8-bit timer/event counter. * 8-bit timer mode control register 00 (TMC00) * Port mode register 5 (PM5) (1) 8-bit timer mode control register 00 (TMC00) TMC00 determines whether to enable or disable 8-bit timer counter 00 (TM00), specifies the count clock for TM00, and controls the operation of the output control circuit of 8-bit timer/event counter 00. TMC00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC00 to 00H. Figure 7-2. 8-Bit Timer Mode Control Register 00 Format Symbol <7> 6 0 5 0 4 0 3 0 2 1 <0> Address FF53H After Reset 00H R/W R/W TMC00 TCE00 TCL001 TCL000 TOE00 TCE00 0 1 8-Bit Timer Counter 00 Operation Control Operation disabled (TM00 is cleared to 0.) Operation enabled TCL001 TCL000 0 0 1 1 0 1 0 1 fX (5.0 MHz) 8-Bit Timer Counter 00 Count Clock Selection fX/25 (156 kHz) Rising edge of TI0Note Falling edge of TI0Note TOE00 0 1 Output disabled (port mode) Output enabled 8-Bit Timer/Event Counter 00 Output Control Note When inputting a clock signal eternally, timer output cannot be used. Caution Always stop the timer before setting TMC00. Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U11919EJ3V0UM00 107 CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) Port mode register 5 (PM5) This register sets port 5 input/output in 1-bit units. When using the P50/TI0/TO0 pin for timer output, set PM50 and the output latch of P50 to 0. PM5 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM5 to FFH. Figure 7-3. Port Mode Register 5 Format 7 1 6 1 5 1 4 1 3 PM53 2 PM52 1 PM51 0 PM50 Symbol PM5 Address FF25H After Reset FFH R/W R/W PM50 0 1 Output mode (output buffer ON) Input mode (output buffer OFF) P50 Pin Input/Output Mode Selection 108 User's Manual U11919EJ3V0UM00 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4 8-Bit Timer/Event Counter Operation 7.4.1 Operation as interval timer Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare register 00 (CR00) in advance. To operate the 8-bit timer/event counter as an interval timer, the following settings are required. <1> Disable the operation of 8-bit timer counter 00 (TM00) (TCE00 (bit 7 of 8-bit timer mode control register 00 (TMC00)) = 0). <2> Set the count clock of the 8-bit timer/event counter (see Table 7-4). <3> Set a count value in CR00. <4> Enable the operation of TM00 (TCE00 = 1). When the count value of the 8-bit timer counter 00 (TM00) coincides with the value set to CR00, the value of TM00 is cleared to 0 and TM00 continues counting. At the same time, an interrupt request signal (INTTM0) is generated. Table 7-4 shows interval time, and Figure 7-4 shows the timing of interval timer operation. Cautions 1. Before rewriting CR00, stop the timer operation. immediately. 2. If setting the count clock in TMC00 and enabling the operation of TM00 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use the 8-bit timer/event counter as an interval timer, therefore, perform the setting in the above sequence. Table 7-4. Interval Time of 8-Bit Timer/Event Counter 00 TCL001 0 0 1 1 TCL000 0 1 0 1 Minimum Interval Time 1/fX (200 ns) 2 /fX (6.4 s) 5 8 If CR00 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated Maximum Interval Time 2 /fX (51.2 s) 2 /fX (1.64 ms) 8 2 x TI0 input cycle 13 Resolution 1/fX (200 ns) 2 /fX (6.4 s) 5 TI0 input cycle TI0 input cycle TI0 input edge cycle TI0 input edge cycle 2 x TI0 input cycle 8 Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U11919EJ3V0UM00 109 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-4. Interval Timer Operation Timing t Count Clock TM00 Count Value 00 01 N 00 Clear 01 N 00 Clear 01 N CR00 N N N N TCE00 Count Start INTTM0 Interrupt Accepted TO0 Interrupt Accepted Interval Time Interval Time Interval Time Remark Interval time = (N + 1) x t where N = 00H to FFH 110 User's Manual U11919EJ3V0UM00 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses input to the TI0/P50/TO0 pin by using timer counter 00 (TM00). To operate the 8-bit timer/event counter as an external event counter, the following settings are required. <1> Set P50 to input mode (PM50 = 1). <2> Disable the operation of 8-bit timer counter 00 (TM00) (TCE00 (bit 7 of 8-bit timer mode control register 00 (TMC00)) = 0). <3> Specify the rising or falling edge of TI0 (see Table 7-4). <4> Set a count value in CR00. <5> Enable the operation of TM00 (TCE00 = 1). Each time the valid edge specified by the bit 1 or 2 (TCL001 or TCL000) of TMC00 is input, the value of 8-bit timer counter 00 (TM00) is incremented. When the count value of TM00 coincides with the value set to CR00, the value of TM00 is cleared to 0 and TM00 continues counting. At the same time, an interrupt request signal (INTTM0) is generated. Figure 7-5 shows the timing of external event counter operation (with rising edge specified). Cautions 1. Before rewriting CR00, stop the timer operation. immediately. 2. If setting the count clock in TMC00 and enabling the operation of TM00 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use the 8-bit timer/event counter as an external event counter, therefore, perform the setting in the above sequence. Figure 7-5. External Event Counter Operation Timing (with Rising Edge Specified) TI0 Pin Input If CR00 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated TM00 Count Value 00 01 02 03 04 05 N-1 N 00 01 02 03 CR00 N TCE00 INTTM0 Remark N = 00H to FFH User's Manual U11919EJ3V0UM00 111 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.3 Operation as square wave output The 8-bit timer/event counter can generate the output square waves of arbitrary frequency at intervals specified by the count value set to 8-bit compare register 00 (CR00) in advance. To operate 8-bit timer/event counter 00 as square wave output, the following settings are required. <1> Set P50 to output mode (PM50 = 0). <2> Set 0 for the output latch of P50. <3> Disable the operation of 8-bit timer counter 00 (TM00) (TCE00 (bit 7 of 8-bit timer mode control register 00 (TMC00)) = 1). <4> Set a count clock for 8-bit timer/event counter 00 and enable output of TO0 (TOE00 (bit 0 of TMC00) = 1). <5> Set a count value in CR00. <6> Enable the operation of TM00 (TCE00 = 1). When the count value of 8-bit timer counter 00 (TM00) matches the value set in CR00, the TO0/P50/TI0 pin output will be inverted, respectively. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurred, the TM00 value will be cleared to 0 then resume to count, generating an interrupt request signal (INTTM0). Setting 0 to the bit 7 in TMC00, that is, TCE00 makes the square-wave output clear to 0. Table 7-5 lists square wave output range, and Figure 7-6 shows timing of square wave output. Cautions 1. Before rewriting CR00, stop the timer operation. immediately. 2. If setting the count clock in TMC00 and enabling the operation of TM00 are performed at the same time with an 8-bit memory manipulation instruction, the error one cycle after the timer has been started may exceed one clock. To use the 8-bit timer/event counter as a square wave output, therefore, perform the setting in the above sequence. Table 7-5. Square Wave Output Range of 8-Bit Timer/Event Counter 00 TCL001 0 0 TCL000 0 1 Minimum Pulse Width 1/fX (200 ns) 2 /fX (6.4 s) 5 8 If CR00 is rewritten while the timer operation is enabled, the coincidence interrupt request signal may be generated Maximum Pulse Width 2 /fX (51.2 s) 2 /fX (1.64 ms) 13 Resolution 1/fX (200 ns) 2 /fX (6.4 s) 5 Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. 112 User's Manual U11919EJ3V0UM00 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-6. Square Wave Output Timing Count Clock TM00 Count Value 00 01 N 00 Clear 01 N 00 Clear 01 N CR00 N N N N TCE00 Count Start INTTM0 Interrupt Accepted TO0Note Interrupt Accepted Note The initial value of TO0 at output enable (TOE00 = 1) becomes low-level. User's Manual U11919EJ3V0UM00 113 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.5 Notes on Using 8-Bit Timer/Event Counters (1) Error on starting timer An error of up to 1 clock occurs after the timer has been started until a coincidence signal is generated. This is because 8-bit timer counter 00 (TM00) started asynchronously with the count pulse. Figure 7-7. 8-Bit Timer Counter 00 Start Timing Count Pulse TM00 Count Value 00H 01H 02H 03H 04H Timer starts (2) Setting of 8-bit compare register 8-bit compare register 00 (CR00) can be set to 00H. Therefore, one pulse can be counted when an 8-bit timer/event counter operates as an event counter. Figure 7-8. External Event Counter Operation Timing TI0 Input CR00 00H TM00 Count Value 00H 00H 00H 00H Interrupt Request Flag 114 User's Manual U11919EJ3V0UM00 CHAPTER 8 WATCHDOG TIMER 8.1 Watchdog Timer Functions The watchdog timer has the following functions: * Watchdog timer * Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect inadvertent program loops. When an inadvertent loop is detected, a non-maskable interrupt or the RESET signal can be generated. Table 8-1. Inadvertent Loop Detection Time of Watchdog Timer Inadvertent Loop Detection Time 11 2 x 1/fX At fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms 2 x 1/fX 13 2 x 1/fX 15 17 2 x 1/fX fX: System clock oscillation frequency (2) Interval timer The interval timer generates an interrupt at a given interval set in advance. Table 8-2. Interval Time Interval 2 x 1/fX 11 At fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms 2 x 1/fX 13 2 x 1/fX 15 2 x 1/fX 17 fX: System clock oscillation frequency User's Manual U11919EJ3V0UM00 115 CHAPTER 8 WATCHDOG TIMER 8.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 8-3. Configuration of Watchdog Timer Item Control register Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Configuration Figure 8-1. Block Diagram of Watchdog Timer Internal Bus fX 24 fX 26 Prescaler fX 28 fX 210 TMMK4 TMIF4 Selector INTWDT Maskable Interrupt Request RESET INTWDT Non-Maskable Interrupt Request 7-Bit Counter Clear Control Circuit 3 TCL22 TCL21 TCL20 Timer Clock Select Register 2 (TCL2) RUN WDTM4 WDTM3 Watchdog Timer Mode Register (WDTM) Internal Bus 116 User's Manual U11919EJ3V0UM00 CHAPTER 8 WATCHDOG TIMER 8.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. * Timer clock select register 2 (TCL2) * Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input clears TCL2 to 00H. Figure 8-2. Timer Clock Select Register 2 Format Symbol TCL2 7 0 6 0 5 0 4 0 3 0 2 TCL22 1 TCL21 0 TCL20 Address FF42H After Reset 00H R/W R/W TCL22 0 0 1 1 TCL21 0 1 0 1 TCL20 0 0 0 0 Watchdog Timer Count Clock Selection fX/2 fX/2 4 6 Interval Time 2 /fX (410 s) 11 (312.5 kHz) (78.1 kHz) (19.5 kHz) 213/fX (1.64 ms) 215/fX (6.55 ms) 217/fX (26.2 ms) fX/28 fX/210 (4.88 kHz) Setting prohibited Other than above Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U11919EJ3V0UM00 117 CHAPTER 8 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 8-3. Watchdog Timer Mode Register Format Symbol WDTM <7> RUN 6 0 5 0 4 3 2 0 1 0 0 0 Address FFF9H After Reset 00H R/W R/W WDTM4 WDTM3 RUN 0 1 Stops counting. Selects Operation of Watchdog TimerNote 1 Clears counter and starts counting. WDTM4 WDTM3 0 0 1 1 0 1 0 1 Operation stop Selects Operation Mode of Watchdog TimerNote 2 Interval timer mode (overflow and maskable interrupt occur)Note 3 Watchdog timer mode 1 (overflow and non-maskable interrupt occur) Watchdog timer mode 2 (overflow occurs and reset operation started) Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is started, it cannot be stopped by any means other than RESET input. 2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software. 3. The watchdog timer starts operations as an interval timer when RUN is set to 1. Cautions 1. When the watchdog timer is cleared by setting 1 to RUN, the actual overflow time is up to 0.8% shorter than the time set by timer clock select register 2 (TCL2). 2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of interrupt request flag register 0 (IF0)) being set to 0. When watchdog timer mode 1 or 2 is selected under the condition where TMIF4 is 1, a non-maskable interrupt occurs at the completion of rewriting. 118 User's Manual U11919EJ3V0UM00 CHAPTER 8 WATCHDOG TIMER 8.4 Operation of Watchdog Timer 8.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started. Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the inadvertent loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3 (WDTM3) of WDTM. The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction. Caution The actual inadvertent loop detection time may be up to 0.8% shorter than the set time. Table 8-4. Inadvertent Loop Detection Time of Watchdog Timer TCL22 0 0 1 1 TCL21 0 1 0 1 TCL20 0 0 0 0 Inadvertent Loop Detection Time 2 x 1/fX 11 At fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms 2 x 1/fX 13 2 x 1/fX 15 17 2 x 1/fX fX: System clock oscillation frequency User's Manual U11919EJ3V0UM00 119 CHAPTER 8 WATCHDOG TIMER 8.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1 respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a count value set in advance. Select a count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1. In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable interrupts. The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the interval timer, and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set, unless the RESET signal is input. 2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the set time. Table 8-5. Interval Time of Interval Timer TCL22 0 0 1 1 TCL21 0 1 0 1 TCL20 0 0 0 0 2 x 1/fX 11 Interval Time At fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms 2 x 1/fX 13 2 x 1/fX 15 17 2 x 1/fX fX: System clock oscillation frequency 120 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 9.1 Serial Interface 00 Functions Serial interface 00 employs the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out. It enables power consumption reduction. (2) Asynchronous serial interface (UART) mode In this mode, one byte of data following the start bit is transmitted/received, and full-duplex operation is possible. A UART-dedicated baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin. (3) 3-wire serial I/O mode (MSB/LSB start bit switchable) In this mode, 8-bit data transfer is carried out with three lines, one for serial clock (SCK0) and two for serial data (SI0, SO0). The 3-wire serial I/O mode supports simultaneous transmit and receive operation, reducing data transfer processing time. It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus allowing connection to devices with either start bit. The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/Os such as the 75XL Series, 78K Series, and 17K Series, which have internal conventional synchronous serial interface. 9.2 Serial Interface 00 Configuration Serial interface 00 has the following hardware configuration. Table 9-1. Configuration of Serial Interface 00 Item Register Transmission shift register 00 (TXS00) Receive shift register 00 (RXS00) Receive buffer register 00 (RXB00) Serial operation mode register 00 (CSIM00) Asynchronous serial interface mode register 00 (ASIM00) Asynchronous serial interface status register 00 (ASIS00) Baud rate generator control register 00 (BRGC00) Configuration Control register User's Manual U11919EJ3V0UM00 121 122 Figure 9-1. Block Diagram of Serial Interface 00 Internal Bus Asynchronous Serial Interface Status Register 00 (ASIS00) Receive Buffer Register 00 (RXB00/SIO00) PE00 FE00 OVE00 Direction Control Circuit Asynchronous Serial Interface Mode Register 00 (ASIM00) TXE00 RXE00 PS100 PS000 CL00 SL00 Direction Control Circuit Transmit Shift Register (TXS00/SIO00) Receive Shift Register (RXS00) Receive Control Circuit INTSR/INTCSI0 Transmit Control Circuit SCK Output Control Circuit INTST Note RxD/SI0/P22 TxD/SO0/P21 PM21 CHAPTER 9 SERIAL INTERFACE 00 User's Manual U11919EJ3V0UM00 PM20 ASCK/SCK0/P20 Baud Rate Generator fX/2 to fX/28 CSIE00 TXE00 RXE00 CSIE00 DIR00 CSCK00 Serial Operation Mode Register 00 (CSIM00) Internal Bus 4 CSCK00 TPS003 TPS002 TPS001 TPS000 Baud Rate Generator Control Register 00 (BRGC00) Note For the configuration of the baud rate generator, see Figure 9-2. Figure 9-2. Block Diagram of Baud Rate Generator CSIE00 TXE00 RXE00 fX fX 23 fX 22 fX 2 Stop Prescaler fX 28 Clear Clear 1/2 3-Bit Counter fX 27 fX 26 fX 25 fX 24 BRGC00 Write TXE00 Selector Transmit Clock ASCK/SCK0/P20 Selector Receive Clock 4 3-Bit Counter Clear Clear CSIE00 CHAPTER 9 SERIAL INTERFACE 00 User's Manual U11919EJ3V0UM00 CSCK00 RXE00 CSIE00 Start Bit Detection BRGC00 Write TPS003 TPS002 TPS001 TPS000 RXE00 Baud Rate Generator Control Register 00 (BRGC00) Internal Bus Selector 1/2 123 CHAPTER 9 SERIAL INTERFACE 00 (1) Transmit shift register 00 (TXS00) This register is used to specify data to be transmitted. Data written to TXS00 is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written to TXS00 are transferred as the transmit data. The transmit operation is started by writing data to TXS00. TXS00 is written to with an 8-bit memory manipulation instruction. It cannot be read. RESET input sets TXS00 to FFH. Caution Do not write to TXS00 during transmission. TXS00 and receive buffer register 00 (RXB00) are allocated to the same address, and when reading is performed, RXB00 values are read. (2) Receive shift register 00 (RXS00) This register is used to convert serial data input to the RxD pin into parallel data. Each time one byte of data is received, it is transferred to receive buffer register 00 (RXB00). RXS00 cannot be manipulated directly by program. (3) Receive buffer register 00 (RXB00) This register is used to hold received data. Each time one byte of data is received, a new byte of data is transferred from receive shift register 00 (RXS00). If the data length is specified as 7 bits, receive data is transferred to bits 0 to 6 of RXB00, and the MSB of RXB00 always becomes 0. RXB00 can be read with an 8-bit memory manipulation instruction. It cannot be written to. RESET input makes RXB00 undefined. Caution RXB00 and transmit shift register 00 (TXS00) are allocated to the same address, and when writing is performed, the values are written to TXS00. (4) Transmit control circuit This circuit controls transmit operations by adding a start bit, parity bit, and stop bit to data written to transmit shift register 00 (TXS00), according to the data set to asynchronous serial interface mode register 00 (ASIM00). (5) Receive control circuit This circuit controls receive operations according to the data set to asynchronous serial interface mode register 00 (ASIM00). It performs also parity error check, etc., during receive operations, and when an error is detected, it sets the value to asynchronous serial interface status register 00 (ASIS00) depending on the nature of the error. 124 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 9.3 Serial Interface 00 Control Register The following four types of registers are used to control serial interface 00. * * * * Serial operation mode register 00 (CSIM00) Asynchronous serial interface mode register 00 (ASIM00) Asynchronous serial interface status register 00 (ASIS00) Baud rate generator control register 00 (BRGC00) Serial operation mode register 00 (CSIM00) This register is set when using serial interface 00 in the 3-wire serial I/O mode. CSIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM00 to 00H. Figure 9-3. Serial Operation Mode Register 00 Format Symbol <7> 6 0 5 0 4 0 3 0 2 1 0 0 Address FF72H After Reset 00H R/W R/W (1) CSIM00 CSIE00 DIR00 CSCK00 CSIE00 0 1 Operation stop Operation enable Operation Control in 3-Wire Serial I/O Mode DIR00 0 1 MSB LSB Start Bit Specification CSCK00 0 1 Clock Selection in 3-Wire Serial I/O Mode Input clock to SCK0 pin from external Dedicated baud rate generator output Cautions 1. Be sure to set bit 0 and bits 3 to 6 to 0. 2. Set 00H to CSIM00 at the UART mode. User's Manual U11919EJ3V0UM00 125 CHAPTER 9 SERIAL INTERFACE 00 (2) Asynchronous serial interface mode register 00 (ASIM00) This register is set when using serial interface 00 in the asynchronous serial interface mode. ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. Figure 9-4. Asynchronous Serial Interface Mode Register 00 Format Symbol ASIM00 <7> TXE00 <6> RXE00 5 PS001 4 PS000 3 CL00 2 SL00 1 0 0 0 Address FF70H After Reset 00H R/W R/W TXE00 0 1 Transmit operation stop Transmit operation enable Transmit Operation Control RXE00 0 1 Receive operation stop Receive operation enable Receive Operation Control PS001 0 0 PS000 0 1 No parity Parity Bit Specification Always add 0 parity at transmission Parity check is not performed at reception (No parity error is generated) Odd parity Even parity 1 1 0 1 CL00 0 1 7 bits 8 bits Character Length Specification SL00 0 1 1 bit 2 bits Transmit Data Stop Bit Length Specification Cautions 1. Be sure to set bits 0 and 1 to 0. 2. Set 00H to ASIM00 at the 3-wire serial I/O mode. 3. Switching operating modes must be performed after the halt of serial transmit/receive operation. 126 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 Table 9-2. Serial Interface 00 Operating Mode Settings (1) Operation stop mode CSIM00 PM22 P22 PM21 P21 PM20 P20 Start Bit x Note 1 ASIM00 Shift P22/SI0/RxD P21/SO0/TxD P20/SCK0/ASCK Clock Pin Function - P22 Pin Function P21 Pin Function P20 TXE00 RXE00 CSIE00 DIR00 CSCK00 0 0 0 x x x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 - Other than above Setting prohibited (2) 3-wire serial I/O mode CSIM00 PM22 P22 PM21 P21 PM20 P20 Start Bit 1Note 2 x Note 2 ASIM00 Shift P22/SI0/RxD P21/SO0/TxD P20/SCK0/ASCK Clock Pin Function External clock TXE00 RXE00 CSIE00 DIR00 CSCK00 0 0 1 0 0 0 1 1 x Pin Function SO0 (CMOS output) Pin Function SCK0 input MSB SI0 Note 2 1 0 1 Internal clock SCK0 output 1 1 0 1 x LSB External clock SCK0 input 1 0 1 Internal clock SCK0 output Other than above Setting prohibited (3) Asynchronous serial interface mode CSIM00 PM22 P22 PM21 P21 PM20 P20 Start Bit x Note 1 ASIM00 Shift P22/SI0/RxD P21/SO0/TxD P20/SCK0/ASCK Clock Pin Function External clock TXE00 RXE00 CSIE00 DIR00 CSCK00 1 0 0 0 0 x Note 1 Pin Function TxD (CMOS output) Pin Function ASCK input 0 1 1 x LSB P22 x Note 1 x Note 1 Internal clock P20 0 1 0 0 0 1 x x Note 1 x Note 1 1 x External clock RxD P21 ASCK input x Note 1 x Note 1 Internal clock P20 1 1 0 0 0 1 x 0 1 1 x External clock TxD (CMOS output) ASCK input x Note 1 x Note 1 Internal clock P20 Other than above Setting prohibited Notes 1. Can be used as port function. 2. If used only for transmission, can be used as P22 (CMOS input/output). Remark x: Don't care. User's Manual U11919EJ3V0UM00 127 CHAPTER 9 SERIAL INTERFACE 00 (3) Asynchronous serial interface status register 00 (ASIS00) This register indicates types of error when a reception error is generated in the asynchronous interface mode. ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS00 become undefined in the 3-wire serial I/O mode. RESET input clears ASIS00 to 00H. Figure 9-5. Asynchronous Serial Interface Status Register 00 Format Symbol ASIS00 7 0 6 0 5 0 4 0 3 0 2 PE00 1 FE00 0 OVE00 Address FF71H After Reset 00H R/W R PE00 0 1 Parity error not generated Parity Error Flag Parity error generated (when the parity of transmit data does not coincide.) FE00 0 1 Flaming error not generated Flaming Error Flag Flaming error generated (when stop bit is not detected.)Note 1 OVE00 0 1 Overrun error not generated Overrun Error Flag Overrun error generatedNote 2 (when the next receive operation is completed before the data is read from the receive buffer register.) Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial interface mode register 00 (ASIM00), the stop bit detection in the case of reception is performed with 1 bit. 2. When an overrun error occurs, be sure to read out receive buffer register 00 (RXB00). Unless RXB00 is read out, overrun errors occur at each data reception. 128 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 (4) Baud rate generator control register 00 (BRGC00) This register is used to set the serial clock of serial interface 00. BRGC00 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC00 to 00H. Figure 9-6. Baud Rate Generator Control Register 00 Format Symbol BRGC00 7 6 5 4 3 0 2 0 1 0 0 0 Address FF73H After Reset 00H R/W R/W TPS003 TPS002 TPS001 TPS000 TPS003 0 0 0 0 0 0 0 0 1 TPS002 0 0 0 0 1 1 1 1 0 TPS001 TPS000 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fX/2 (2.5 MHz) fX/22 3-Bit Counter Source Clock Selection n 1 2 3 4 5 6 7 8 - (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 fX/26 (156 kHz) (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) Input clock from external to ASCK pinNote Setting prohibited Other than above Note Only used in UART mode. Cautions 1. When writing to BRGC00 is performed during a communication operation, the baud rate generator output is disrupted and communications cannot be performed normally. Be sure not to write to BRGC00 during communication operation. 2. Be sure not to select n = 1 during an operation at fX = 5.0 MHz because n = 1 exceeds the baud rate limit. 3. When selecting an input clock from an external source, set port mode register 2 (PM2) to the input mode. Remarks 1. fX : System clock oscillation frequency 2. n : Value determined by setting TPS000 through TPS003 (1 n 8) 3. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U11919EJ3V0UM00 129 CHAPTER 9 SERIAL INTERFACE 00 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of system clock The transmit/receive clock is generated by scaling the system clock. The baud rate generated from the system clock is found from the following expression. [Baud rate] = fX [Hz] 2n + 1 x 8 fX : System clock oscillation frequency n : Value determined by values of TPS000 through TPS003 as shown in Figure 9-6 (2 n 8) Table 9-3. Example of Relationship between System Clock and Baud Rate Baud Rate (bps) n BRGC00 Set Value fX = 5.0 MHz 1,200 2,400 4,800 9,600 19,200 38,400 76,800 8 7 6 5 4 3 2 70H 60H 50H 40H 30H 20H 10H 1.73 Error (%) fX = 4.9152 MHz 0 Caution Be sure not to select n = 1 during an operation at fX = 5.0 MHz because n = 1 exceeds the baud rate limit. 130 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is found from the following expression. [Baud rate] = fASCK [Hz] 16 fASCK: Frequency of clock input to the ASCK pin Table 9-4. Relationship between ASCK Pin Input Frequency and Baud Rate (When BRGC00 is Set to 80H) Baud Rate (bps) 75 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 ASCK Pin Input Frequency (kHz) 1.2 2.4 4.8 9.6 19.2 38.4 76.8 153.6 307.2 500.0 614.4 User's Manual U11919EJ3V0UM00 131 CHAPTER 9 SERIAL INTERFACE 00 9.4 Serial Interface 00 Operation Serial interface 00 provides the following three types of modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode 9.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed, therefore, the power consumption can be reduced. The P20/SCK0/ASCK, P21/SO0/TxD, and P22/SI0/RxD pins can be used as normal I/O ports. (1) Register setting Operation stop mode is set by serial operation mode register 00 (CSIM00) and asynchronous serial interface mode register 00 (ASIM00). (a) Serial operation mode register 00 (CSIM00) CSIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM00 to 00H. Symbol CSIM00 <7> CSIE00 6 0 5 0 4 0 3 0 2 DIR00 1 CSCK00 0 0 Address FF72H After Reset 00H R/W R/W CSIE00 0 1 Operation stop Operation enable Operation Control in 3-Wire Serial I/O Mode Caution Be sure to set bit 0 and bits 3 to 6 to 0. 132 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 (b) Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. Symbol ASIM00 <7> TXE00 <6> RXE00 5 PS001 4 PS000 3 CL00 2 SL00 1 0 0 0 Address FF70H After Reset 00H R/W R/W TXE00 0 1 Transmit operation stop Transmit operation enable Transmit Operation Control RXE00 0 1 Receive operation stop Receive operation enable Receive Operation Control Caution Be sure to set bits 0 and 1 to 0. User's Manual U11919EJ3V0UM00 133 CHAPTER 9 SERIAL INTERFACE 00 9.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible. This device incorporates a UART-dedicated baud rate generator that enables communications at a desired transfer rate from many options. In addition, the baud rate can also be defined by dividing the input clock to the ASCK pin. The UART-dedicated baud rate generator also can output the 31.25-kbps baud rate that complies with the MIDI standard. (1) Register setting The UART mode is set by serial operation mode register 00 (CSIM00), asynchronous serial interface mode register 00 (ASIM00), asynchronous serial interface status register 00 (ASIS00), and baud rate generator control register 00 (BRGC00). (a) Serial operation mode register 00 (CSIM00) CSIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM00 to 00H. Set 00H to CSIM00 when UART mode is selected. Symbol CSIM00 <7> CSIE00 6 0 5 0 4 0 3 0 2 DIR00 1 CSCK00 0 0 Address FF72H After Reset 00H R/W R/W CSIE00 0 1 Operation stop Operation enable Operation Control in 3-Wire Serial I/O Mode DIR00 0 1 MSB LSB Start Bit Specification CSCK00 0 1 Clock Selection in 3-Wire Serial I/O Mode Input clock to SCK0 pin from external Dedicated baud rate generator output Caution Be sure to set bit 0 and bits 3 to 6 to 0. 134 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 (b) Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. Symbol ASIM00 <7> TXE00 <6> RXE00 5 PS001 4 PS000 3 CL00 2 SL00 1 0 0 0 Address FF70H After Reset 00H R/W R/W TXE00 0 1 Transmit operation stop Transmit operation enable Transmit Operation Control RXE00 0 1 Receive operation stop Receive operation enable Receive Operation Control PS001 0 0 PS000 0 1 No parity Parity Bit Specification Always add 0 parity at transmission Parity check is not performed at reception (No parity error is generated) Odd parity Even parity 1 1 0 1 CL00 0 1 7 bits 8 bits Character Length Specification SL00 0 1 1 bit 2 bits Transmit Data Stop Bit Length Specification Cautions 1. 2. Be sure to set bits 0 and 1 to 0. Switching operating modes must be performed after the halt of serial transmit/receive operation. User's Manual U11919EJ3V0UM00 135 CHAPTER 9 SERIAL INTERFACE 00 (c) Asynchronous serial interface status register 00 (ASIS00) ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIS00 to 00H. Symbol ASIS00 7 0 6 0 5 0 4 0 3 0 2 PE00 1 FE00 0 OVE00 Address FF71H After Reset 00H R/W R PE00 0 1 Parity error not generated Parity Error Flag Parity error generated (when the parity of transmit data does not coincide.) FE00 0 1 Framing error not generated Flaming Error Flag Framing error generated (when stop bit is not detected.)Note 1 OVE00 0 1 Overrun error not generated Overrun Error Flag Overrun error generatedNote 2 (when the next receive operation is completed before the data is read from the receive buffer register.) Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial interface mode register 00 (ASIM00), the stop bit detection in the case of reception is performed with 1 bit. 2. Be sure to read reception buffer register 00 (RXB00) when an overrun error occurs. If not, every time the data is received an overrun error is generated. 136 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 (d) Baud rate generator control register 00 (BRGC00) BRGC00 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC00 to 00H. Symbol BRGC00 7 6 5 4 3 0 2 0 1 0 0 0 Address FF73H After Reset 00H R/W R/W TPS003 TPS002 TPS001 TPS000 TPS003 TPS002 TPS001 TPS000 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fX/2 (2.5 MHz) 3-Bit Counter Source Clock Selection n 1 2 3 4 5 6 7 8 fX/22 (1.25 MHz) fX/23 fX/24 (625 kHz) (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) Input clock from external to ASCK pin Setting prohibited - Other than above Cautions 1. When writing to BRGC00 is performed during a communication operation, the output of baud rate generator is disrupted and communications cannot be performed normally. operation. Be sure not to write to BRGC00 during communication 2. 3. Be sure not to select n = 1 during an operation at fX = 5.0 MHz because n = 1 exceeds the baud rate limit. When selecting an input clock from an external source, set port mode register 2 (PM2) to the input mode. Remarks 1. fX : System clock oscillation frequency 2. n : Value determined by setting TPS000 through TPS003 (1 n 8) 3. The parenthesized values apply to operation at fX = 5.0 MHz. The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of system clock The transmit/receive clock is generated by scaling the system clock. The baud rate generated from the system clock is estimated by using the following expression. [Baud rate] = fX [Hz] 2n + 1 x 8 fX : System clock oscillation frequency n : Value determined by setting TPS000 through TPS003 as shown in the above table (2 n 8) User's Manual U11919EJ3V0UM00 137 CHAPTER 9 SERIAL INTERFACE 00 Table 9-5. Example of Relationship between System Clock and Baud Rate Baud Rate (bps) n BRGC00 Set Value fX = 5.0 MHz 1,200 2,400 4,800 9,600 19,200 38,400 76,800 8 7 6 5 4 3 2 70H 60H 50H 40H 30H 20H 10H 1.73 Error (%) fX = 4.9152 MHz 0 Caution Be sure not to select n = 1 during an operation at fX = 5.0 MHz because n = 1 exceeds the baud rate limit. (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is estimated by using the following expression. [Baud rate] = fASCK [Hz] 16 fASCK: Frequency of clock input to the ASCK pin Table 9-6. Relationship between ASCK Pin Input Frequency and Baud Rate (When BRGC00 is Set to 80H) Baud Rate (bps) 75 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 ASCK Pin Input Frequency (kHz) 1.2 2.4 4.8 9.6 19.2 38.4 76.8 153.6 307.2 500.0 614.4 138 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 9-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character bit length, parity selection, and specification of stop bit length for one data frame is carried out with asynchronous serial interface mode register 00 (ASIM00). Figure 9-7. Asynchronous Serial Interface Transmit/Receive Data Format One Data Frame Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit * Start bit...................... 1 bit * Character bits............ 7 bits/8 bits * Parity bit .................... Even parity/odd parity/0 parity/no parity * Stop bit(s).................. 1 bit/2 bits When 7 bits are selected as the number of character bits, only the low-order 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always "0". The serial transfer rate is selected by means of ASIM00 and baud rate generator control register 00 (BRGC00). If a serial data receive error is generated, the receive error contents can be determined by reading the status of asynchronous serial interface status register 00 (ASIS00). User's Manual U11919EJ3V0UM00 139 CHAPTER 9 SERIAL INTERFACE 00 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected. (i) Even parity * At transmission The parity bit is determined so that the number of bits with a value of "1" in the transmit data including parity bit may be even. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data :1 The number of bits with a value of "1" is an even number in transmit data : 0 * At reception The number of bits with a value of "1" in the receive data including parity bit is counted, and if the number is odd, a parity error is generated. (ii) Odd parity * At transmission Conversely to the even parity, the parity bit is determined so that the number of bits with a value of "1" in the transmit data including parity bit may be odd. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data :0 The number of bits with a value of "1" is an even number in transmit data : 1 * At reception The number of bits with a value of "1" in the receive data including parity bit is counted, and if the number is even, a parity error is generated. (iii) 0 parity When transmitting, the parity bit is set to "0" irrespective of the transmit data. At reception, a parity bit check is not performed. irrespective of whether the parity bit is set to "0" or "1". (iv) No parity A parity bit is not added to the transmit data. At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a parity error is not generated. Therefore, a parity error is not generated, 140 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 (c) Transmission A transmit operation is started by writing transmit data to transmit shift register 00 (TXS00). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS00 is shifted out, and when TXS00 is empty, a transmission completion interrupt (INTST) is generated. Figure 9-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 STOP TxD (Output) START INTST D0 D1 D2 D6 D7 Parity (b) Stop bit length: 2 TxD (Output) START INTST D0 D1 D2 D6 D7 Parity STOP Caution Do not rewrite to asynchronous serial interface mode register 00 (ASIM00) during a transmit operation. RESET input). It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (INTST) or the interrupt request flag (STIF00) set by INTST. If the ASIM00 register is rewritten to during transmission, subsequent transmission may not be performed (the normal state is restored by User's Manual U11919EJ3V0UM00 141 CHAPTER 9 SERIAL INTERFACE 00 (d) Reception When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is set to 1, a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM00. When the RxD pin input becomes low, the 3-bit counter starts counting, and at the time when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. If the RxD pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. When character data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends. When one frame of data has been received, the receive data in the shift register is transferred to receive buffer register 00 (RXB00), and a reception completion interrupt (INTSR) is generated. If an error is generated, the receive data in which the error was generated is still transferred to RXB00, and INTSR is generated. If the RXE00 bit is reset to 0 during the receive operation, the receive operation is stopped immediately. In this case, the contents of RXB00 and asynchronous serial interface status register 00 (ASIS00) are not changed, and INTSR is not generated. Figure 9-9. Asynchronous Serial Interface Reception Completion Interrupt Timing STOP RxD (Input) START INTSR D0 D1 D2 D6 D7 Parity Caution Be sure to read receive buffer register 00 (RXB00) even if a receive error occurs. If RXB00 is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely. 142 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 (e) Receive errors The following three errors may occur during a receive operation: 00 (ASIS00). Receive error causes are shown in Table 9-7. It is possible to determine what kind of error was generated during reception by reading the contents of ASIS00 in the reception error interrupt servicing (see Figures 9-9 and 9-10). The contents of ASIS00 are reset to 0 by reading receive buffer register 00 (RXB00) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). Table 9-7. Receive Error Causes Receive Error Parity error Framing error Overrun error Cause Transmission-time parity specification and reception data parity do not match Stop bit not detected Reception of next data is completed before data is read from receive buffer register a parity error, framing error, or overrun error. Upon data reception, an error flag is set in asynchronous serial interface status register Figure 9-10. Receive Error Timing (a) Parity error generated STOP RxD (Input) START INTSR D0 D1 D2 D6 D7 Parity (b) Framing error or overrun error generated STOP RxD (Input) START INTSR D0 D1 D2 D6 D7 Parity Cautions 1. The contents of the ASIS00 register are reset to 0 by reading receive buffer register 00 (RXB00) or receiving the next data. ASIS00 before reading RXB00. 2. Be sure to read receive buffer register 00 (RXB00) even if a receive error is generated. If RXB00 is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely. To ascertain the error contents, read User's Manual U11919EJ3V0UM00 143 CHAPTER 9 SERIAL INTERFACE 00 (3) Cautions related to UART mode (a) When bit 7 (TXE00) of asynchronous serial interface mode register 00 (ASIM00) is cleared during transmission, be sure to set transmit shift register 00 (TXS00) to FFH, then set TXE00 to 1 before executing the next transmission. (b) When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is cleared during reception, receive buffer register 00 (RXB00) and receive completion interrupt (INTSR) are as follows. RxD Pin Parity RXB00 INTSR <1> <3> <2> When RXE00 is set to 0 at a time indicated by <1>, RXB00 holds the previous data and INTSR is not generated. When RXE00 is set to 0 at a time indicated by <2>, RXB00 renews the data and INTSR is not generated. When RXE00 is set to 0 at a time indicated by <3>, RXB00 renews the data and INTSR is generated. 144 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 9.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK0), serial output (SO0), and serial input (SI0). (1) Register setting 3-wire serial I/O mode settings are performed using serial operation mode register 00 (CSIM00), asynchronous serial interface mode register 00 (ASIM00), and baud rate generator control register 00 (BRGC00). (a) Serial operation mode register 00 (CSIM00) CSIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM00 to 00H. Symbol CSIM00 <7> CSIE00 6 0 5 0 4 0 3 0 2 DIR00 1 CSCK00 0 0 Address FF72H After Reset 00H R/W R/W CSIE00 0 1 Operation stop Operation enable Operation Control in 3-Wire Serial I/O Mode DIR00 0 1 MSB LSB Start Bit Specification CSCK00 0 1 Clock Selection in 3-Wire Serial I/O Mode Input clock to SCK0 pin from external Dedicated baud rate generator output Caution Be sure to set bit 0 and bits 3 to 6 to 0. User's Manual U11919EJ3V0UM00 145 CHAPTER 9 SERIAL INTERFACE 00 (b) Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. When the 3-wire serial I/O mode is selected, 00H must be set to ASIM00. Symbol ASIM00 <7> TXE00 <6> RXE00 5 PS001 4 PS000 3 CL00 2 SL00 1 0 0 0 Address FF70H After Reset 00H R/W R/W TXE00 0 1 Transmit operation stop Transmit operation enable Transmit Operation Control RXE00 0 1 Receive operation stop Receive operation enable Receive Operation Control PS001 0 0 PS000 0 1 No parity Parity Bit Specification Always add 0 parity at transmission Parity check is not performed at reception (No parity error is generated) Odd parity Even parity 1 1 0 1 CL00 0 1 7 bits 8 bits Character Length Specification SL00 0 1 1 bit 2 bits Transmit Data Stop Bit Length Specification Cautions 1. Be sure to set bits 0 and 1 to 0. 2. Switching operating modes must be performed after serial transmit/receive operation is halted. 146 User's Manual U11919EJ3V0UM00 CHAPTER 9 SERIAL INTERFACE 00 (c) Baud rate generator control register 00 (BRGC00) BRGC00 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC00 to 00H. Symbol BRGC00 7 6 5 4 3 0 2 0 1 0 0 0 Address FF73H After Reset 00H R/W R/W TPS003 TPS002 TPS001 TPS000 TPS003 TPS002 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 TPS001 TPS000 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 fX/25 (313 kHz) (156 kHz) 3-Bit Counter Source Clock Selection n 1 2 3 4 5 6 7 8 fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) Setting prohibited Other than above Cautions 1. When writing to BRGC00 is performed during a communication operation, the baud rate generator output is disrupted and communications cannot be performed normally. Be sure not to write to BRGC00 during communication operation. 2. Be sure not to select n = 1 during an operation at fX = 5.0 MHz because n = 1 exceeds the baud rate limit. 3. When selecting an input clock from an external source, set port mode register 2 (PM2) to the input mode. Remarks 1. fX : System clock oscillation frequency 2. n : Value determined by setting TPS000 through TPS003 (1 n 8) 3. The parenthesized values apply to operation at fX = 5.0 MHz. If the internal clock is used as the serial clock for 3-wire serial I/O mode, set the TPS000 to TPS003 bits to set the frequency of the serial clock. To obtain the frequency to be set, use the following formula. When the serial clock is input from external, setting BRGC00 is not necessary. Serial clock frequency = fX [Hz] 2n + 1 fX : System clock oscillation frequency n : Value determined by setting TPS000 through TPS003 as shown in the above table (1 n 8) User's Manual U11919EJ3V0UM00 147 CHAPTER 9 SERIAL INTERFACE 00 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. transmitted/received bit by bit in synchronization with the serial clock. Transmit shift register 00 (TXS00/SIO00) and receive shift register 00 (RXS00) shift operations are performed in synchronization with the fall of the serial clock (SCK0). Then transmit data is held in the SO0 latch and output from the SO0 pin. Also, receive data input to the SI0 pin is latched in receive buffer register 00 (RXB00/SIO00) on the rise of SCK0. At the end of an 8-bit transfer, the operations of TXS00/SIO00 and RXS00 stop automatically, and the interrupt request signal (INTCSI0) is generated. Figure 9-11. 3-Wire Serial I/O Mode Timing Data is SCK0 1 2 3 4 5 6 7 8 SI0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI0 Transfer start at the falling edge of SCK0 End of Transfer (3) Transfer start Serial transfer is started by setting transfer data to transmit shift register 00 (TXS00/SIO00) when the following two conditions are satisfied. * Serial operation mode register 00 (CSIM00) bit 7 (CSIE00) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Caution If CSIE00 is set to "1" after data write to TXS00/SIO00, transfer does not start. A termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (INTCSI0). 148 User's Manual U11919EJ3V0UM00 CHAPTER 10 INTERRUPT FUNCTIONS 10.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. The non-maskable interrupt has one source of interrupt from the watchdog timer. (2) Maskable interrupt These interrupts undergo mask control. A standby release signal is generated. The maskable interrupt has four sources of external interrupts and five sources of internal interrupts. If two or more interrupts are simultaneously generated, each interrupt has a predetermined priority (priority) as shown in Table 10-1. 10.2 Interrupt Sources and Configuration There are total of ten non-maskable and maskable interrupts in the interrupt sources (see Table 10-1). User's Manual U11919EJ3V0UM00 149 CHAPTER 10 INTERRUPT FUNCTIONS Table 10-1. Interrupt Source List Interrupt Type Priority Note 1 Interrupt Source Name Trigger Internal/ External Vector Table Address 0004H Basic Configuration Note 2 Type (A) Non-maskable - INTWDT Watchdog timer overflow (watchdog timer Internal mode 1 selected) Watchdog timer overflow (interval timer mode selected) Pin input edge detection External Maskable 0 INTWDT (B) 1 2 3 4 INTP0 INTP1 INTP2 INTSR INTCSI0 0006H 0008H 000AH (C) End of serial interface 00 UART reception Internal End of serial interface 00 3-wire transfer End of serial interface 00 UART transmission Generation of 8-bit timer/event counter 00 match signal Generation of 16-bit timer 20 match signal Key return signal detection External 000CH (B) 5 INTST 000EH 6 INTTM0 0010H 7 INTTM2 0014H 8 INTKR 002AH (C) Notes 1. Priorities are intended for the priority for two or more simultaneously generated maskable interrupts. 0 is the highest priority and 8 is the lowest priority. 2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 10-1. 150 User's Manual U11919EJ3V0UM00 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal Bus Interrupt Request Vector Table Address Generator Standby Release Signal (B) Internal maskable interrupt Internal Bus MK IE Interrupt Request IF Vector Table Address Generator Standby Release Signal (C) External maskable interrupt Internal Bus INTM0, KRM00 MK IE Interrupt Request Edge Detector IF Vector Table Address Generator Standby Release Signal INTM0 : External interrupt mode register 0 KRM00 : Key return mode register 00 IF IE MK : Interrupt request flag : Interrupt enable flag : Interrupt mask flag User's Manual U11919EJ3V0UM00 151 CHAPTER 10 INTERRUPT FUNCTIONS 10.3 Interrupt Function Control Registers The following five registers are used to control the interrupt functions. * Interrupt request flag registers (IF0 and IF1) * Interrupt mask flag registers (MK0 and MK1) * External interrupt mode register 0 (INTM0) * Program status word (PSW) * Key return mode register 00 (KRM00) Table 10-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. Table 10-2. Flags Corresponding to Interrupt Request Signal Name Interrupt Request Signal Name INTWDT INTP0 INTP1 INTP2 INTSR/INTCSI0 INTST INTTM0 INTTM2 INTKR TMIF4 PIF0 PIF1 PIF2 SRIF00 STIF00 TMIF00 TMIF20 KRIF00 Interrupt Request Flag TMMK4 PMK0 PMK1 PMK2 SRMK00 STMK00 TMMK00 TMMK20 KRMK00 Interrupt Mask Flag 152 User's Manual U11919EJ3V0UM00 CHAPTER 10 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0 and IF1) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 upon acknowledgement of an interrupt request, upon RESET input, or when an instruction is executed. IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears IF0 and IF1 to 00H. Figure 10-2. Interrupt Request Flag Register Format Symbol IF0 7 0 <6> TMIF00 <5> STIF00 <4> SRIF00 <3> PIF2 <2> PIF1 <1> PIF0 <0> TMIF4 Address FFE0H After Reset 00H R/W R/W <7> IF1 TMIF20 6 0 5 0 4 0 3 0 2 0 1 0 <0> KRIF00 FFE1H 00H R/W xxIFx 0 1 No interrupt request signal is generated Interrupt Request Flag Interrupt request signal is generated; Interrupt request state Cautions 1. Be sure to clear bit 7 of IF0 and bits 1 to 6 of IF1 to 0. 2. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If the watchdog timer mode 1 or 2 is used, set TMIF4 flag to 0. 3. Because port 3 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the output mode. User's Manual U11919EJ3V0UM00 153 CHAPTER 10 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 to FFH. Figure 10-3. Interrupt Mask Flag Register Format Symbol MK0 7 1 <6> <5> <4> <3> PMK2 <2> PMK1 <1> PMK0 <0> TMMK4 Address FFE4H After Reset FFH R/W R/W TMMK00 STMK00 SRMK00 <7> MK1 TMMK20 6 1 5 1 4 1 3 1 2 1 1 1 <0> KRMK00 FFE5H FFH R/W xxMKx 0 1 Interrupt servicing enabled Interrupt servicing disabled Interrupt Servicing Control Cautions 1. Be sure to set bit 7 of MK0 and bits 1 to 6 of MK1 to 1. 2. IF the TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1 or 2, its value becomes undefined. 3. Because port 3 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the output mode. 154 User's Manual U11919EJ3V0UM00 CHAPTER 10 INTERRUPT FUNCTIONS (3) External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 10-4. External Interrupt Mode Register 0 Format ' Symbol INTM0 7 ES21 6 ES20 5 ES11 4 ES10 3 ES01 2 ES00 1 0 0 0 Address FFECH After Reset 00H R/W R/W ES21 0 0 1 1 ES20 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTP2 Valid Edge Selection ES11 0 0 1 1 ES10 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTP1 Valid Edge Selection ES01 0 0 1 1 ES00 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTP0 Valid Edge Selection Cautions 1. Be sure to set bits 0 and 1 to 0. 2. Before setting INTM0 register, be sure to set the corresponding interrupt mask flag xxMKx = 1) to disable interrupts. (xx xx x interrupts. After setting INTM0 register, clear the interrupt xxIFx xxMKx = 0) to enable request flag (xx x = 0), then clear the interrupt mask flag (xx xx xx x User's Manual U11919EJ3V0UM00 155 CHAPTER 10 INTERRUPT FUNCTIONS (4) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status of the interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped. Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI and DI). POP PSW instructions. RESET input sets PSW to 02H. Figure 10-5. Program Status Word Configuration When a vectored interrupt request is acknowledged, PSW is automatically saved into a stack, and the IE flag is reset to 0. It is restored from the stack with the RETI and Symbol PSW 7 IE 6 Z 5 0 4 AC 3 0 2 0 1 1 0 CY After Reset 02H Used when normal instruction is executed IE 0 1 Disable Enable Interrupt Acknowledge Enable/Disable 156 User's Manual U11919EJ3V0UM00 CHAPTER 10 INTERRUPT FUNCTIONS (5) Key return mode register 00 (KRM00) KRM00 is used to specify the pin at which a key return signal is detected. KRM00 is set with a 1-bit or 8-bit memory manipulation instruction. Bit 0 (KRM000) is set for the four pins from KR0/P40 to KR3/P43. Bits 4 to 7 (KRM004 to KRM007) are set in 1-bit units for pins KR4/P44 to KR7/P47, respectively. RESET input clears KRM00 to 00H. Figure 10-6. Key Return Mode Register 00 Format Symbol KRM00 7 6 5 4 3 0 2 0 1 0 0 KRM000 Address FFF5H After Reset 00H R/W R/W KRM007 KRM006 KRM005 KRM004 KRM00n 0 1 Undetected Key Return Signal Detection Selection Detected (at the falling edge of port 4) Cautions 1. Be sure to set bits 1 to 3 to 0. 2. When KRM00 is set to 1, the corresponding pin is connected to a pull-up resistor unless it is in output mode. In output mode, the pull-up resistor is not connected. 3. Before setting KRM00, set bit 0 of MK1 (KRMK00 = 1) to disable interrupts. To enable interrupts, clear bit 0 of IF1 (KRIF00 = 0), then bit 0 of MK1 (KRMK00 = 0). Remark n = 0, 4 to 7 Figure 10-7. Falling Edge Detection Circuit Key Return Mode Register (KRM00) Note P40/KR0 P41/KR1 P42/KR2 P43/KR3 P44/KR4 P45/KR5 P46/KR6 P47/KR7 KRMK00 Standby Release Signal Selector Falling Edge Detection Circuit KRIF00 Set Signal Note Selector used to select the pin to be used for falling edge input User's Manual U11919EJ3V0UM00 157 CHAPTER 10 INTERRUPT FUNCTIONS 10.4 Interrupt Processing Operation 10.4.1 Non-maskable interrupt request acceptance operation The non-maskable interrupt request is unconditionally accepted even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches. Figure 10-8 shows the flowchart from non-maskable interrupt request generation to acceptance. Figure 10-9 shows the timing of non-maskable interrupt request acceptance. Figure 10-10 shows the acceptance operation if multiple non-maskable interrupts are generated. Caution During a non-maskable interrupt service program execution, do not input another nonmaskable interrupt request; if it is input, the service program will be interrupted and the new interrupt request will be acknowledged. 158 User's Manual U11919EJ3V0UM00 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-8. Flowchart from Non-Maskable Interrupt Request Generation to Acceptance Start WDTM4 = 1 (watchdog timer mode is selected) Yes No Interval Timer WDT overflows Yes WDTM3 = 0 No (non-maskable interrupt is selected) Yes Interrupt request is generated Interrupt processing is started No Reset Processing WDTM : Watchdog timer mode register WDT : Watchdog timer Figure 10-9. Non-Maskable Interrupt Request Acceptance Timing CPU Processing Instruction Instruction Saving PSW and PC, and jump to interrupt processing Interrupt Processing Program TMIF4 User's Manual U11919EJ3V0UM00 159 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-10. Accepting Non-Maskable Interrupt Request Main Routine First Interrupt Processing NMI Request (first) NMI Request (second) Second Interrupt Processing 160 User's Manual U11919EJ3V0UM00 CHAPTER 10 INTERRUPT FUNCTIONS 10.4.2 Maskable interrupt request acceptance operation A maskable interrupt request can be accepted when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is accepted in the interrupt enabled status (when the IE flag is set to 1). The time required to start the interrupt processing after a maskable interrupt request has been generated is shown in Table 10-3. See Figures 10-12 and 10-13 for the interrupt request acceptance timing. Table 10-3. Time from Generation of Maskable Interrupt Request to Processing Minimum Time 9 clocks Maximum Time 19 clocks Note Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instruction. Remark 1 clock: 1 (fCPU: CPU clock) fCPU When two or more maskable interrupt requests are generated at the same time, they are accepted starting from the interrupt request assigned the highest priority. A pended interrupt is accepted when the status where it can be accepted is set. Figure 10-11 shows the algorithm of accepting interrupt requests. When a maskable interrupt request is accepted, the contents of PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To return from interrupt processing, use the RETI instruction. User's Manual U11919EJ3V0UM00 161 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-11. Interrupt Request Acceptance Program Algorithm Start No xxIF = 1 ? Yes (Interrupt request generated) No xxMK = 0 ? Yes Interrupt Request Pending No IE = 1 ? Yes Vectored Interrupt Processing Interrupt Request Pending xxIF IE : Interrupt request flag : Flag to control maskable interrupt request acceptance (1 = enable, 0 = disable) xxMK : Interrupt mask flag 162 User's Manual U11919EJ3V0UM00 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-12. Interrupt Request Acceptance Timing (Example of MOV A,r) 8 Clocks Clock CPU MOV A,r Saving PSW and PC, jump to interrupt processing Interrupt Processing Program Interrupt If an interrupt request flag (xxIF) is set before an instruction clock n (n = 4 to 10) under execution becomes n - 1, the interrupt is accepted after the instruction under execution completes. Figure 10-12 shows an example of the interrupt request acceptance timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acceptance processing is performed after the MOV A,r instruction is completed. Figure 10-13. Interrupt Request Acceptance Timing (When Interrupt Request Flag Generates at the Last Clock during Instruction Execution) 8 Clocks Clock CPU NOP MOV A,r Saving PSW and PC, jump to interrupt processing Interrupt Processing Program Interrupt If an interrupt request flag (xxIF) is set at the last clock of the instruction, the interrupt acceptance processing starts after the next instruction is executed. Figure 10-13 shows an example of the interrupt acceptance timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is executed, and then the interrupt acceptance processing is performed. Caution Interrupt requests are reserved while the interrupt request flag register (IF0 or IF1) or the interrupt mask flag register (MK0 or MK1) is being accessed. 10.4.3 Nesting processing Nesting processing in which another interrupt is accepted while an interrupt is processed can be processed by priority. When two or more interrupts are generated at once, interrupt processing is performed according to the priority assigned to each interrupt request in advance (see Table 10-1). User's Manual U11919EJ3V0UM00 163 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-14. Example of Nesting Example 1. Nesting is accepted Main Processing INTxx Processing INTyy Processing EI IE = 0 EI IE = 0 INTxx INTyy RETI RETI During interrupt INTxx servicing, interrupt request INTyy is accepted, and a nesting is generated. set. Example 2. A nesting is not generated because interrupts are not enabled Main Processing INTxx Processing INTyy Processing An EI instruction is issued before each interrupt request acceptance, and the interrupt request acceptance enable state is EI IE = 0 INTyy RETI INTyy is kept pending INTxx IE = 0 RETI Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request INTyy is not accepted, and a nesting is not generated. The INTyy request is reserved and accepted after the INTxx processing is performed. IE = 0: Interrupt request acceptance disabled 164 User's Manual U11919EJ3V0UM00 CHAPTER 10 INTERRUPT FUNCTIONS 10.4.4 Interrupt request reserve Some instructions may reserve the acceptance of an interrupt request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution. The following shows such instructions (interrupt request reserve instruction). * Manipulation instruction for the interrupt request flag registers 0 and 1 (IF0 and IF1) * Manipulation instruction for the interrupt mask flag registers 0 and 1 (MK0 and MK1) User's Manual U11919EJ3V0UM00 165 [MEMO] 166 User's Manual U11919EJ3V0UM00 CHAPTER 11 STANDBY FUNCTION 11.1 Standby Function and Configuration 11.1.1 Standby function The standby function is to reduce the power consumption of the system and can be effected in the following two modes: (1) HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU. The system clock oscillation circuit continues oscillating. This mode does not reduce the current drain as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) STOP mode This mode is set when the STOP instruction is executed. this mode. Data memory can be retained at low voltages (VDD = 1.8 V min.). Therefore, this mode is useful for retaining the contents of the data memory at an extremely low current. The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent operation. However, some time is required until the system clock oscillation circuit settles after the STOP mode has been released. If processing must be resumed immediately by using an interrupt request, therefore, use the HALT mode. In both modes, the previous contents of the registers, flags, and data memory before setting standby mode are all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained. Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then execute the STOP instruction. The STOP mode stops the system clock oscillation circuit and stops the entire system. The current drain of the CPU can be substantially reduced in User's Manual U11919EJ3V0UM00 167 CHAPTER 11 STANDBY FUNCTION 11.1.2 Standby function control register The wait time after the STOP mode is released upon interrupt request until the oscillation settles is controlled with the oscillation settling time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, the oscillation settling time after RESET input is 215/fX, instead of 2 /fX. Figure 11-1. Oscillation Settling Time Select Register Format Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 Address FFFAH After Reset 04H R/W R/W 17 OSTS2 0 0 1 OSTS1 0 1 0 OSTS0 0 0 0 212/fX (819 Oscillation Settling Time Selection s) ms) 215/fX (6.55 217/fX (26.2 ms) Setting prohibited Other than above Caution The wait time after the STOP mode is released does not include the time from STOP mode release to clock oscillation start ("a" in the figure below), regardless of release by RESET input or by interrupt generation. STOP Mode Release X1 Pin Voltage Waveform a VSS Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. 168 User's Manual U11919EJ3V0UM00 CHAPTER 11 STANDBY FUNCTION 11.2 Operation of Standby Function 11.2.1 HALT mode (1) HALT mode HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 11-1. HALT Mode Operating Status Item Clock generation circuit HALT Mode Operating Status System clock oscillation enabled Clock supply to CPU stopped Operation stopped Retains the status before setting the HALT mode Operation enabled Operation enabled Operation enabled Operation enabled Operation enabled Only the pin set to key return mode is enabled CPU Port (Output latch) 16-bit timer 8-bit timer/event counter Watchdog timer Serial interface External interrupt Key return User's Manual U11919EJ3V0UM00 169 CHAPTER 11 STANDBY FUNCTION (2) Releasing HALT mode The HALT mode can be released by the following three types of sources: (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is enabled to be accepted, vectored interrupt processing is performed. If the interrupt is disabled, the instruction at the next address is executed. Figure 11-2. Releasing HALT Mode by Interrupt HALT Instruction Standby Release Signal Operation Mode Wait HALT Mode Wait Oscillation Operation Mode Clock Remarks 1. The broken line indicates the case where the interrupt request that has released the standby mode is accepted. 2. The wait time is as follows: * When vectored interrupt processing is performed : 9 to 10 clocks * When vectored interrupt processing is not performed : 1 to 2 clocks (b) Releasing by non-maskable interrupt request The HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed. 170 User's Manual U11919EJ3V0UM00 CHAPTER 11 STANDBY FUNCTION (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 11-3. Releasing HALT Mode by RESET Input HALT Instruction RESET Signal Operation Mode Reset Period Oscillation Stop Wait (215/fX : 6.55 ms) HALT Mode Oscillation Oscillation Settling Wait Status Oscillation Operation Mode Clock Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. Table 11-2. Operation after Release of HALT Mode Releasing Source Maskable interrupt request MKxx 0 0 1 Non-maskable interrupt request RESET input - - IE 0 1 x x - Operation Executes next address instruction Executes interrupt processing Retains HALT mode Executes interrupt processing Reset processing x: Don't care User's Manual U11919EJ3V0UM00 171 CHAPTER 11 STANDBY FUNCTION 11.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the HALT mode is set immediately after the STOP instruction has been executed, the wait time set by the oscillation settling time select register (OSTS) elapses, and then operation mode is set. The operation status in the STOP mode is shown in the following table. Table 11-3. STOP Mode Operating Status Item Clock generation circuit CPU Port (Output latch) 16-bit timer 8-bit timer/event counter Watchdog timer Serial interface External interrupt Key return STOP Mode Operation Status Stops system clock oscillation Stops operation Retains the status before setting the STOP mode Stops operation Operation is enabled only when TI0 is selected as the count clock Stops operation Enables operation only when input clock from external is selected as serial clock Operation enabled Only the pin set to key return mode is enabled 172 User's Manual U11919EJ3V0UM00 CHAPTER 11 STANDBY FUNCTION (2) Releasing STOP mode The STOP mode can be released by the following two types of sources: (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is enabled to be accepted, vectored interrupt processing is performed, after the oscillation settling time has elapsed. If the interrupt acceptance is disabled, the instruction at the next address is executed. Figure 11-4. Releasing STOP Mode by Interrupt Wait ( Set Time by OSTS) STOP Instruction Standby Release Signal Operation Mode Oscillation STOP Mode Oscillation Stop Oscillation Settling Wait Status Oscillation Operation Mode Clock Remark The broken line indicates the case where the interrupt request that has released the standby mode is accepted. User's Manual U11919EJ3V0UM00 173 CHAPTER 11 STANDBY FUNCTION (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation settling time has elapsed. Figure 11-5. Releasing STOP Mode by RESET Input STOP Instruction RESET Signal Operation Mode Oscillation Reset Period Oscillation Settling Wait Status Oscillation Operation Mode Wait (215/fX : 6.55 ms) STOP Mode Oscillation Stop Clock Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. Table 11-4. Operation after Release of STOP Mode Releasing Source Maskable interrupt request MKxx 0 0 1 RESET input - IE 0 1 x - Operation Executes next address instruction Executes interrupt processing Retains STOP mode Reset processing x: Don't care 174 User's Manual U11919EJ3V0UM00 CHAPTER 12 RESET FUNCTION The following two operations are available to generate reset signals. (1) (2) External reset input with RESET pin Internal reset by program run-away time detected with watchdog timer In both cases, program execution starts at the External and internal reset have no functional differences. address at 0000H and 0001H by reset signal input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in Table 12-1. Each pin has a high impedance during reset input or during oscillation settling time just after reset clear. When a high level is input to the RESET pin, the reset is cleared and program execution is started after the oscillation settling time (215/fX) has elapsed. The reset applied by the watchdog timer overflow is automatically cleared after reset, and program execution is started after the oscillation settling time (215/fX) has elapsed (see Figures 12-2 through 12-4). Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pins become high impedance. Figure 12-1. Block Diagram of Reset Function RESET Reset Control Circuit Reset Signal Count Clock Watchdog Timer Stop Overflow Interrupt Function User's Manual U11919EJ3V0UM00 175 CHAPTER 12 RESET FUNCTION Figure 12-2. Reset Timing by RESET Input X1 Normal Operation Reset Period (oscillation stops) Oscillation Settling Time Wait Normal Operation (reset processing) RESET Internal Reset Signal Delay Delay Hi-Z Port Pin Figure 12-3. Reset Timing by Overflow in Watchdog Timer X1 Normal Operation Overflow in Watchdog Timer Reset Period (oscillation continues) Oscillation Settling Time Wait Normal Operation (reset processing) Internal Reset Signal Port Pin Hi-Z Figure 12-4. Reset Timing by RESET Input in STOP Mode X1 STOP Instruction Execution Stop Status (oscillation Normal Operation stops) RESET Reset Period (oscillation stops) Oscillation Settling Time Wait Normal Operation (reset processing) Internal Reset Signal Delay Port Pin Delay Hi-Z 176 User's Manual U11919EJ3V0UM00 CHAPTER 12 RESET FUNCTION Table 12-1. Hardware Status after Reset Hardware Program counter (PC) Note 1 State after Reset The contents of reset vector tables (0000H and 0001H) are set. Undefined 02H Stack pointer (SP) Program status word (PSW) RAM Data memory General-purpose register Ports (P0 to P5) (Output latch) Port mode registers (PM0 to PM5) Pull-up resistor option register (PUO) Processor clock control register (PCC) Oscillation settling time select register (OSTS) 16-bit timer Timer counter (TM20) Compare register (CR20) Mode control register (TMC20) Capture register (TCP20) 8-bit timer/event counter Timer counter (TM00) Compare register (CR00) Mode control register (TMC00) Watchdog timer Timer clock select register (TCL2) Mode register (WDTM) Serial interface Mode register (CSIM00) Asynchronous serial interface mode register (ASIM00) Asynchronous serial interface status register (ASIS00) Baud rate generator control register (BRGC00) Transmit shift register (TXS00) Receive buffer register (RXB00) Interrupt Request flag registers (IF0, IF1) Mask flag registers (MK0, MK1) External interrupt mode register (INTM0) Key return mode register (KRM00) Undefined Note 2 Undefined 00H FFH 00H 02H 04H 0000H FFFFH 00H Note 2 Undefined 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH Undefined 00H FFH 00H 00H Notes 1. During reset input and oscillation settling time wait, only the PC contents among the hardware statuses become undefined. All other hardware remains unchanged after reset. 2. In post-reset values are retained in the standby mode. User's Manual U11919EJ3V0UM00 177 [MEMO] 178 User's Manual U11919EJ3V0UM00 CHAPTER 13 PD78F9026A The PD78F9026A is a version with an internal ROM of the mask ROM models replaced with a flash memory. The differences between the PD78F9026A and the mask ROM models are shown in Table 13-1. Table 13-1. Differences between PD78F9026A and Mask ROM Models Item Flash Memory Model Mask ROM Model PD78F9026A Internal memory ROM 16 Kbytes (flash memory) 512 bytes PD789022 4 Kbytes PD789024 8 Kbytes PD789025 12 Kbytes PD789026 16 Kbytes Internal highspeed RAM IC pin VPP pin Electric characteristics 256 bytes 512 bytes Not provided Provided Refer to Data Sheet. Provided Not provided Caution The flash memory and masked ROM products have different noise immunity and noise radiation characteristics. Do not use ES products for evaluation when considering switching from flash memory products to those using masked ROM upon the transition from preproduction to mass-production. CS products (masked ROM products) should be used in this case. User's Manual U11919EJ3V0UM00 179 CHAPTER 13 PD78F9026A 13.1 Flash Memory Programming The program memory provided to the PD78F9026A is flash memory. The flash memory can be written on-board, i.e., with the PD78F9026A mounted on the target system. To do so, connect a dedicated flash writer (Flashpro III (Part number: FL-PR3, PG-FP3)) to the host machine and target system. Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd. 13.1.1 Selecting communication mode The flash memory is written by using Flashpro III and by means of serial communication. Select a communication mode from those listed in Table 13-2. To select a communication mode, the format shown in Figure 13-1 is used. Each communication mode is selected depending on the number of VPP pulses shown in Table 13-2. Table 13-2. Communication Modes Communication Mode 3-wire serial I/O Pins Used SCK0/ASCK/P20 SO0/TxD/P21 SI0/RxD/P22 TxD/SO0/P21 RxD/SI0/P22 Note Number of VPP Pulses 0 UART 8 Pseudo 3-wire mode P00 (Serial clock input) P01 (Serial data output) P02 (Serial data input) P40/KR0 (serial clock input) P41/KR1 (serial data output) P42/KR2 (serial data input) 12 13 Note Serial transfer is performed by controlling the port with software. Caution Be sure to select a communication mode by the number of VPP pulses shown in Table 13-2. Figure 13-1. Communication Mode Selection Format 10 V VPP VDD VSS 1 2 n VDD RESET VSS 180 User's Manual U11919EJ3V0UM00 CHAPTER 13 PD78F9026A 13.1.2 Flash memory programming function An operation such as writing the flash memory is performed when a command or data is transmitted/received in the selected communication mode. The major flash memory programming functions are listed in Table 13-3. Table 13-3. Major Flash Memory Programming Functions Function Batch erase Batch blank check Data write Erases all memory contents. Checks erased status of entire memory. Writes data to flash memory starting from write start address and based on number of data (bytes) to be written. Compares all contents of memory with input data Description Batch verify 13.1.3 Connection Example of Flashpro III Connection with Flashpro III differs depending on the communication mode (3-wire serial I/O, UART, or pseudo 3-wire mode). Figures 13-2 through 13-4 show the connection in the respective modes. Figure 13-2. Connection Example of Flashpro III in 3-Wire Serial I/O Mode Flashpro III VPPnNote VDD RESET SCK SO SI GND VPP VDD0, VDD1 RESET SCK0 SI0 SO0 VSS0, VSS1 PD78F9026A Note n = 1, 2 User's Manual U11919EJ3V0UM00 181 CHAPTER 13 PD78F9026A Figure 13-3. Connection Example of Flashpro III in UART Mode Flashpro III VPPnNote VDD RESET SO SI GND PD78F9026A VPP VDD0, VDD1 RESET RxD TxD VSS0, VSS1 Note n = 1, 2 Figure 13-4. Connection Example of Flashpro III in Pseudo 3-Wire Mode (When using P0) Flashpro III VPPnNote VDD RESET SCK SO SI GND VPP VDD0, VDD1 RESET P00 (serial clock) P02 (serial input) P01 (serial output) VSS0, VSS1 PD78F9026A Note n = 1, 2 182 User's Manual U11919EJ3V0UM00 CHAPTER 13 PD78F9026A 13.1.4 Setting example when using Flashpro III (PG-FP3) When writing data to flash memory by using Flashpro III (PG-FP3), set as follows. <1> Load the parameter file. <2> Select a serial mode and serial clock by using the type command. <3> An example of setting with PG-FP3 is shown below. Table 13-4. Setting Example When Using PG-FP3 Communication Mode 3-wire serial I/O COMM PORT CPU CLK On Target Board SIO CLK In Flashpro SIO CLK UART COMM PORT CPU CLK On Target Board UART BPS Pseudo 3-wire mode COMM PORT CPU CLK On Target Board SIO CLK In Flashpro SIO CLK COMM PORT CPU CLK On Target Board SIO CLK In Flashpro SIO CLK Setting Example with PG-FP3 SIO-ch0 On Target Board In Flashpro 4.1943 MHz 1.0 MHz 4.0 MHz 1.0 MHz UART-ch0 On Target Board 4.1943 MHz 9,600 bps Port A On Target Board In Flashpro 4.1943 MHz 1.0 MHz 4.0 MHz 1.0 MHz Port B On Target Board In Flashpro 4.1943 MHz 1 kHz 4.0 MHz 1 kHz 13 Note 2 Number of VPP Pulses 0 Note 1 8 12 Notes 1. This is the number of VPP pulses supplied from Flashpro III during initialization of serial communication. The pin used for the communication is decided depending on this number. 2. Select from 9,600 bps, 19,200 bps, 38,400 bps, or 76,800 bps. Remark COMM PORT : Selection of serial port. SIO CLK : Selection of serial clock frequency. CPU CLK : Selection of source of CPU clock to be input. User's Manual U11919EJ3V0UM00 183 [MEMO] 184 User's Manual U11919EJ3V0UM00 CHAPTER 14 INSTRUCTION SET This chapter lists the instruction set of the PD789026 Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series User's Manual Instruction (U11047E). 14.1 Operation 14.1.1 Operand identifiers and writing methods Operands are written in "Operand" column of each instruction in accordance with the writing method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more writing methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are written as they are. Each symbol has the following meaning. * # : Immediate data specification *! : Absolute address specification * $ : Relative address specification * [ ] : Indirect address specification In the case of immediate data, write an appropriate numeric value or a label. When using a label, be sure to write the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either functional names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used. Table 14-1. Operand Identifiers and Writing Methods Identifier r rp sfr saddr saddrp addr16 addr5 word byte bit Writing Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbol FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even addresses only) 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) 0040H to 007FH Immediate data or labels (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label Remark See Table 3-4 for symbols of special function registers. User's Manual U11919EJ3V0UM00 185 CHAPTER 14 INSTRUCTION SET 14.1.2 Description of "Operation" column A X B C D E H L AX BC DE HL PC SP PSW CY AC Z IE NMIS () xH, xL jdisp8 : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair : Program counter : Stack pointer : Program status word : Carry flag : Auxiliary carry flag : Zero flag : Interrupt request enable flag : Flag indicating non-maskable interrupt servicing in progress : Memory contents indicated by address or register contents in parentheses : High-order 8 bits and low-order 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) : Inverted data : Signed 8-bit data (displacement value) addr16 : 16-bit immediate data or label 14.1.3 Description of "Flag" column (Blank) : Unchanged 0 1 x R : Cleared to 0 : Set to 1 : Set/cleared according to the result : Previously saved value is restored 186 User's Manual U11919EJ3V0UM00 CHAPTER 14 INSTRUCTION SET 14.2 Operation List Mnemonic Operands Byte Clock Operation Z MOV r,#byte saddr,#byte sfr,#byte A,r r,A Note 1 Flag AC CY 3 3 3 2 2 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 2 2 2 1 1 2 6 6 6 4 4 4 4 4 4 8 8 6 4 4 6 6 6 6 6 6 4 6 6 6 8 8 8 r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL+byte) (HL+byte) A AX Ar A (saddr) A sfr A (DE) A (HL) A (HL+byte) x x x x x x Note 1 A,saddr saddr,A A,sfr sfr,A A,!addr16 !addr16,A PSW,#byte A,PSW PSW,A A,[DE] [DE],A A,[HL] [HL],A A,[HL+byte] [HL+byte],A XCH A,X A,r Note 2 A,saddr A,sfr A,[DE] A,[HL] A,[HL+byte] Notes 1. Except r = A. 2. Except r = A, X. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by processor clock control register (PCC). User's Manual U11919EJ3V0UM00 187 CHAPTER 14 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Z Flag AC CY MOVW rp,#word AX,saddrp saddrp,AX AX,rp rp,AX Note 3 2 2 1 1 1 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 6 6 8 4 4 8 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 rp word AX (saddrp) (saddrp) AX AX rp rp AX AX rp A,CY A + byte (saddr),CY (saddr) + byte A,CY A + r A,CY A + (saddr) A,CY A + (addr16) A,CY A + (HL) A,CY A + (HL+byte) A,CY A + byte + CY (saddr),CY (saddr) + byte + CY A,CY A + r + CY A,CY A + (saddr) + CY A,CY A + (addr16) + CY A,CY A + (HL) + CY A,CY A + (HL+byte) + CY A,CY A - byte (saddr),CY (saddr) - byte A,CY A - r A,CY A - (saddr) A,CY A - (addr16) A,CY A - (HL) A,CY A - (HL+byte) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Note XCHW ADD AX,rp Note A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] ADDC A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] SUB A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by processor clock control register (PCC). 188 User's Manual U11919EJ3V0UM00 CHAPTER 14 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Z Flag AC CY x x x x x x x x x x x x x x SUBC A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 A,CY A - byte - CY (saddr),CY (saddr) - byte - CY A,CY A - r - CY A,CY A - (saddr) - CY A,CY A - (addr16) - CY A,CY A - (HL) - CY A,CY A - (HL+byte) - CY A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL+byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL+byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL+byte) x x x x x x x x x x x x x x x x x x x x x x x x x x x x AND A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] OR A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] XOR A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by processor clock control register (PCC). User's Manual U11919EJ3V0UM00 189 CHAPTER 14 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Z Flag AC CY x x x x x x x x x x x x x x x x x x x x x x x x CMP A,#byte saddr,#byte A,r A,saddr A,!addr16 A,[HL] A,[HL+byte] 2 3 2 2 3 1 2 3 3 3 2 2 2 2 1 1 1 1 1 1 3 3 2 3 2 3 3 2 3 2 1 1 1 4 6 4 4 8 6 6 6 6 6 4 4 4 4 4 4 2 2 2 2 6 6 4 6 10 6 6 4 6 10 2 2 2 A - byte (saddr) - byte A-r A - (saddr) A - (addr16) A - (HL) A - (HL+byte) AX,CY AX + word AX,CY AX - word AX - word rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY,A7 A0,Am-1 Am) x 1 (CY,A0 A7,Am+1 Am) x 1 (CY A0,A7 CY,Am-1 Am) x 1 (CY A7,A0 CY,Am+1 Am) x 1 (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (HL).bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY x x x x x x x x x x x x x x ADDW SUBW CMPW INC AX,#word AX,#word AX,#word r saddr DEC r saddr INCW DECW ROR ROL RORC ROLC SET1 rp rp A,1 A,1 A,1 A,1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x x x x x x CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x x SET1 CLR1 NOT1 CY CY CY 1 0 x Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by processor clock control register (PCC). 190 User's Manual U11919EJ3V0UM00 CHAPTER 14 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Z Flag AC CY CALL !addr16 3 6 (SP-1) (PC+3)H, (SP-2) (PC+3)L, PC addr16, SP SP - 2 (SP-1) (PC+1)H, (SP-2) (PC+1)L, PCH (00000000,addr5+1), PCL (00000000,addr5), SP SP - 2 PCH (SP+1), PCL (SP), SP SP + 2 PCH (SP+1), PCL (SP), PSW (SP+2), SP SP + 3, NMIS 0 (SP-1) PSW, SP SP - 1 (SP-1) rpH, (SP-2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP+1), rpL (SP), SP SP + 2 SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 4 + jdisp8 if PSW.bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW.bit = 0 B B - 1, then PC PC + 2 + jdisp8 if B 0 C C - 1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode R R R R R R CALLT [addr5] 1 8 RET RETI 1 1 6 8 PUSH PSW rp 1 1 1 1 2 2 3 2 1 2 2 2 2 4 4 3 4 4 4 3 4 2 2 3 2 4 4 6 8 6 6 6 6 6 6 6 6 10 10 8 10 10 10 8 10 6 6 8 POP PSW rp MOVW SP,AX AX,SP BR !addr16 $addr16 AX BC BNC BZ BNZ BT $saddr16 $saddr16 $saddr16 $saddr16 saddr.bit,$addr16 sfr.bit,$addr16 A.bit,$addr16 PSW.bit,$addr16 BF saddr.bit,$addr16 sfr.bit,$addr16 A.bit,$addr16 PSW.bit,$addr16 DBNZ B,$addr16 C,$addr16 saddr,$addr16 NOP EI DI HALT STOP 1 3 3 1 1 2 6 6 2 2 Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by processor clock control register (PCC). User's Manual U11919EJ3V0UM00 191 CHAPTER 14 INSTRUCTION SET 14.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV Note #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL+byte] $addr16 1 None MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC XCH ADD ADDC SUB SUBC AND OR XOR CMP INC DEC B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV MOV MOV DBNZ DBNZ INC DEC PUSH POP [DE] [HL] [HL+byte] MOV MOV MOV Note Except r = A. 192 User's Manual U11919EJ3V0UM00 CHAPTER 14 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word AX rp Note saddrp SP None 1st Operand AX ADDW SUBW CMPW MOVW MOVW Note MOVW XCHW MOVW MOVW rp INCW DECW PUSH POP saddrp SP MOVW MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand 1st Operand A.bit BT BF BT BF BT BF BT BF SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 $addr16 None sfr.bit saddr.bit PSW.bit [HL].bit CY User's Manual U11919EJ3V0UM00 193 CHAPTER 14 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand 1st Operand Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ DBNZ AX !addr16 [addr5] $addr16 Compound instructions (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP 194 User's Manual U11919EJ3V0UM00 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the PD789026 Subseries. Figure A-1 shows development tools. * Compatibility with PC98-NX series Unless stated otherwise, products which are supported for the IBM PC/ATTM compatibles can also be used with the PC98-NX series. When using the PC98-NX series, therefore, refer to the explanations for the IBM PC/AT compatibles. * Windows Unless stated otherwise, "Windows" refers to the following operating systems. * Windows 3.1 * Windows 95 TM * Windows NT Ver. 4.0 User's Manual U11919EJ3V0UM00 195 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Language Processing Software * Assembler package * C compiler package * System simulator * Device file * C compiler source file * Integrated debugger Embedded Software * OS Host Machine (PC or EWS) Interface adapter Flash Memory Writing Environment In-Circuit Emulator Flash writer Emulation board Flash memory writing adapter Power-Supply Unit Flash memory Emulation Probe Conversion socket Target System 196 User's Manual U11919EJ3V0UM00 APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K0S Assembler package Program that converts program written in mnemonic into object code that can be executed by microcontroller. In addition, automatic functions to generate symbol table and optimize branch instructions are also provided. Used in combination with optional device file (DF789026). Note File containing the information inherent to the device. Used in combination with other optional tools (RA78K0S, CC78K0S, SM78K0S). Part number: SxxxxDF789026 CC78K0S-L C compiler source file Source file of functions constituting object library included in C compiler package. Necessary for changing object library included in C compiler package according to customer's specifications. Since this is the source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0S-L Note DF789026 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S. Remark xxxx in the part number differs depending on the host machines and operating systems to be used. SxxxxRA78K0S SxxxxCC78K0S SxxxxDF789026 SxxxxCC78K0S-L xxxx AA13 AB13 3P16 3K13 3K15 3R13 NEWS (RISC) TM Host Machine PC-9800 series IBM PC/AT compatibles HP9000 series 700 SPARCstation TM TM OS Japanese Windows Japanese Windows TM Note Supply Media 3.5" 2HD FD 3.5" 2HC FD DAT (DDS) 3.5" 2HC FD 1/4" CGMT 3.5" 2HC FD Note HP-UX (Rel.10.10) SunOS (Rel.4.1.1), TM Solaris (Rel.2.5.1) NEWS-OS (Rel.6.1) TM TM Note Also operates under the DOS environment. User's Manual U11919EJ3V0UM00 197 APPENDIX A DEVELOPMENT TOOLS A.2 Flash Memory Writing Tools Flashpro III (part number: FL-PR3, PG-FP3) Flash writer FA-42CU FA-44GB FA-44GB-8ES Flash memory writing adapter Flash writer dedicated to microcontrollers with flash memory. Flash memory writing adapter. Used in connection with Flashpro III. * FA-42CU: For 42-pin plastic shrink DIP (CU type) * FA-44GB: For 44-pin plastic QFP (GB-3BS type) * FA-44GB-8ES: For 44-pin plastic LQFP (GB-8ES type) Remark FL-PR3, FA-42CU, FA-44GB, and FA-44GB-8ES are products of Naito Densei Machida Mfg. Co., Ltd. For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (044-822-3813) 198 User's Manual U11919EJ3V0UM00 APPENDIX A DEVELOPMENT TOOLS A.3 Debugging Tools A.3.1 Hardware IE-78K0S-NS In-circuit emulator In-circuit emulator for debugging hardware and software upon developing the application system using 78K/0S series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine. This is the adapter for supplying power from 100 to 240 VAC outlet. IE-70000-MC-PS-B AC adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF Interface adapter IE-789026-NS-EM1 Emulation board NP-44GB Note This adapter is needed when PC-9800 series (excluding notebook models) is used as a host machine of IE-78K0S-NS (C bus compatible). This PC card and interface cable are needed when a notebook-type personal computer is used as a host machine of IE-78K0S-NS (PCMCIA socket compatible). This adapter is needed when IBM PC/AT compatibles are used as a host machine of IE78K0S-NS (ISA bus compatible). This adapter is needed when a personal computer incorporating the PCI bus is used as a host machine of IE-78K0S-NS. Emulation board for emulating the peripheral hardware inherent to the device. Used in combination with in-circuit emulator. Emulation probe for connecting the in-circuit emulator and target system. This is for the 44-pin plastic QFP (GB-3BS type) and the 44-pin plastic LQFP (GB-8ES type). This conversion adapter is used to connect a target system board designed to allow mounting of the 44-pin plastic QFP (GB-3BS type) and the 44-pin plastic LQFP (GB-8ES type) and the NP-44GB. Emulation probe for connecting the in-circuit emulator and target system. This is for the 44-pin plastic QFP (GB-3BS type) and the 44-pin plastic LQFP (GB-8ES type). This conversion adapter is used to connect a target system board designed to allow mounting of the 44-pin plastic QFP (GB-3BS type) and the 44-pin plastic LQFP (GB-8ES type) and the NP-44GB-TQ. Emulation probe EV-9200G-44 Conversion adapter NP-44GB-TQ Emulation probe TGB-044SAP Conversion adapter Remarks 1. NP-44GB and NP-44GB-TQ are products of Naito Densei Machida Mfg. Co., Ltd. For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (044-822-3813) 2. TGB-044SAP is a product of TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kougyou, Ltd. Tokyo Electronics Department (03-3820-7112) Osaka Electronics Department (06-6244-6672) User's Manual U11919EJ3V0UM00 199 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software ID78K0S-NS Integrated debugger (Supports in-circuit emulator IE78K0S-NS) Control program for debugging 78K/0S Series. This program provides a graphical user interface. It runs on Windows for personal computer TM users and on OSF/Motif for engineering work station users, and has visual designs and operationability that comply with these operating systems. In addition, it has a powerful debug function that supports C language. Therefore, trace results can be displayed at a C language level by the window integration function that links source program, disassembled display, and memory display, to the trace result. This software also allows users to add other function extension modules such as task debugger and system performance analyzer to improve the debug efficiency for programs using a real-time operating system. Used in combination with optional device file (DF789026). Part number: SxxxxID78K0S-NS Remark xxxx in the part number differs depending on the host machines and operating system to be used. SxxxxID78K0S-NS xxxx AA13 AB13 Host Machine PC-9800 series IBM PC/AT compatibles OS Japanese Windows Japanese Windows Note Supply Media 3.5" 2HD FD 3.5" 2HC FD Note Note Also operates under the DOS environment. SM78K0S System simulator Debugs program at C source level or assembler level while simulating operation of target system on host machine. SM78K0S runs on Windows. By using SM78K0S, the logic and performance of an application can be verified independently of hardware development even when the in-circuit emulator is not used. This enhances development efficiency and improves software quality. Used in combination with optional device file (DF789026). Part number: SxxxxSM78K0S DF789026 Device file Note File containing the information inherent to the device. Used in combination with other optional tools (RA78K0S, CC78K0S, SM78K0S). Part number: SxxxxDF789026 Note DF789026 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S. Remark xxxx in the part number differs depending on the host machines and operating system to be used. SxxxxSM78K0S xxxx AA13 AB13 Host Machine PC-9800 series IBM PC/AT compatibles OS Japanese Windows Japanese Windows Note Supply Media 3.5" 2HD FD 3.5" 2HC FD Note Note Also operates under the DOS environment. 200 User's Manual U11919EJ3V0UM00 APPENDIX A DEVELOPMENT TOOLS A.4 Conversion Socket (EV-9200G-44) Drawing and Recommended Footprint Figure A-2. EV-9200G-44 Package Drawing (Reference) Based on EV-9200G-44 (1) Package drawing (in mm) A E B F EV-9200G-44 M N O Q P R K D C J 1 No.1 pin index G H I EV-9200G-44-G0 ITEM A B C D E F G H I J K L M O N P Q R MILLIMETERS 15.0 10.3 10.3 15.0 4-C 3.0 0.8 5.0 12.0 14.7 5.0 12.0 14.7 8.0 7.8 2.0 1.35 0.35 0.1 INCHES 0.591 0.406 0.406 0.591 4-C 0.118 0.031 0.197 0.472 0.579 0.197 0.472 0.579 0.315 0.307 0.079 0.053 0.014 -0.005 +0.004 1.5 0.059 L User's Manual U11919EJ3V0UM00 201 APPENDIX A DEVELOPMENT TOOLS Figure A-3. EV-9200G-44 Recommended Footprint (Reference) Based on EV-9200G-44 (2) Pad drawing (in mm) G J K E D F L I C B A EV-9200G-44-P1E ITEM A B C D E F G H I J K L Caution MILLIMETERS 15.7 11.0 0.80.02 x 10=8.00.05 0.80.02 x 10=8.00.05 11.0 15.7 5.00 0.08 5.00 0.08 0.5 0.02 1.57 0.03 2.2 0.1 1.57 0.03 INCHES 0.618 0.433 0.031+0.002 -0.001 x 0.394=0.315 +0.002 -0.002 0.031+0.002 x 0.394=0.315 +0.002 -0.001 -0.002 0.433 0.618 0.197 +0.003 -0.004 0.197 +0.003 -0.004 0.02 +0.001 -0.002 0.062 +0.001 -0.002 0.087 +0.004 -0.005 0.062 +0.001 -0.002 Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). 202 User's Manual U11919EJ3V0UM00 H APPENDIX A DEVELOPMENT TOOLS A.5 Conversion Adapter (TGB-044SAP) Drawing Figure A-4. TGB-044SAP Package Drawing (Reference) Reference diagram: TGB-044SAP (TQPACK044SA+TQSOCKET044SAP) Package dimension (unit: mm) A H C B P D E F G Protrusion height NO Q S T X R g f UW a V Z Y b d c e ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z MILLIMETERS 10.12 0.8x10=8.0 0.8 16.65 8.4 10.8 13.2 C 2.0 9.35 1.325 1.325 12.0 16.65 8.5 13.15 5.0 1.8 J I L M K INCHES 0.398 0.031x0.394=0.315 0.031 0.656 0.331 0.425 0.520 C 0.079 0.368 0.052 0.052 0.472 0.656 0.335 0.518 0.197 0.071 ITEM a b c d e f g MILLIMETERS 2.0 0.25 9.6 1.2 1.2 2.4 2.7 INCHES 0.079 0.010 0.378 0.047 0.047 0.094 0.106 TGB-044SAP-G0E 3.55 0.9 0.3 (16.95) 7.35 1.2 6.0 1.85 3.5 0.140 0.035 0.012 (0.667) 0.289 0.047 0.236 0.073 0.138 note: Product by TOKYO ELETECH CORPORATION. User's Manual U11919EJ3V0UM00 203 [MEMO] 204 User's Manual U11919EJ3V0UM00 APPENDIX B EMBEDDED SOFTWARE The following embedded software products are available for efficient program development and maintenance of the PD789026 Subseries. MX78K0S OS MX78K0S is a subset OS that is based on the ITRON specification. Supplied with the MX78K0S nucleus. The MX78K0S OS controls tasks, events, and time. In task control, the MX78K0S OS controls task execution order, and performs the switching process to a task to be executed. Remark xxxx in the part number differs depending on the host machines and operating system to be used. SxxxxMX78K0S xxxx AA13 AB13 BB13 Host Machine PC-9800 series IBM PC/AT compatibles OS Japanese Windows Japanese Windows English Windows Note Supply Media 3.5" 2HD FD 3.5" 2HC FD Note Note Note Also operates under the DOS environment. User's Manual U11919EJ3V0UM00 205 [MEMO] 206 User's Manual U11919EJ3V0UM00 APPENDIX C REGISTER INDEX C.1 Register Name Index 16-bit capture register 20 (TCP20).............................................................................................................................. 95 16-bit compare register 20 (CR20).............................................................................................................................. 95 16-bit timer counter 20 (TM20).................................................................................................................................... 95 16-bit timer mode control register 20 (TMC20) ........................................................................................................... 96 8-bit compare register 00 (CR00).............................................................................................................................. 106 8-bit timer counter 00 (TM00).................................................................................................................................... 106 8-bit timer mode control register 00 (TMC00) ........................................................................................................... 107 [A] Asynchronous serial interface mode register 00 (ASIM00)............................................................... 126, 133, 135, 146 Asynchronous serial interface status register 00 (ASIS00)............................................................................... 128, 136 [B] Baud rate generator control register 00 (BRGC00)................................................................................... 129, 137, 147 [E] External interrupt mode register 0 (INTM0)............................................................................................................... 155 [I] Interrupt mask flag register 0 (MK0).......................................................................................................................... 154 Interrupt mask flag register 1 (MK1).......................................................................................................................... 154 Interrupt request flag register 0 (IF0) ........................................................................................................................ 153 Interrupt request flag register 1 (IF1) ........................................................................................................................ 153 [K] Key return mode register 00 (KRM00) ...................................................................................................................... 157 [O] Oscillation settling time select register (OSTS)......................................................................................................... 168 [P] Port 0 (P0)................................................................................................................................................................... 71 Port 1 (P1)................................................................................................................................................................... 72 Port 2 (P2)................................................................................................................................................................... 73 Port 3 (P3)................................................................................................................................................................... 76 Port 4 (P4)................................................................................................................................................................... 77 Port 5 (P5)................................................................................................................................................................... 78 Port mode register 0 (PM0) ......................................................................................................................................... 81 Port mode register 1 (PM1) ......................................................................................................................................... 81 Port mode register 2 (PM2) ......................................................................................................................................... 81 User's Manual U11919EJ3V0UM00 207 APPENDIX C REGISTER INDEX Port mode register 3 (PM3)..........................................................................................................................................81 Port mode register 4 (PM4)..........................................................................................................................................81 Port mode register 5 (PM5)............................................................................................................................81, 98, 108 Processor clock control register (PCC) ........................................................................................................................86 Pull-up resistor option register (PUO) ..........................................................................................................................82 [R] Receive buffer register 00 (RXB00) ...........................................................................................................................124 Receive shift register 00 (RXS00)..............................................................................................................................124 [S] Serial operation mode register 00 (CSIM00)......................................................................................125, 132, 134, 145 [T] Timer clock select register 2 (TCL2) ..........................................................................................................................117 Transmit shift register 00 (TXS00) .............................................................................................................................124 [W] Watchdog timer mode register (WDTM) ....................................................................................................................118 208 User's Manual U11919EJ3V0UM00 APPENDIX C REGISTER INDEX C.2 Register Symbol Index [A] ASIM00 ASIS00 : Asynchronous serial interface mode register 00 ............................................................ 126, 133, 135, 146 : Asynchronous serial interface status register 00 ........................................................................... 128, 136 [B] BRGC00 : Baud rate generator control register 00 ................................................................................. 129, 137, 147 [C] CR00 CR20 CSIM00 : 8-bit compare register 00 ...................................................................................................................... 106 : 16-bit compare register 20 ...................................................................................................................... 95 : Serial operation mode register 00 ................................................................................. 125, 132, 134, 145 [I] IF0 IF1 INTM0 : Interrupt request flag register 0 ............................................................................................................. 153 : Interrupt request flag register 1 ............................................................................................................. 153 : External interrupt mode register 0 ......................................................................................................... 155 [K] KRM00 : Key return mode register 00.................................................................................................................. 157 [M] MK0 MK1 : Interrupt mask flag register 0 ................................................................................................................ 154 : Interrupt mask flag register 1 ................................................................................................................ 154 [O] OSTS : Oscillation settling time select register .................................................................................................. 168 [P] P0 P1 P2 P3 P4 P5 PCC PM0 PM1 PM2 PM3 PM4 PM5 PUO : Port 0....................................................................................................................................................... 71 : Port 1....................................................................................................................................................... 72 : Port 2....................................................................................................................................................... 73 : Port 3....................................................................................................................................................... 76 : Port 4....................................................................................................................................................... 77 : Port 5....................................................................................................................................................... 78 : Processor clock control register .............................................................................................................. 86 : Port mode register 0................................................................................................................................ 81 : Port mode register 1................................................................................................................................ 81 : Port mode register 2................................................................................................................................ 81 : Port mode register 3................................................................................................................................ 81 : Port mode register 4................................................................................................................................ 81 : Port mode register 5.................................................................................................................. 81, 98, 108 : Pull-up resistor option register ............................................................................................................... 82 [R] RXB00 RXS00 : Receive buffer register 00 ..................................................................................................................... 124 : Receive shift register 00........................................................................................................................ 124 User's Manual U11919EJ3V0UM00 209 APPENDIX C REGISTER INDEX [T] TCL2 TCP20 TM00 TM20 TMC00 TMC20 TXS00 : Timer clock select register 2 ..................................................................................................................117 : 16-bit capture register 20 .........................................................................................................................95 : 8-bit timer counter 00 .............................................................................................................................106 : 16-bit timer counter 20 .............................................................................................................................95 : 8-bit timer mode control register 00 .......................................................................................................107 : 16-bit timer mode control register 20 .......................................................................................................96 : Transmit shift register 00........................................................................................................................124 [W] WDTM : Watchdog timer mode register ...............................................................................................................118 210 User's Manual U11919EJ3V0UM00 APPENDIX D REVISION HISTORY Here is the revision history of this manual. "Chapter" indicates the chapter of the previous edition. Edition Second edition Revision from Previous Edition Change of PD789025 and PD789026 from "under development" to "developed" Change of symbols in Table 3-4 Change of asynchronous serial interface status register 00 so that it can be manipulated in 1-bit units Change of block diagram of each port in Section 4.2 Change of symbols and flag names of 16-bit timer mode control register 20 Change of symbols and flag names of 8-bit timer mode control register 00 Change of symbols and flag names of serial operation mode register 00 Change of symbols and flag names of asynchronous serial interface mode register 00 Change of symbols and flag names of asynchronous serial interface status register 00 Change of asynchronous serial interface status register 00 so that 1-bit memory manipulation instruction can be used Change of symbols and flag names of baud rate generator control register 00 Change of flag names of interrupt request flag register Change of flag names of interrupt mask flag register Change of symbols and flag names of key return mode register 00 Addition of description on timing of maskable interrupt request acceptance Addition of setting with Flashpro II Third edition Completion of development of PD789022 and PD789024 Change of part number from PD78F9026 to PD78F9026A Deletion of following products: PD789022CU-xxx, PD789024CU-xxx Addition of GB-8ES type package to all models Change of circuit type and recommended connection of unused pins in processing of input/output circuit type of each pin and unused pins Addition of cautions on rewriting CR20 to operation as timer interrupt Addition of cautions on rewriting CR00 to 8-bit compare register 00 (CR00) Addition of description of operation to operation as interval timer Addition of description of operation to operation as external event counter Addition of description of operation to operation as square wave output Change of flash writer from Flashpro II to Flashpro III Addition of part number of MX78K0S to embedded software CHAPTER 13 PD78F9026A APPENDIX B EMBEDDED SOFTWARE CHAPTER 2 PIN FUNCTION CHAPTER 6 16-BIT TIMER CHAPTER 7 8-BIT TIMER/EVENT COUNTER Chapter 13 PD78F9026 Throughout Chapter 10 Interrupt Functions Chapter 4 Port Functions Chapter 6 16-Bit Timer Counter Chapter 7 8-Bit Timer/Event Counter Chapter 9 Serial Interface 00 Throughout Chapter 3 CPU Architecture Chapter User's Manual U11919EJ3V0UM00 211 [MEMO] 212 User's Manual U11919EJ3V0UM00 Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6462-6829 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-2719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. 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