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FEATURES 250 MHz-1000 MHz Operating Frequency +2.5 dBm P1 dB @ 800 MHz -155 dBm/Hz Noise Floor 0.5 Degree RMS Phase Error (IS95) 0.2 dB Amplitude Balance Single 2.7 V-5.5 V Supply Pin-Compatible with AD8346 16-Lead Exposed Paddle TSSOP Package APPLICATIONS Cellular Communication Systems W-CDMA/CDMA/GSM/PCS/ISM Transceivers Fixed Broadband Access Systems LMDS/MMDS Wireless LAN Wireless Local Loop Digital TV/CATV Modulators Single Sideband Upconverter
250 MHz-1000 MHz Quadrature Modulator AD8345
FUNCTIONAL BLOCK DIAGRAM
AD8345
IBBP 1 IBBN 2 COM3 3 COM1 4 LOIN 5 LOIP
6 16 15 14
QBBP QBBN COM3 COM3 VPS2 VOUT COM2 COM3
+
13 12
PHASE SPLITTER
11 10
VPS1 7 BIAS ENBL 8
9
PRODUCT DESCRIPTION
APPLICATIONS
The AD8345 is a silicon RFIC quadrature modulator, designed for use from 250 MHz to 1000 MHz. Its excellent phase accuracy and amplitude balance enable the high performance direct modulation of an IF carrier. The AD8345 accurately splits the external LO signal into two quadrature components through the polyphase phase-splitter network. The two I and Q LO components are mixed with the baseband I and Q differential input signals. Finally, the outputs of the two mixers are combined in the output stage to provide a single-ended 50 drive at VOUT.
The AD8345 Modulator can be used as the IF transmit modulator in digital communication systems such as GSM and PCS transceivers. It can also directly modulate an LO signal to produce QPSK and various QAM formats for 900 MHz communication systems as well as digital TV and CATV systems. Additionally, this quadrature modulator can be used with direct digital synthesizers in hybrid phase-locked loops to generate signals over a wide frequency range with millihertz resolution. The AD8345 Modulator is supplied in a 16-lead TSSOP package with exposed paddle. Its performance is specified over a -40C to +85C temperature range. This device is fabricated on Analog Devices' advanced silicon bipolar process.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD8345-SPECIFICATIONS (V = 5 V; LO= -2 dBm @ 800 MHz, 50
Parameters RF OUTPUT Operating Frequency1 Output Power Output P1 dB Noise Floor Quadrature Error I/Q Amplitude Balance LO Leakage Sideband Rejection Third Order Distortion Second Order Distortion Equivalent Output IP3 Equivalent Output IP2 Output Return Loss (S22) RESPONSE TO CDMA IS95 BASEBAND SIGNALS ACPR EVM Rho LO INPUT LO Drive level LOIP Input Return Loss (S11)2 No Termination on LOIP, LOIN at AC Ground 50 Terminating Resistor, Differential Drive via Balun BASEBAND INPUTS Input Bias Current Input Capacitance DC Common Level Bandwidth (3 dB) ENABLE Turn-On Turn-Off ENBL High Threshold (Logic 1) ENBL Low Threshold (Logic 0) POWER SUPPLIES Voltage Current Active Current Standby
NOTES 1 For information on operation below 250 MHz, see Figure 4. 2 See LO Drive section for more details on input matching. Specifications subject to change without notice.
source and load impedances, I and Q inputs S 0.7 V 0.3 V on each side for a 1.2 V p-p differential input, I and Q inputs driven in quadrature @ 1 MHz Baseband Frequency. TA = 25 C, unless otherwise noted.)
Conditions Min 250 -3 20 MHz Offset from LO, All BB Inputs at 0.7 V (CDMA IS95 Setup, Refer to Figure 13) (CDMA IS95 Setup, Refer to Figure 13) Typ Max 1000 +2 Unit MHz dBm dBm dBm/Hz Degree rms dB dBm dBc dBc dBc dBm dBm dB
-1 2.5 -155 0.5 0.2 -42 -42 -52 -60 25 59 -20
-33 -34
(Refer to Figure 13) -72 1.3 0.9995 -10 -2 -5 -9 0 dBc %
dBm dB dB
0.6 Full Power (0.7 V 0.3 V on Each Input, Refer to TPC 2) Enable High to Output within 0.5 dB of Final Value Enable Low to Supply Current Dropping below 2 mA
10 2 0.7 80
0.8
A pF V MHz
2.5 1.5 +VS/2 +VS/2 2.7 50 5.5 78
s s V V V mA A
65 70
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AD8345
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
IBBP 1 IBBN 2 COM3 3 COM1 4 LOIN 5 LOIP 6 VPS1 7 ENBL 8
16 QBBP 15 QBBN 14 COM3
Supply Voltage VPS1, VPS2 . . . . . . . . . . . . . . . . . . . . . 5.5 V Input Power LOIP, LOIN (re 50 ) . . . . . . . . . . . . . 10 dBm IBBP, IBBN, QBBP, QBBN . . . . . . . . . . . . . . . . . 0 V, 2.5 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 500 mW JA (Exposed Paddle Soldered Down) . . . . . . . . . . . . 30C/W JA (Exposed Paddle not Soldered Down) . . . . . . . . . 95C/W Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD8345
TOP VIEW (Not to Scale)
13 COM3 12 VPS2 11 VOUT 10 COM2 9
COM3
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8345 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD8345ARE AD8345ARE-REEL AD8345ARE-REEL7 AD8345-EVAL
Temperature Range -40C to +85C
Package Description Tube (16-Lead TSSOP with Exposed Pad) 13" Tape and Reel 7" Tape and Reel Evaluation Board
Package Option RE-16
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AD8345
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 2
Mnemonic IBBP, IBBN
Function
Equivalent Circuit
3, 9, 13, 14 4 5, 6 7 8 10 11 12 15, 16
COM3 COM1 LOIN, LOIP VPS1 ENBL COM2 VOUT VPS2 QBBN, QBBP
I Channel Baseband Differential Input Pins. These high impedance inputs should Circuit A be dc biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin (0.4 V to 1 V). This gives a differential drive of 1.2 V p-p. Inputs are not self-biasing so external biasing circuitry must be used in ac-coupled applications. Ground Pin for Input V-to-I Converters and Mixer Core. Ground Pin for the LO Phase-Splitter and LO Buffers. Differential LO Drive Pins. Internal dc bias (approximately 1.8 V @ VS = 5 V) Circuit B is supplied. Pins must be ac-coupled. Single-ended or differential drive is permissible. Power Supply Pin for the Bias Cell and LO Buffers. This pin should be decoupled using local 1000 pF and 0.01 F capacitors. Enable Pin. A high level enables the device; a low level puts the device in sleep mode. Circuit C Ground Pin for the Output Stage of Output Amplifier. 50 DC-Coupled RF Output. Pin should be ac-coupled. Power supply pin for baseband input voltage to current converters and mixer core. This pin should be decoupled using local 1000 pF and 0.01 F capacitors. Q Channel Baseband Differential Input Pins. Inputs should be dc biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin (0.4 V to 1 V). This gives a differential drive level of 1.2 V p-p. Inputs are not self-biasing so external biasing circuitry must be used in ac-coupled applications. Circuit D
Circuit A
EQUIVALENT CIRCUITS
VPS2 BUFFER TO MIXER CORE
100k 100k TO BIAS FOR STARTUP/ SHUTDOWN ENBL VPS2
INPUT CURRENT MIRROR
100k
Circuit A
Circuit C
VPS1
VPS2
LOIN LOIP PHASE SPLITTER CONTINUES
40 VOUT
40
Circuit B Figure 1. Equivalent Circuits
Circuit D
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Typical Performance Characteristics- AD8345
0 -2 -4 SSB POWER - dBm -6 -8 -10 -12 -14 -16 -18 -20 250 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000 LO FREQUENCY - MHz VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
SSB OUTPUT P1dB - dBm
0 -2 -4 -6 TA = +25 C -8 -10 -12 -14 -16 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY - MHz TA = +85 C TA = -40 C
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
TPC 1. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (FLO). (I and Q Inputs Driven in Quadrature at Baseband Frequency (FBB) = 1 MHz; TA = 25C)
TPC 4. SSB Output 1 dB Compression Point (OP 1 dB) vs. FLO. (VS = 2.7 V, LO Level = -2 dBm, I and Q Inputs Driven in Quadrature, FBB = 1 MHz)
1.0 0.5
4.0 3.5
SSB OUTPUT P1dB - dBm
OUTPUT POWER VARIATION - dB
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 0.1 1 10 BASEBAND FREQUENCY - MHz 100 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
3.0 TA = +25 C 2.5 2.0 1.5 1.0 0.5 0.0 TA = -40 C
TA = +85 C
VS = 2.7V, 5V DIFFERENTIAL INPUT = 200mV p-p
-0.5 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY - MHz
TPC 2. I and Q Input Bandwidth. (TA = 25C, FLO = 800 MHz, LO Level = -2 dBm, I and Q Inputs Driven in Quadrature)
TPC 5. SSB Output 1 dB Compression Point (OP 1 dB) vs. FLO. (VS = 5 V, LO Level = -2 dBm, I and Q Inputs Driven in Quadrature, FBB = 1 MHz)
0 -2 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
-40 -41
CARRIER FEEDTHROUGH - dBm
-4 -6
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p -42 -43 -44 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p -45 -46 -47 -48 -49
SSB POWER - dBm
-8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -40 -20 20 0 40 TEMPERATURE - C 60 80 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
-50 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY - MHz
TPC 3. SSB POUT vs. Temperature. (FLO = 800 MHz, LO Level = -2 dBm, FBB = 1 MHz, I and Q Inputs Driven in Quadrature)
TPC 6. Carrier Feedthrough vs. FLO. (LO Level = -2 dBm, TA = 25C)
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AD8345
-30 -32 -26 -28
CARRIER FEEDTHROUGH - dBm
-34 -36 -38 -40 -42 -44 -46 -48 -50 -40 -20 0 20 40 TEMPERATURE - C 60 80 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
SIDEBAND SUPPRESSION - dBc
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p -30 -32 -34 -36 -38 -40 -42 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p -44 0 5 10 15 20 25 30 35 40 BASEBAND FREQUENCY - MHz 45 50
TPC 7. Carrier Feedthrough vs. Temperature. (FLO = 800 MHz, LO Level = -2 dBm)
TPC 10. Sideband Suppression vs. FBB. (TA = 25C, FLO = 800 MHz, LO Level = -2 dBm, I and Q Inputs Driven in Quadrature)
-35
30 28 26 24 22 20 T = +85 T = -40
-36
SIDEBAND SUPPRESSION - dBc
-37 -38 -39 -40 -41 -42 -43 -44 -45 -40 -20 0 20 40 TEMPERATURE - C 60 80 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
PERCENTAGE
18 16 14 12 10 8 6 4 2 0 -86 -82 -78 -74 -70 -66 -62 -58 CARRIER FEEDTHROUGH - dBm AFTER NULLING TO -65dBm AT +25 C -54 -50
TPC 8. Carrier Feedthrough Distribution at Temperature Extremes. After Feedthrough Nulled to <-65 dBm at TA = 25C. (FLO = 800 MHz, LO Level = -2 dBm)
TPC 11. Sideband Suppression vs. Temperature. (FLO = 800 MHz, LO Level = -2 dBm, FBB =1 MHz, I and Q Inputs Driven in Quadrature)
-30 -32 -34 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p -36 -38 -40 -42 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p -44 -46 -48 -50 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 LO FREQUENCY - MHz
-20 -25
THIRD ORDER DISTORTION - dBc
SIDEBAND SUPPRESSION - dBc
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p -30 -35 -40 -45 -50 -55 -60 -65 0 5 10 15 20 25 30 35 40 BASEBAND FREQUENCY - MHz 45 50 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
TPC 9. Sideband Suppression vs. FLO. (TA = 25C, LO Level = -2 dBm, FBB = 1 MHz, I and Q Inputs Driven in Quadrature)
TPC 12. Third Order Distortion vs. FBB. (TA = 25C, FLO = 800 MHz, LO Level = -2 dBm, I and Q Inputs Driven in Quadrature)
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-45
80 75
SUPPLY CURRENT - mA
THIRD ORDER DISTORTION - dBc
-50
-55 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p -60
70 65 60 55 50 45 40 -40
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
-65
-70
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
-75 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p -80 -40 -20 0 20 40 TEMPERATURE - C 60 80
-20
0
20 40 TEMPERATURE - C
60
80
TPC 13. Third Order Distortion vs. Temperature. (FLO = 800 MHz, LO Level = -2 dBm, FBB =1 MHz, I and Q Inputs Driven in Quadrature)
TPC 16. Power Supply Current vs. Temperature
1GHz SMITH CHART NORMALIZED TO 50
-10 -15
-2 -4 -6 SSB POUT -8 -10 -12 -14 THIRD ORDER DISTORTION -16 -18 -20 -22 -24 0.5 1.0 1.5 2.0 2.5 BASEBAND DIFFERENTIAL INPUT VOLTAGE - V p-p -26 3.0
WITH 50
THIRD ORDER DISTORTION - dBc
-20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 0.0
SSB OUTPUT POWER - dBm
250MHz
WITH 100
1GHz
LOIN NO BALUN OR TERMINATION
TPC 14. Third Order Distortion and SSB POUT vs. Baseband Differential Input Level. (TA = 25C, FLO = 800 MHz, LO Level = -2 dBm, FBB = 1 MHz, VS = 2.7 V)
TPC 17. Smith Chart of LOIN Port S11 (LOIP Pin ACCoupled to Ground). Curves with Balun and External Termination Resistors Also Shown. (VS = 5 V, TA = 25C)
0
-5 -10
THIRD ORDER DISTORTION - dBc
4 2 0 SSB POUT
SSB OUTPUT POWER - dBm
-15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 0.0 0.5 1.0 1.5 2.0 2.5 BASEBAND DIFFERENTIAL INPUT VOLTAGE - V p-p THIRD ORDER DISTORTION
-5
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 3.0
RETURN LOSS - dB
-10
-15
-20 VS = 2.7V -25 VS = 5V -30 250 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000 FREQUENCY - MHz
TPC 15. Third Order Distortion and SSB POUT vs. Baseband Differential Input Level. (TA = 25C, FLO = 800 MHz, LO level = -2 dBm, FBB = 1 MHz, VS = 5 V)
TPC 18. Return Loss (S22) of VOUT Output (TA = 25C)
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AD8345
-150 -151 -152
NOISE FLOOR - dBm/Hz
-153 -154 -155 -156 -157 -158 -159 -160 -10 -9 -8 -7 -6 -5 -4 -3 -2 LO LEVEL - dBm -1 0 1 2 VS = 5V
The LO Interface generates two LO signals at 90 degrees of phase difference with each other, to drive two mixers in quadrature. Baseband signals are converted into current form in the Differential V-to-I Converters, feeding into the two mixers. The outputs of the mixers are combined to feed the Differential-toSingle-Ended Converter, which provides a 50 output interface. Bias currents to each section are controlled by the Enable (ENBL) signal. Detailed description of each section follows.
LO Interface
TPC 19. Noise Floor vs. LO Input Power. (TA = 25C, FLO = 800 MHz, VS = 5 V, All I and Q Inputs are DC-Biased to 0.7 V) Noise Measured at 20 MHz Offset from Carrier
-36 -38
The LO Interface consists of interleaved stages of polyphase phase-splitters and buffer amplifiers. The polyphase phase-splitter contains resistors and capacitors connected in a circular manner to split the LO signal into I and Q paths in precise quadrature with each other. The signal on each path goes through a buffer amplifier to make up for the loss and high frequency roll-off. The two signals then go through another polyphase network to enhance the quadrature accuracy. The broad operating frequency range (250 MHz to 1000 MHz) is achieved by staggering the RC time constants of each stage of the phasesplitters. The outputs of the second phase-splitter are fed into the driver amplifiers for the mixers' LO inputs.
Differential V-to-I Converter
CARRIER FEEDTHROUGH - dBm
-40 -42 -44 -46 -48 -50 -10 VS = 5.5V
In this circuit, each baseband input pin is connected to an op amp driving a transistor connected as an emitter follower. A resistor between the two emitters maintains a varying current proportional to the differential input voltage through the transistor. These currents are fed to the two mixers in differential form.
Mixers
-9
-8
-7
-6
-5 -4 -3 -2 LO LEVEL - dBm
-1
0
1
2
TPC 20. LO Feedthrough vs. LO Input Power. (TA = 25C, LO = 800 MHz, VS = 5.5 V)
There are two double-balanced mixers, one for the In-phase Channel (I-Channel) and one for the Quadrature Channel (QChannel). Each mixer uses the Gilbert-cell design with four cross-connected transistors. The bases of the transistors are driven by the LO signal of the corresponding channel. The output currents from the two mixers are summed together in two load resistors. The signal developed across the load resistors is sent to the D-to-S stage.
Differential to Single-Ended Converter
CIRCUIT DESCRIPTION Overview
The AD8345 can be divided into the following sections: Local Oscillator (LO) Interface, Mixer, Differential Voltage-to-Current (V-to-I) Converter, Differential-to-Single-Ended (D-to-S) Converter, and Bias. A block diagram of the part is shown in Figure 2.
LOIP LOIN IBBP IBBN OUT QBBP QBBN PHASE SPLITTER
The differential-to-single-ended converter consists of two emitter followers driving a totem-pole output stage whose output impedance is established by the emitter resistors in the output transistors. The output of this stage is connected to the output (VOUT) pin.
Bias
A bandgap reference circuit based on the -VBE principle generates the Proportional-To-Absolute-Temperature (PTAT) as well as temperature-stable currents used by the different sections as references. When the bandgap reference is disabled by pulling down the voltage at the ENBL pin, all other sections are shut off accordingly.
Figure 2. AD8345 Block Diagram
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IP
1
AD8345
IBBP IBBN COM3 COM1 LOIN LOIP VPS1 ENBL QBBP 16 QBBN 15 COM3 14 COM3 13 VPS2 12 VOUT 11 COM2 10 COM3 9 C5 1000pF C1 1000pF C2 0.01 F QN +VS VOUT QP
2
IN C6 1000pF LO R1 50
4 5 1
3 4 5 6 7
T1 ETC1-1-13
2 3
C7 1000pF
+VS
8
C4 0.01 F
C3 1000pF
Figure 3. Basic Connections
BASIC CONNECTIONS
SIDEBAND SUPPRESSION - dBc
-5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 40 60 80 100 120 140 160 180 200 220 240 260 280 300 LO FREQUENCY - MHz VS = 5V, DIFFERENTIAL INPUT = 1.2V
The basic connections for operating the AD8345 are shown in Figure 3. A single power supply of between 2.7 V and 5.5 V is applied to pins VPS1 and VPS2. A pair of ESD protection diodes are connected internally between VPS1 and VPS2 so these must be tied to the same potential. Both pins should be individually decoupled using 1000 pF and 0.01 F capacitors, located as close as possible to the device. For normal operation, the enable pin, ENBL, must be pulled high. The turn-on threshold for ENBL is VS/2. Pins COM1 to COM3 should all be tied to the same low impedance ground plane.
LO Drive
In Figure 3, a 50 resistor to ground combines with the device's high input impedance to provide an overall input impedance of approximately 50 (see TPC 17 for a plot of LO port input impedance). For maximum LO suppression at the output, a differential LO drive is recommended. In Figure 3, this is achieved using a balun (M/A-COM Part Number ETC1-1-13). The output of the balun is ac coupled to the LO inputs which have a bias level about 1.8 V dc. An LO drive level of -2 dBm is recommended for lowest output noise. Higher levels will degrade linearity while lower levels will tend to increase the noise floor slightly. For example, reducing the LO power from -2 dBm to -10 dBm will increase the noise floor by approximately 0.3 dB (see TPC 19). The LO terminal can be driven single-ended at the expense of slightly higher LO leakage. LOIN is ac coupled to ground using a capacitor and LOIP is driven through a coupling capacitor from a (single-ended) 50 source (this scheme could also be reversed with the drive signal being applied to LOIN).
LO Frequency Range
Figure 4. Typical Lower Frequency Sideband Suppression Performance
Baseband I and Q Channel Drive
The I and Q channel baseband inputs should be driven differentially. This is convenient as most modern high-speed DACs have differential outputs. For optimal performance at VS = 5 V, the drive signal should be a 1.2 V p-p differential signal with a bias level of 0.7 V; that is, each input should swing from 0.4 V to 1 V. If the AD8345 is being run on a lower supply voltage, the peak-to-peak voltage on the I and Q channel inputs must be reduced to avoid input clipping. For example, at a supply voltage of 2.7 V, a 200 mV p-p differential drive is recommended. This will result in a corresponding reduction in output power (see TPC 1). The I and Q inputs have a large input bandwidth of approximately 80 MHz. At lower baseband input levels, the input bandwidth increases (see TPC 2). If the baseband signal has a high peak-to-average ratio (e.g., CDMA or WCDMA), the rms signal strength will have to be backed off from this peak level in order to prevent clipping of the signal peaks. Clipping of signal peaks will tend to increase signal leakage into adjacent channels. Backing off the I and Q signal strength in the manner recommended will reduce the output power by a corresponding amount. This also applies to multicarrier applications where the per-carrier output power will be lower by 3 dB for each doubling of the number of output carriers.
The frequency range on the LO input is limited by the internal quadrature phase splitter. The phase splitter generates drive signals for the internal mixers which are 90 out of phase relative to one another. Outside of the specified LO frequency range of 250 MHz to 1 GHz, this quadrature accuracy degrades, resulting in decreased sideband suppression. See TPC 9 for a plot of sideband suppression vs. LO frequency from 250 MHz to 1 GHz. Figure 4 shows the sideband suppression of a typical device from 50 MHz to 300 MHz. The level of sideband suppression degradation below 250 MHz will be subject to manufacturing process variations.
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AD8345
+5V 10k 1.5k 348 49.9 0.1 F 348 24.9 IBBN 348 0.1 F -5V QBBP +5V QBBN 0.1 F 348 348 49.9 0.1 F 348 24.9 348 10 F 0.1 F 10 F 10 F PHASE SPLITTER LOIN VOUT 0.1 F 348 10 F 0.01 F 1000pF 1000pF 0.01 F
IIN
AD8132
VPS1 VPS2 IBBP
LOIP
AD8345
COM1 COM2 COM3
QIN
AD8132
-5V
Figure 5. Single-Ended IQ Drive Circuit
The I and Q inputs have high input impedances because they connect directly to the bases of pnp transistors. If a (dc-coupled) filter is being used between a DAC and the modulator inputs, this filter will need to be terminated with the appropriate resistance. If the filter is differential, the termination resistor should be connected across the I and Q differential inputs.
Reduction of LO Leakage
Compensated LO leakage will degrade somewhat as the frequency is moved away from the frequency at which the compensation was performed. This is due to the effects of LO to RF output leakage which are not a result of offsets on the I and Q inputs.
Single-Ended I and Q Drive
Because the I and Q signals are being effectively multiplied with the LO, any internal offset voltages on these inputs will result in leakage of the LO. The nominal LO leakage of -42 dBm which results from these internal offset voltages, can be reduced further by applying offset compensation voltages on the I and Q inputs. (Note that LO feedthrough is reduced by varying the differential offset voltages on the I and Q inputs, not by varying the nominal bias level of 0.7 V.) This is easily accomplished by programming (and then storing) the appropriate DAC offset code to reduce the LO leakage. This does, however, require the path from the DAC to the I and Q inputs to be dc-coupled. (DC-coupling is also advantageous from the perspective of I and Q input biasing if the DAC is capable of delivering a bias level of 0.7 V). The procedure for reducing the LO feedthrough is simple. In order to isolate the LO in the output spectrum, a single sideband configuration is recommended (set I and Q signals to sine and cosine waves at, say, 100 kHz, set LO to FRF - 100 kHz). An offset voltage is applied from the I DAC until the LO leakage reaches a trough. With this offset level held, an offset voltage is applied to the Q DAC until a (lower) trough is reached. LO leakage compensation holds up well over temperature. TPC 8 shows the effect of temperature on LO leakage after compensation at ambient.
Where only single-ended I and Q signals are available, a differential amplifier such as the AD8132 or AD8138 can be used to generate the required differential drive signal for the AD8345. Even though most DACs have differential outputs, using a single-ended low-pass filter between the dual DAC and the I and Q inputs, may be more desirable from the perspective of component count and cost. As a result, the output signal from the filter must be converted back to differential mode and possibly be rebiased to 0.7 V common mode. Figure 5 shows a circuit which converts a ground-referenced, single-ended signal to a differential signal and adds the required 0.7 V bias voltage. Two AD8132 differential op amps, configured for a gain of unity, are used. With a 50 input impedance, this circuit is configured to accept a signal from a 50 source (e.g., a low-pass filter). The input impedance can be easily changed by replacing the 49.9 shunt resistor (and the corresponding 24.9 resistor on the inverting input) with the appropriate value. The required dc-bias level is conveniently added to the signal by applying 0.7 V to the VOCM pins of the differential amplifiers. Differential amplifiers such as the AD8132 and AD8138 can also be used to implement active filters. For more information on this topic, consult the data sheets of these devices.
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DVDD DCOM AVDD 310nH 33pF IOUTB DAC DATA INPUTS 51 51 10 QOUTA LATCH "Q" SELECT WRITE CLOCK MUX CONTROL SLEEP FS ADJ RSET 2k REFIO 10 0.1 F 2 "Q" DAC QOUTB 51 33pF 51 310nH 310nH 100 33pF QBBN QBBP PHASE SPLITTER LOIN 310nH 100 33pF VOUT IBBN VPS1 IBBP VPS2 IOUTA LATCH "I" 2 "I" DAC
AD9761
LOIP
AD8345
Figure 6. AD8345/TxDAC Interface
Note that this circuit assumes that the single-ended I and Q signals are ground referenced. Any differential dc-offsets will result in increased LO Leakage at the output of the AD8345. It is possible to drive the baseband inputs with a single-ended signal biased to 0.7 V, with the unused inputs being biased to a dc level of 0.7 V. However, this mode of operation is not recommended because any dc level difference between the bias level of the drive signal and the dc level on the unused input (including the effect of temperature drift) will result in increased LO leakage. In addition, the maximum output power will be reduced by 6 dB.
RF Output
positive full scale, IBBP will be equal to 0.96 V. With IOUTB at 0 mA, the voltage at IBBN will be equal to 0.456 V. This results in a full-scale differential signal of approximately 1 V p-p which will have a common-mode level of 0.7 V.
Soldering Information
The AD8345 is packaged in a 16-lead TSSOP package with exposed pad. For optimum thermal conductivity, the exposed pad can be soldered to the exposed metal of a ground plane. This results in a junction-to-air thermal impedance (JA) of 30C/W. However, soldering is not necessary for safe operation. If exposed pad is not soldered down, the JA is equal to 95C/W.
Evaluation Board
The RF output is designed to drive a 50 load but should be ac coupled as shown in Figure 3. If the I and Q inputs are driven in quadrature by 1.2 V p-p signals, the resulting output power will be approximately -1 dBm (see TPC 1). The RF output impedance is very close to 50 . As a result, no additional matching circuitry is required if the output is driving a 50 load.
Application with TxDAC
Figure 7. Shows the schematic of the AD8345 evaluation board. Note that uninstalled components are marked as open. This is a 4-layer board, with the two center layers used as ground plane and top and bottom layers used as signal and power planes. The board is powered by a single supply (VS) in the range, 2.7 V to 5.5 V. The power supply is decoupled by a 0.01 F and 1000 pF capacitors. The circuit closely follows the basic connection schematic with SW1 in B Position. If SW1 is in Position A, the Enable pin will be pulled to ground by a 10 k resistor and the device will be in its power-down mode. All connectors are SMA-type. The I and Q inputs are dc-coupled to allow a direct connection to a dual DAC with differential outputs. Resistor pads are provided in case termination at the I and Q inputs is required. The local oscillator input (LO) is terminated to approximately 50 with an external 50 resistor to ground. A 1:1 wide-band transformer (ETC1-1-13) provides a differential drive to the AD8345's differential LO input. The device can also be driven single-ended by shorting out T1.
Figure 6 shows the AD8345 driven by the AD9761 TxDAC (any of the devices in ADI's TxDAC family can also be used in this application). The signal from the DAC is being filtered by a differential 51 MHz low-pass filter. The I and Q DACs generate differential output currents of 0 mA to 20 mA and 20 mA to 0 mA, respectively. When loaded with 50 ground-referenced resistors, this would produce a 2 V p-p differential signal (i.e., 1 V p-p on each output) with a commonmode level of 0.5 V. In the configuration shown, each DAC output sees a composite load of 48 (10 + 51 (100 + 51 )) in the passband. So, for example, when IOUTA is driven to its
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AD8345
R1 (OPEN) IP
AD8345
1 IBBP
R9 (OPEN) QP
QBBP 16
IN R2 (OPEN)
2 IBBN
QBBN 15 R10 (OPEN)
QN
3 COM3
COM3 14 R11 0 C5 1000pF R12 0 C6 0.01 F VPOS
4 COM1
COM3 13
C1 1000pF LO R6 50
4 5 1 5 LOIN
VPS2 12
T1 ETC1-1-13
2 3
C2 1000pF
6 LOIP
VOUT 11 C7 1000pF R14 (OPEN) R15 (OPEN)
VOUT
VPOS C3 0.01 F
R7 0
7 VPS1
COM2 10
C4 1000pF
8 ENBL
COM3 9
A ENBL R8 10k B VPOS SW1
Figure 7. Evaluation Board Schematic
IP
QP COMPONENT SIDE QN
IN
TP 4 R1
R6
R2 T1 C1 C2
C4
R9 DUT C5 C7
R 10 R 12
R 14 R 15
TP 2
A R8 L0 SW 1 ENBL B
VOUT
TP 1 TP 3
08-007084 REV A
a
AD8345 EVAL BOARD
Figure 8. Evaluation Board Silkscreen
Figure 10. Layout of Evaluation Board, Bottom Layer
Figure 9. Layout of Evaluation Board, Top Layer
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AD8345
IEEE D1 34901 D1 +15V MAX COM IEEE +25V MAX -25V MAX VN GND VP P1 VPS1 INTERFACE BOARD I_IN Q_IN
HP34970A
D2 34907 D2 D3 34907 D3
TEKAFG2020
OUTPUT_1 OUTPUT_2 IEEE
HP3631
ARB FUNCTION GEN IN IP QP QN
IP
QP
HP8648C
IEEE RFOUT
IN
AD8345
QN
CHARACTERIZATION BOARD LO VOUT ENBL P1
HP8593E
RF I/P SWEEP OUT 28V IEEE
SPECTRUM ANALYZER IEEE PC CONTROLLER
Figure 11. Characterization Board SSB Test Setup
CHARACTERIZATION SETUPS SSB Setup Modulated Waveform Setup
Essentially, two primary setups were used to characterize the AD8345. These setups are shown in Figures 11 and 13. Figure 11 shows the setup used to evaluate the product as a Single Sideband modulator. The interface board converts the singleended I and Q inputs from the arbitrary function generator to differential inputs with a dc bias of approximately 0.7 V. The interface board also provides connections for power supply routing. The HP34970A and its associated plug-in 34901 were used to monitor power supply currents and voltages being supplied to the AD8345 characterization board. Two HP34907 plug-ins were used to provide additional miscellaneous dc and control signals to the interface board. The LO input was driven directly by an RF signal generator and the output was measured directly with a spectrum analyzer. With the I Channel driven with a sine wave and the Q Channel driven with a cosine wave, the lower sideband is the single sideband output. The typical SSB output spectrum is shown in Figure 12.
0 -10 -20
For evaluating the AD8345 with modulated waveforms, the setup shown in Figure 13 was used. A Rohde & Schwarz AMIQ signal generator with differential outputs was used to generate the baseband signals. For all measurements the input level on each baseband input pin was 0.7 V 0.3 V peak. The output was measured with a Rohde & Schwarz FSIQ spectrum/vector analyzer.
PC CONTROL AMIQ IN IEEE PC CONTROLLER IP QP QN IP QP QN
HP8648C
IEEE RFOUT
IN
AD8345
CHARACTERIZATION BOARD LO ENBL VOUT P1
FSIQ
RF I/P IEEE
SPECTRUM ANALYZER +15V MAX COM IEEE +25V MAX -25V MAX
AMPLITUDE - dBm
-30 -40 -50 -60 -70 -80 -90
HP3631
Figure 13. Test Setup for Evaluating AD8345 with Modulated Waveforms
-100 CENTER = 900MHz SPAN = 1MHz
Figure 12. Typical SSB Output Spectrum
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AD8345
CDMA IS95
-10 -20 -30
AMPLITUDE - dBm
For measuring ACPR, the I and Q input signals used were generated with Pilot (Walsh Code 00), Sync (WC 32), Paging (WC 01), and 6 Traffic (WC 08, 09, 10, 11, 12, 13) channels active. Figure 14 shows the typical output spectrum for this configuration. For performing EVM, Rho, phase, and amplitude balance measurements, the I and Q input signals used were generated with only the Pilot Channel (Walsh Code 00) active.
-10 -20 -30
AMPLITUDE - dBm
CH PWR = -10.95dBm ACP UP = -52.51dB ACP LOW = -52.41dB
-40 -50 -60 -70 -80 -90
CH PWR = -12.41dBm ACP UP = -72.8dB ACP LOW = -72.8dB
-100 -110 CENTER = 380MHz SPAN = 14.7MHz
-40 -50 -60 -70 -80 -90 -100 -110 CENTER = 880MHz SPAN = 7.5MHz
Figure 15. Typical AD8345 WCDMA 3GPP Output Spectrum
GSM
For comparing the AD8345 output to the GSM transmit mask I and Q signals were generated using MSK modulation, GSM differential coding, a Gaussian filter and a symbol rate of 270.833 kHz. The transmit mask was manually generated on the FSIQ using the GSM BTS specification for reference. The plot in Figure 16 shows that the AD8345 meets the GSM transmit mask requirements.
0 -10 -20
Figure 14. Typical IS95 Output Spectrum
WCDMA 3GPP
AMPLITUDE - dBm
For evaluating the AD8345 for WCDMA, the 3GPP standard was used with a Chip Rate of 3.84 MHz. The plot in Figure 15 is an ACPR plot of the AD8345 using "Test Model 1" from the 3GPP specification with 64 channels active.
-30 -40 -50 -60 -70 -80 -90
-100 CENTER = 900MHz SPAN = 1MHz
Figure 16. Typical AD8345 GSM Output Spectrum
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AD8345
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead HTSSOP with Exposed Pad (RE-16)
0.201 (5.10) 0.193 (4.90)
16
9
0.118 (3.0) SQ
1
EXPOSED PAD
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
8
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
8 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0 BSC 0.0075 (0.19) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
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-16-
C00932-1.5-7/01(0)
PRINTED IN U.S.A.

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