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CY7C371I
UltraLogicTM 32-Macrocell Flash CPLD
Features
* * * * 32 macrocells in two logic blocks 32 I/O pins 5 dedicated inputs including 2 clock pins In-System Reprogrammable (ISRTM) Flash technology -- JTAG interface * Bus Hold capabilities on all I/Os and dedicated inputs * No hidden delays * High speed -- fMAX = 143 MHz -- tPD= 8.5 ns -- tS = 5 ns * * * * -- tCO = 6 ns Fully PCI compliant 3.3V or 5.0V I/O operation Available in 44-pin PLCC, and TQFP packages Pin compatible with the CY7C372i signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. Like all of the UltraLogicTM FLASH370i devices, the CY7C371I is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins. The ISR interface is enabled using the programming voltage pin (ISR EN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments. The 32 macrocells in the CY7C371I are divided between two logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370i architecture are connected with an extremely fast and predictable routing resource--the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. Like all members of the FLASH370i family, the CY7C371I is rich in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY7C371I. In addition, there are three dedicated inputs and two input/clock pins.
Functional Description
The CY7C371I is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370iTM family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C371I is de-
Logic Block Diagram
CLOCK INPUTS INPUTS
3 INPUT MACROCELLS 2 16 I/Os I/O0-I/O15 LOGIC BLOCK A
2 INPUT/CLOCK MACROCELLS 2 LOGIC BLOCK B 16 I/Os I/O16-I/O31
36 16
PIM
36 16
16
16
7c371i-1
Selection Guide
7C371i-143 Maximum Propagation Delay , tPD (ns) Minimum Set-Up, tS (ns) Maximum Clock to Output[1], tCO (ns) Typical Supply Current, ICC (mA) Comm./Ind.
[1]
7C371i-110 10 6 6.5 75
7C371i-83 12 8 8 75
7C371iL-83 12 8 8 45
7C371i-66 15 10 10 75
7C371iL-66 15 10 10 45
8.5 5 6 75
Note: 1. The 3.3V I/O mode timing adder, t 3.3IO, must be added to this specification when VCCIO = 3.3V.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 July 1, 1998
CY7C371I
Pin Configurations
PLCC TopView
I/O4 I/O3 I/O31 I/O30 I/O29 I/O28 I/O2
I/O1 I/O0 GND VCCIO
TQFP TopView
I/O31 I/O30 I/O29 I/O28
I/O 1 I/O 0 GND VCCIO
I/O 4 I/O 3
I/O 2
6 5 4 3 2 1 44 43 42 41 40 I/O5 /SCLK I/O6 I/O7 I0 ISREN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O13 /SMODE I/O14 I/O15 V CCINT GND I/O16 I/O17 I/O18 I/O19 /SDO I/O20 I/O27 /SDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 I2 I/O23 I/O22 I/O21 7c371i-2
I/O5 /SCLK I/O6 I/O7 I0 ISREN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11
44 43 42 41 40 39 38 37 36 35 34 33 32 2 3 31 4 30 5 29 6 28 27 7 1 26 8 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 I/O12 I/O13 /SMODE I/O14 I/O15 V CCINT GND I/O16 I/O17 I/O18 I/O19 /SDO I/O20
I/O27 /SDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 I2 I/O23 I/O22 I/O21 7c371i-3
Functional Description (continued)
Finally, the CY7C371I features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used or the type of application, the timing parameters on the CY7C371I remain the same. Logic Block The number of logic blocks distinguishes the members of the FLASH370i family. The CY7C371I includes two logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. Product Term Array The product term array in the FLASH370i logic block includes 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows for very complex functions to be implemented in a single pass through the device. Product Term Allocator The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370i CPLDs. Note that product term allocation is handled by software and is invisible to the user.
I/O Macrocell Each of the macrocells on the CY7C371I has a separate associated I/O pin. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed. It also has polarity control, and two global clocks to trigger the register. The macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the two logic blocks on the CY7C371I to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Programming For an overview of ISR programming, refer to the FLASH370i Family data sheet and for ISR cable and software specifications, refer to ISR data sheets. For a detailed description of ISR capabilities, refer to the Cypress application note, "An Introduction to In System Reprogramming with FLASH370i." PCI Compliance The FLASH370i family of CMOS CPLDs are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The simple and predictable timing model of FLASH370i ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without simple and predictable timing, PCI compliance is dependent upon routing and product term distribution. 3.3V or 5.0V I/O operation The FLASH370i family can be configured to operate in both 3.3V and 5.0V systems. All devices have two sets of VCC pins: one
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CY7C371I
set, VCCINT, for internal operation and input buffers, and another set, VCCIO, for I/O output drivers. VCCINT pins must always be connected to a 5.0V power supply. However, the VCCIO pins may be connected to either a 3.3V or 5.0V power supply, depending on the output requirements. When VCCIO pins are connected to a 5.0V source, the I/O voltage levels are compatible with 5.0V systems. When VCCIO pins are connected to a 3.3V source, the input voltage levels are compatible with both 5.0V and 3.3V systems, while the output voltage levels are compatible with 3.3V systems. There will be an additional timing delay on all output buffers when operating in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is available in commercial and industrial temperature ranges. Bus Hold Capabilities on all I/Os and Dedicated Inputs In addition to ISR capability, a new feature called bus-hold has been added to all FLASH370i I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. Design Tools Development software for the CY7C371I is available from Cypress's Warp2(R), Warp2SimTM, and Warp3(R) software packages. All of these products are based on the IEEE-standard VHDL language. Cypress also actively supports third-party design tools from companies such as Synopsys, Mentor Graphics, Cadence, and Synario. Please refer to third-party tool support for further information.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential ................. -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State..................................................... -0.5V to +7.0V DC Input Voltage ................................................. -0.5V to +7.0V DC Program Voltage..................................................... 12.5V Output Current into Outputs (LOW)............................. 16 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC VCCINT 5V 0.25V VCCIO 5V 0.25V OR 3.3V 0.3V 5V 0.5V OR 3.3V 0.3V
Industrial
-40C to +85C
5V 0.5V
3
CY7C371I
Electrical Characteristics Over the Operating Range[2,3]
Param. VOH VOHZ VOL VIH VIL IIX IOZ IOS ICC IBHL IBHH IBHLO IBHHO Description Output HIGH Voltage with Output Enabled Output HIGH Voltage with Output Disabled[8] Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[7,8] Power Supply Current Input Bus Hold LOW Sustaining Current Input Bus Hold HIGH Sustaining Current Input Bus Hold LOW Overdrive Current Input Bus Hold HIGH Overdrive Current VCC = Min. VCC = Max. VCC = Min. Test Conditions IOH = -3.2 mA (Com'l/Ind) IOH = 0 A (Com'l/Ind)[4,5] IOH = -50 A (Com'l/Ind) Guaranteed Input Logical HIGH Voltage for all inputs Guaranteed Input Logical LOW Voltage for all inputs VI = Internal GND, V I = V CC VCC = Max., VO = GND or VO =VCC, Output Disabled VCC = Max., VO = 3.3V, Output Disabled[5] VCC = Max., VOUT = 0.5V VCC = Max., IOUT = 0 mA, f = 1 MHz, VIN = GND, VCC[9] VCC = Min., VIL = 0.8V VCC = Min., VIH = 2.0V VCC = Max. VCC = Max. Com'l/Ind. Com'l "L" -66, -83 +75 -75 +500 -500
[4,5] [4]
Min. 2.4
Typ.
Max.
Unit V
4.0 3.6 0.5 2.0 -0.5 -10 -50 0 -30 75 45 -70 7.0 0.8 +10 +50 -125 -160 125 75
V V V V V A A A mA mA mA A A A A
IOL = 16 mA (Com'l/Ind)[4]
[6] [6]
Capacitance[8]
Parameter CI/O[10] CCLK Description Input Capacitance Clock Signal Capacitance Test Conditions VIN = 5.0V at f=1 MHz VIN = 5.0V at f = 1 MHz 5 Min. Max. 8 12 Unit pF pF
Inductance[8]
Parameter L Description Maximum Pin Inductance Test Conditions VIN = 5.0V at f= 1 MHz 44-Lead TQFP 2 44-Lead PLCC 5 Unit nH
Endurance Characteristics[8]
Parameter N Description Maximum Reprogramming Cycles Test Conditions Normal Programming Conditions Max. 100 Unit Cycles
Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT. 4. I OH = -2 mA, IOL = 2 mA for SDO. 5. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note "Understanding Bus Hold" for additional information. 6. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 7. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 8. Tested initially and after any design or process changes that may affect these parameters. 9. Measured with 16-bit counter programmed into each logic block.
4
CY7C371I
AC Test Loads and Waveforms
238 (COM'L) 319 (MIL) 5V OUTPUT 35 pF INCLUDING JIG AND SCOPE 170 (COM'L) 236 (MIL)
7c371i-4
238 (COM'L) 319 (MIL) 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 170 (COM'L) 236 (MIL) (b) 3.0V
7c371i-5
(a)
ALL INPUT PULSES 90% 90% 10% < 2 ns
7c371i-6
Equivalent to:
THEVENIN EQUIVALENT 99 (COM'L) 136 (MIL) 2.08V(COM'L) OUTPUT 2.13V(MIL)
GND < 2 ns
10%
(c)
Parameter[11] tER(-)
Vx 1.5V
Output Waveform Measurement Level
VOH 0.5V tER(+) 2.6V 0.5V VOL tEA(+) 1.5V 0.5V VX tEA(-) Vthe VX 0.5V
Notes: 10. CI/O for ISR EN is 15 pF Max. 11. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
VX VX
VOH
VOL
5
CY7C371I
Switching Characteristics Over the Operating Range[12]
7C371i-143 Parameter tPD tPDL tPDLL tEA tER tWL tWH tIS tIH tICO tICOL Description Input to Combinatorial Output[1] Input to Output Through Transparent Input or Output Latch[1] Input to Output Through Transparent Input and Output Latches[1] Input to Output Enable[1] Input to Output Disable Clock or Latch Enable Input LOW Time[8] Clock or Latch Enable Input HIGH Time Input Register or Latch Set-Up Time Input Register or Latch Hold Time Input Register Clock or Latch Enable to Combinatorial Output[1] Input Register Clock or Latch Enable to Output Through Transparent Output Latch[1] Clock or Latch Enable to Output[1] Set-Up Time from Input to Clock or Latch Enable Register or Latch Data Hold Time Output Clock or Latch Enable to Output Delay (Through Memory Array)[1] Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable Maximum Frequency with Internal Feedback (Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[8] Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO)[8] Maximum Frequency with external feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH))[8] Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[8,13] 7 9 5 0 12 9 10
[8]
7C371i-110 Min. Max. 10 13 15 14 14 3 3 2 2
7C371i-83 7C371iL-83 Min. Max. 12 18 20 19 19 4 4 3 3
7C371i-66 7C371iL-66 Min. Max. 15 22 24 24 24 5 5 4 4 Unit ns ns ns ns ns ns ns ns ns 24 26 ns ns
Min.
Max. 8.5 11.5 13.5 13 13
Combinatorial Mode Parameters
Input Registered/Latched Mode Parameters 2.5 2.5 2 2 12 14
14 16
19 21
Output Registered/Latched Mode Parameters tCO tS tH tCO2 tSCS tSL 6 6 0 14 12 12 6.5 8 0 19 15 15 8 10 0 24 10 ns ns ns ns ns ns
tHL
0
0
0
0
ns
fMAX1 fMAX2
143 166.7
111 153.8
83.3 100
66.6 83.3
MHz MHz
fMAX3 tOH-tIH 37x
91 0
80 0
50 0
41.6 0
MHz ns
Notes: 12. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 13. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C371I. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.
6
CY7C371I
Switching Characteristics Over the Operating Range[12] (continued)
7C371i-143 Parameter tICS fMAX4 Description Input Register Clock to Output Register Clock Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) Asynchronous Reset Width[8] Asynchronous Reset Recovery Time Asynchronous Reset to Output Asynchronous Preset Width[8] Asynchronous Preset Recovery Time Asynchronous Preset to Output Tap Controller Frequency 3.3V I/O mode timing adder
[1] [8] [1] [8]
7C371i-110 Min. 9 111 Max.
7C371i-83 7C371iL-83 Min. 12 76.9 Max.
7C371i-66 7C371iL-66 Min. 15 62.5 Max. Unit ns MHz
Min. 7 125
Max.
Pipelined Mode Parameters
Reset/Preset Parameters tRW tRR tRO tPW tPR tPO fTAP t3.3IO 8 10 14 8 10 14 500 1 500 1 10 12 16 500 1 10 12 16 15 17 21 500 1 15 17 21 20 22 26 20 22 26 ns ns ns ns ns ns kHz ns
Tap Controller Parameters 3.3V I/O Mode Parameters
Switching Waveforms
Combinatorial Output
INPUT tPD COMBINATORIAL OUTPUT
7c371i-7
atched Output
INPUT tS LATCH ENABLE tPDL LATCHED OUTPUT
7c371i-8
tH
tCO
7
CY7C371I
Switching Waveforms (continued)
Registered Input
REGISTERED INPUT tIS INPUT REGISTER CLOCK COMBINATORIAL OUTPUT tWH CLOCK tWL tIH
tICO
7c371i-9
Clock to Clock
REGISTERED INPUT
INPUT REGISTER CLOCK tICS OUTPUT REGISTER CLOCK
7c371i-10
tSCS
Latched Input
LATCHED INPUT tIS LATCH ENABLE tPDL COMBINATORIAL OUTPUT tICO tIH
tWH LATCH ENABLE
tWL
7c371i-11
8
CY7C371I
Switching Waveforms (continued)
Latched Input and Output
LATCHED INPUT
tPDLL LATCHED OUTPUT tICOL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tSL tHL
tWH LATCH ENABLE
tWL
7c371i-12
Asynchronous Reset
tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK
7c371i-13
Asynchronous Preset
tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK
7c371i-14
9
CY7C371I
Switching Waveforms (continued)
Output Enable/Disable
INPUT tER OUTPUTS
7c371i-16
tEA
Ordering Information
Speed (MHz) 143 110 Ordering Code CY7C371I-143AC CY7C371I-143JC CY7C371I-110AC CY7C371I-110JC CY7C371I-110AI CY7C371I-110JI 83 CY7C371I-83AC CY7C371I-83JC CY7C371I-83AI CY7C371I-83JI CY7C371IL-83AC CY7C371IL-83JC CY7C371IL-83AI CY7C371IL-83JI 66 CY7C371I-66AC CY7C371I-66JC CY7C371I-66AI CY7C371I-66JI CY7C371IL-66AC CY7C371IL-66JC CY7C371IL-66AI CY7C371IL-66JI Package Name A44 J67 A44 J67 A44 J67 A44 J67 A44 J67 A44 J67 A44 J67 A44 J67 A44 J67 A44 J67 A44 J67 Package Type 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier 44-Lead Thin Plastic Quad Flat Pack 44-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial
Document #: 38-00497-D Warp2Sim, FLASH370, FLASH370i, ISR, and UltraLogic are trademarks of Cypress Semiconductor Corporation Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
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CY7C371I
Package Diagrams
44-Lead Thin Plastic Quad Flat Pack A44
51-85064-B
44-Lead Plastic Leaded Chip Carrier J67
51-85003-A
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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