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| ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER Description The ICS558-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs are split into two banks of two outputs. Each bank has a separate output enable to tri-state the output buffers. The ICS558-02 is a member of the ICS Clock BlocksTM family of clock generation, synchronization, and distribution devices. Features * * * * * * 16-pin TSSOP package LVHSTL inputs Accepts up to 250 MHz input frequency Four low skew (<250 ps) outputs Selectable internal divider of 3 or 4 Operating voltage of 3.3 V Block Diagram VDD 4 OE0 CLK1 CLK2 Output Divide /3 or /4 CLK3 CLK4 HCLK HCLK SEL 3 GND OE1 MDS 558-02 D I n t e gra te d C i r c u i t S y s t e m s 1 525 Race Stre et, San Jo se, CA 9 5126 Revision 020504 te l (40 8) 2 97-12 01 w w w. i c st . c o m ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER Pin Assignment SEL VDD VDD HCLK HCLK GND GND OE0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VDD CLK1 CLK2 CLK3 CLK4 GND OE1 Tri-State Table OE1 0 0 1 1 OE0 0 1 0 1 CLK 1, CLK 2 Tri-state Clock ON Tri-state Clock ON CLK 3, CLK 4 Tri-state Tri-state Clock ON Clock ON Output Divide Selection SEL 0 1 Output Divide /3 /4 16 Pin 173 Mil (0.65mm) TSSOP Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name SEL VDD VDD HCLK HCLK GND GND OE0 OE1 GND CLK4 CLK3 CLK2 CLK1 VDD VDD Pin Type Input Power Power Input Input Power Power Input Input Power Output Output Output Output Power Power Pin Description Select pin for output divider. See table above. Internal pull-up to VDD. Connect to +3.3 V. Connect to +3.3 V. Differential LVHSTL input (true input). Differential LVHSTL input (complimentary input). Connect to ground. Connect to ground. Output enable for CLK1 and CLK2. See table above. Internal pull-up to VDD. Output enable for CLK3 and CLK4. See table above. Internal pull-up to VDD. Connect to ground. Low skew clock output. Low skew clock output. Low skew clock output. Low skew clock output. Connect to +3.3 V. Connect to +3.3 V. MDS 558-02 D In te grated Circuit Systems 2 525 Ra ce Street, San Jose, CA 9512 6 Revision 020504 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS558-02. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 4.6 V Rating -0.5 V to VDD+0.5 V 0 to +70 C -65 to +150 C 125 C 260 C Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. 0 +3.15 Typ. +3.3 Max. +70 +3.5 Units C V DC Electrical Characteristics VDD=3.3 V 5%, Ambient temperature 0 to +70C, unless stated otherwise stated. Parameter Operating Voltage Operating Supply Current Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Peak to Peak Input Voltage HCLK Input Leakage Current Input Common Mode Voltage Output High Voltage Output Low Voltage Symbol VDD IDD VIH VIL VIH VIL IIL Vx VOH VOL Conditions No load, 100 MHz OE pins OE pins HCLK HCLK HCLK Min. 3.135 VDD-0.5 Vx + 0.1 -0.3 0.3 -20 Typ. 3.3 60 Max. 3.465 VDD 0.5 1.2 Vx - 0.1 1.0 20 0.90 Units V mA V V V V V A V V Input Common Mode IOH = -14.5 mA IOL = 9.4 mA 0.68 2.4 0.4 V MDS 558-02 D In te grated Circuit Systems 3 525 Ra ce Street, San Jose, CA 9512 6 Revision 020504 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER Parameter Nominal Output Impedance Internal Pull-up Resistor Input Capacitance Symbol ZO RPU CIN Conditions Min. Typ. 20 250 7 Max. Units k pF AC Electrical Characteristics VDD = 3.3 V 5%, Ambient Temperature 0 to +70C, unless stated otherwise stated. Parameter Input Frequency Output Rise Time Output Fall Time Skew (between any two output clocks) Propagation Delay Output Clock Duty Cycle Symbol tOR tOF Conditions 0.4 to 2.4 V, CL=30 pF 2.4 to 0.4 V, CL=30 pF 30 pF load Min. 0 0.5 0.5 Typ. 1.1 1.0 0 9 Max. Units 250 2.0 2.0 250 12 55 MHz ns ns ps ns % at VDD/2, CL=30 pF 45 50 Thermal Characteristics (16-pin TSSOP) Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 78 70 68 37 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case MDS 558-02 D In te grated Circuit Systems 4 525 Ra ce Street, San Jose, CA 9512 6 Revision 020504 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 16 Millimeters Symbol Min Max Inches Min Max E1 INDEX AREA E 12 D A A1 A2 b C D E E1 e L aaa -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A2 A1 A c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number ICS558G-02 ICS558G-02T Marking (both) ICS558G-02 ICS558G-02 Shipping packaging Tubes Tape and Reel Package 16-pin TSSOP 16-pin TSSOP Temperature 0 to 70C 0 to 70C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 558-02 D In te grated Circuit Systems 5 525 Ra ce Street, San Jose, CA 9512 6 Revision 020504 tel (4 08) 297-1 201 w w w. i c s t . c o m |
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