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K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Document Title
64M x 8 Bit , 32M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 1.0 Initial issue. 1.Pin assignment of TBGA dummy ball is changed. (before) DNU --> (after) N.C 2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 34) 3. Add the data protection Vcc guidence for 1.8V device - below about 1.1V. (Page 35) 4. Add the specification of Block Lock scheme.(Page 29~32) 5. Pin assignment of TBGA A3 ball is changed. (before) N.C --> (after) Vss 2.0 1. The Maximum operating current is changed. Read : Icc1 20mA-->30mA Program : Icc2 20mA-->40mA Erase : Icc3 20mA-->40mA The min. Vcc value 1.8V devices is changed. K9K12XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V Pb-free Package is added. K9K1208U0C-HCB0,HIB0 K9K12XXQ0C-HCB0,HIB0 K9K1216U0C-HCB0,HIB0 K9K1216Q0C-HCB0,HIB0 Errata is added.(Front Page)-K9K12XXQ0C tWC tWP tRC tREH tRP tREA tCEA Specification 45 25 50 15 25 30 45 Relaxed value 60 40 60 20 40 40 55 1. Max. Thickness of TBGA packge is changed. 0.090.10(Before) --> 1.100.10(After) 2. New definition of the number of invalid blocks is added. (Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.) 1. The guidence of LOCKPRE pin usage is changed. Don't leave it N.C. Not using LOCK MECHANISM & POWER-ON AUTOREAD, connect it Vss.(Before) --> Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it N.C(After) 2. 2.65V device is added. 3. Note is added. (VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.) Jan. 17th 2003 Preliminary
Draft Date
Sep. 12th 2002 Jan. 3rd 2003
Remark
Advance
2.1
Mar. 5th 2003
Preliminary
2.2
Mar. 13rd 2003
2.3
Mar. 17th 2003
2.4
Apr. 4th 2003
2.5
Jul. 4th 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site. http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.
1
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Document Title
64M x 8 Bit , 32M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
2.6 1. tREA value of 1.8V device is changed. K9K12XXQ0C : tREA 30ns --> 35ns 2. Errata is deleted. 1. Command table is edited. 2. AC parameters are changed. tWC tWH tWP tRC tREH tRP tREA tCEA K9K12XXU0C K9K12XXD0C 50 15 25 50 15 25 30 45 K9K12XXQ0C 2.8 60 20 40 60 20 40 40 55 Dec. 17th. 2003
Draft Date
Aug. 20th. 2003
Remark
2.7
Oct. 28th. 2003
1. AC parameters are changed. tWC tWH tWP tRC tREH tRP tREA tCEA K9K1208Q0C 50 15 25 50 15 25 35 45 K9K1216Q0C 60 20 40 60 20 40 40 55 1. The Test Condition for Stand-by Currents are changed. ISB1: CE=VIH, WP=0V/VCC -->> CE=VIH, WP=LOCKPRE=0V/VCC ISB2: CE=VCC-0.2, WP=0V/VCC -->> CE=VCC-0.2, WP=LOCKPRE=0V/VCC 1. NAND Flash Technical Notes is changed. -Invalid block -> initial invalid block ( page 14 ) -Error in write or read operation ( page 15 ) -Program Flow Chart ( page 15 ) 2. TBGA->FBGA
2.9
Apr. 22th 2004
3.0
Oct. 25th. 2004
Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site. http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.
2
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
64M x 8 Bit / 32M x 16 Bit NAND Flash Memory
PRODUCT LIST.
Part Number K9K1208Q0C-G,J K9K1216Q0C-G,J K9K1208D0C-G,J K9K1216D0C-G,J K9K1208U0C-G,J K9K1216U0C-G,J 2.7 ~ 3.6V 2.4 ~ 2.9V Vcc Range 1.70 ~ 1.95V Organization X8 X16 X8 X16 X8 X16 FBGA PKG Type
FEATURES
* Voltage Supply - 1.8V device(K9K12XXQ0C) : 1.70~1.95V - 2.65V device(K9F12XXD0C) : 2.4~2.9V - 3.3V device(K9K12XXU0C) : 2.7 ~ 3.6 V * Organization - Memory Cell Array - X8 device(K9K1208X0C) : (64M + 2048K)bit x 8 bit - X16 device(K9K1216X0C) : (32M + 1024 K)bit x 16bit - Data Register - X8 device(K9K1208X0C) : (512 + 16)bit x 8bit - X16 device(K9K1216X0C) : (256 + 8)bit x16bit * Automatic Program and Erase - Page Program - X8 device(K9K1208X0C) : (512 + 16)Byte - X16 device(K9K1216X0C) : (256 + 8)Word - Block Erase : - X8 device(K9K1208X0C) : (16K + 512)Byte - X16 device(K9K1216X0C) : ( 8K + 256)Word * Page Read Operation - Page Size - X8 device(K9K1208X0C) : (512 + 16)Byte - X16 device(K9K1216X0C) : (256 + 8)Word - Random Access : 10s(Max.) - Serial Page Access : 50ns(Min.)* *K9K1216Q0C : 60ns(Min.) * Fast Write Cycle Time - Program time : 200s(Typ.) - Block Erase Time : 2ms(Typ.) * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years * Command Register Operation * Intelligent Copy-Back * Unique ID for Copyright Protection * Package - K9K12XXX0C-GCB0/GIB0 63- Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.2 mm) - K9K12XXX0C-JCB0/JIB0 63- Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.2 mm) - Pb-free Package
GENERAL DESCRIPTION
Offered in 64Mx8bit or 32Mx16bit, the K9K12XXX0C is 512M bit with spare 16M bit capacity. The device is offered in 1.8V, 2.65V, 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200s on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns(K9K1216Q0C : 60ns) cycle time per byte (X8 device) or word(X16 device). The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K12XXX0Cs extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K12XXX0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
3
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
X8
4
FLASH MEMORY
X16
4
PIN CONFIGURATION (FBGA)
K9K12XXX0C-GCB0,JCB0/GIB0,JIB0
5 6
N.C N.C N.C N.C
/WP NC NC NC NC NC NC Vss ALE /RE NC NC NC I/O0 I/O1 I/O2 Vss CLE NC NC NC NC NC /CE NC NC NC NC NC /WE NC NC NC R/B NC NC NC
1
N.C N.C
2
3
1
N.C N.C
2
3
5
6
N.C N.C N.C N.C
A B
C
N.C
A B
C
N.C
/WP NC NC NC NC ALE /RE NC NC NC Vss CLE NC NC NC /CE NC NC NC I/O5 /WE NC NC NC R/B NC NC NC
D E F G H
D E F G H
NC LOCKPRE NC Vcc I/O7 Vss
I/O7 LOCKPRE Vcc
I/O8 I/O1 I/O10 I/O12 IO14 I/O0 Vss
VccQ I/O5 I/O6
I/O9 I/O3 VccQ I/O6 I/O15 I/O2 I/O11 I/O4 I/O13 Vss
I/O3 I/O4
N.C N.C N.C N.C
N.C N.C N.C N.C
N.C N.C N.C N.C
N.C N.C N.C N.C
PACKAGE DIMENSIONS
(Top View)
(Top View)
63-Ball FBGA (measured in millimeters) Top View Bottom View
9.000.10 0.80 x9= 7.20 0.80 x5= 4.00 9.000.10
(Datum A)
A
6
5
0.80 4
3
2
1
B
#A1
A B
0.80 x11= 8.80
0.80 x7= 5.60 2.00 9.000.10 0.450.05 0.25(Min.)
(Datum B)
C D E
0.80
11.000.10
2.80
F G H
63-0.450.05
0.20 M A B
0.10MAX
4
1.20(Max.)
Side View
11.000.10
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
PIN DESCRIPTION
Pin Name I/O0 ~ I/O7 (K9K1208X0C) I/O0 ~ I/O15 (K9K1216X0C) Pin Function DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 operation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and output. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE control during read operation, refer to 'Page read' section of Device operation . READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage generator is reset when the WP pin is active low. When LOCKPRE is a logic high and WP is a logic low, the all blocks go to lock state. READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. OUTPUT BUFFER POWER VccQ is the power supply for Output Buffer. VccQ is internally connected to Vcc, thus should be biased to Vcc. POWER VCC is the power supply for device. GROUND NO CONNECTION Lead is not internally connected. DO NOT USE Leave it disconnected LOCK MECHANISM & POWER-ON AUTO-READ ENABLE To Enable and disable the Lock mechanism and Power On Auto Read. When LOCKPRE is a logic high, Block Lock mode and Power-On Auto-Read mode are enabled, and when LOCKPRE is a logic low, Block Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on 3.3V device(K9K12XXU0C) Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it N.C
CLE
ALE
CE
RE
WE
WP
R/B
VccQ
Vcc Vss N.C DNU
LOCKPRE
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
5
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Figure 1-1. K9K1208X0C (X8) FUNCTIONAL BLOCK DIAGRAM
VCC VSS A9 - A25 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders
512M + 16M Bit NAND Flash ARRAY
A0 - A7
(512 + 16)Byte x 131072 Page Register & S/A
A8
Command Command Register
Y-Gating
I/O Buffers & Latches
VCC/VCCQ VSS Output Driver I/0 0 I/0 7
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
CLE ALE WP
Figure 2-1. K9K1208X0C (X8) ARRAY ORGANIZATION
1 Block =32 Pages = (16K + 512) Byte
128K Pages (=4,096 Blocks)
1st half Page Register (=256 Bytes)
2nd half Page Register (=256 Bytes)
1 Page = 528 Byte 1 Block = 528 Byte x 32 Pages = (16K + 512) Byte 1 Device = 528Bytes x 32Pages x 4,096 Blocks = 528 Mbits 8 bit 16 Byte
512Byte
Page Register
512 Byte I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A9 A17 A25 I/O 1 A1 A10 A18 *L I/O 2 A2 A11 A19 *L 16 Byte I/O 3 A3 A12 A20 *L
I/O 0 ~ I/O 7
I/O 4 A4 A13 A21 *L
I/O 5 A5 A14 A22 *L
I/O 6 A6 A15 A23 *L
I/O 7 A7 A16 A24 *L Column Address Row Address (Page Address)
NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L must be set to "Low". * The device ignores any additional input of address cycles than reguired.
6
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Figure 1-2. K9K1216X0C (X16) FUNCTIONAL BLOCK DIAGRAM
VCC VSS A9 - A25 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders
512M + 16M Bit NAND Flash ARRAY
A0 - A7
(256 + 8)Word x 131072 Page Register & S/A
Command Command Register
Y-Gating
I/O Buffers & Latches
VCC/VCCQ VSS Output Driver I/0 0 I/0 15
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
CLE ALE WP
Figure 2-2. K9K1216X0C (X16) ARRAY ORGANIZATION
1 Block =32 Pages = (8K + 256) Word
128K Pages (=4,096 Blocks)
Page Register (=256 Words)
1 Page = 264 Word 1 Block = 264 Word x 32 Pages = (8K + 256) Word 1 Device = 264Words x 32Pages x 4096 Blocks = 528 Mbits 16 bit 8 Word
256Word
Page Register
256 Word I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A9 A17 A25 I/O 1 A1 A10 A18 I/O 2 A2 A11 A19 I/O 3 A3 A12 A20 8 Word I/O 4 A4 A13 A21
I/O 0 ~ I/O 15
I/O 5 A5 A14 A22
I/O 6 A6 A15 A23
I/O 7 A7 A16 A24
I/O8 to 15
L* L* L* L*
Column Address Row Address (Page Address)
L*
L*
L*
L*
L*
L*
L*
NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than reguired.
7
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
PRODUCT INTRODUCTION
The K9K12XXX0C is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528(X8 device) or 264(X16 device) columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8 device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 4096 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase operation is prohibited on the K9K12XXX0C. The K9K12XXX0C has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). K9K1216X0C allows sixteen bit wide data transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/Os by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other commands like Page Program and Copy-back Program and Block Erase, require three cycles: one cycle for setup and the other cycle for execution. The 32M-byte(X8 device) or 16M-word(X16 device) physical space requires 25 addresses(X8 device) or 24 addresses(X16 device), thereby requiring four cycles for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K12XXX0C. The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
Function Read 1 Read 2 Read ID Reset Page Program Copy-Back Program Lock Unlock Lock-tight Read Block Lock Status Block Erase Read Status 1st. Cycle 00h/01h(1) 50h 90h FFh 80h 00h 2Ah 23h 2Ch 7Ah 60h 70h 2nd. Cycle 10h 8Ah 24h D0h O O Acceptable Command during Busy
NOTE : 1. The 01h command is available only on X8 device(K9K1208X0C). Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
8
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Rating 1.8V DEVICE -0.6 to + 2.45 -0.2 to + 2.45 -0.2 to + 2.45 -10 to +125 -40 to +125 -65 to +150 5 3.3V/2.65V DEVICE -0.6 to + 4.6 -0.6 to + 4.6 -0.6 to + 4.6 C C mA V
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol VIN/OUT Voltage on any pin relative to VSS K9K12XXX0C-XCB0 K9K12XXX0C-XIB0 K9K12XXX0C-XCB0 K9K12XXX0C-XIB0 VCC VCCQ Temperature Under Bias Storage Temperature Short Circuit Current TBIAS TSTG Ios Unit
NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9K12XXX0C-GCB0,JCB0 :TA=0 to 70C, K9K12XXX0C-GIB0,JIB0:TA=-40 to 85C) Parameter Supply Voltage Supply Voltage Supply Voltage Symbol VCC VCCQ VSS K9K12XXQ0C(1.8V) Min 1.70 1.70 0 Typ. 1.8 1.8 0 Max 1.95 1.95 0 K9K12XXD0C(2.65V) Min 2.4 2.4 0 Typ. 2.65 2.65 0 Max 2.9 2.9 0 K9K12XXU0C(3.3V) Min 2.7 2.7 0 Typ. 3.3 3.3 0 Max 3.6 3.6 0 Unit V V V
9
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
K9K12XXX0C
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Symbol Test Conditions 1.8V 2.65V 3.3V Unit
Min Typ Max Min Typ Max Min Typ Max Sequential OperatRead ing Current Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO tRC=50ns, CE=VIL IOUT=0mA CE=VIH, WP=LOCKPRE=0V/VCC VCCQ -0.4 VCC -0.4 K9K12XXQ0C :IOH=-100A VOH K9K12XXD0C :IOH=-100A K9K12XXU0C :IOH=-400A K9K12XXQ0C :IOL=100uA VOL K9K12XXD0C :IOL=100A K9K12XXU0C :IOL=2.1mA K9K12XXQ0C :VOL=0.1V Output Low Current(R/B) IOL(R/B) K9K12XXD0C :VOL=0.1V K9K12XXU0C :VOL=0.4V 3 4 3 4 8 10 mA 0.1 0.4 0.4 -0.3 VCCQ -0.1 10 10 10 10 20 20 20 1 50 10 10 10 10 10 10 20 20 20 1 50 10 10 VCCQ +0.3 VCC +0.3 0.5 2.0 2.0 -0.3 10 10 10 10 30 40 40 1 50 10 10 VCCQ +0.3 VCC +0.3 0.8 V VCCQ -0.4 2.4 A mA
CE=VCC-0.2, WP=LOCKPRE=0V/VCC VIN=0 to Vcc(max) VOUT=0 to Vcc(max) I/O pins
Input High Voltage
VIH* Except I/O pins
VCCQ VCCQ +0.3 -0.4 Vcc VCC +0.3 -0.4 0.4 -0.3
Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level
VIL*
10
K9K1208Q0C K9K1208D0C K9K1208U0C
VALID BLOCK
Parameter Valid Block Number
K9K1216Q0C K9K1216D0C K9K1216U0C
Symbol NVB Min 4026 Typ. -
FLASH MEMORY
Max 4096 Unit Blocks
NOTE : 1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles. 3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
(K9K12XXX0C-GCB0,JCB0 :TA=0 to 70C, K9K12XXX0C-GIB0,JCB0 :TA=-40 to 85C K9K12XXQ0C : Vcc=1.70V~1.95V , K9K12XXD0C : Vcc=2.4V~2.9V , K9K12XXU0C : Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels K9K12XXQ0C 0V to VccQ 5ns VccQ/2 K9K12XXD0C 0V to VccQ 5ns VccQ/2 K9K12XXU0C 0.4V to 2.4V 5ns 1.5V
K9K12XXQ0C:Output Load (VccQ:1.8V +/-10%) K9K12XXD0C:Output Load (VccQ:2.65V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF K9K12XXU0C:Output Load (VccQ:3.0V +/-10%) K9K12XXU0C:Output Load (VccQ:3.3V +/-10%) 1 TTL GATE and CL=100pF
CAPACITANCE(TA=25C, VCC=1.8V/2.65V/3.3V, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 20 20 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE H L H L L L X X X X X ALE L H L H L L X X X X(1) X CE L L L L L L X X X X H H X X X X X H X X X X WE RE H H H H H LOCKPRE X X X X X X X X X X 0V/VCC(2 WP X X H H H X X H H L Read Mode Write Mode Data Input Data Output During Read(Busy) on the devices During Program(Busy) During Erase(Busy) Write Protect Mode Command Input Address Input(4clock) Command Input Address Input(4clock)
0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby.
11
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
Parameter Symbol tPROG tLBSY Nop tBERS Main Array Spare Array Min Typ 200 5 2
FLASH MEMORY
Max 500 10 2 3 3 Unit s s cycles cycles ms
PROGRAM/ERASE CHARACTERISTICS
Program Time Dummy Busy Time for the Lock or Lock-tight Block Number of Partial Program Cycles in the Same Page Block Erase Time
AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT
Min Parameter Symbol
K9K1208X0C K9K12XXD0C K9K12XXU0C K9K1216Q0C K9K1208X0C K9K12XXD0C K9K12XXU0C
Max
K9K1216Q0C
Unit
CLE setup Time CLE Hold Time CE setup Time CE Hold Time WE Pulse Width ALE setup Time ALE Hold Time Data setup Time Data Hold Time Write Cycle Time WE High Hold Time
tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH
0 10 0 10 25(1) 0 10 20 10 50 15
0 10 0 10 40 0 10 20 10 60 20
-
-
ns ns ns ns ns ns ns ns ns ns ns
NOTE: 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
12
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
AC CHARACTERISTICS FOR OPERATION
Min Parameter Symbol
K9K1208X0C K9K12XXD0C K9K12XXU0C K9K1216Q0C K9K1208X0C K9K12XXD0C K9K12XXU0C
Max
K9K1216Q0C
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE or CE High to Output hold RE High Hold Time Output Hi-Z to RE Low WE High to RE Low WE High to RE Low in Block Lcok Device Resetting Time(Read/Program/Erase)
tR tAR tCLR tRR tRP tWB tRC tREA tCEA tRHZ tCHZ tOH tREH tIR tWHR1 tWHR2 tRST
10 10 20 25 50 15 15 0 60 100 -
10 10 20 40 60 15 20 0 60 100
-
10 100 30/35 45 30 20 5/10/500(2)
(1)
10 100 40 55 30 20 5/10/500(2)
NOTE: 1. K9F5608Q0C tREA = 35ns. 2. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
13
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 6th byte(X8 device) or 1st word(X16 device) in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh(X8 device) or non-FFFFh(X16 device) data at the column address of 517(X8 device) or 256 and 261(X16 device). Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
*
Create (or update) Initial Invalid Block(s) Table No Check "FFh" ? Yes No
Check "FFh" at the column address 517(X8 device) or 256 and 261(X16 device) of the 1st and 2nd page in the block
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
14
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks. Failure Mode Write Read Erase Failure Program Failure Single Bit Failure Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Verify ECC -> ECC Correction
ECC
: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ?
No
Program Error
*
Yes Program Completed
*
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.
15
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Start Write 60h Write Block Address Write D0h Read Status Register
Read Flow Chart
Start Write 00h Write Address Read Data ECC Generation
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Erase Completed
No
Reclaim the Error
No
Verify ECC Yes Page Read Completed
Erase Error
*
*
: If erase operation results in an error, map out the failing block and replace it with another block.
Block Replacement
1st (n-1)th nth (page)
{ {
Block A 2 an error occurs. Buffer memory of the controller. Block B 1
1st (n-1)th nth (page)
* Step1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2 Copy the nth page data of the Block 'A' in the buffer memory to the nth page of another free block. (Block 'B') * Step3 Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block 'B'. * Step4 Do not further erase Block 'A' by creating an 'invalid Block' table or other appropriate scheme.

16
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Pointer Operation of K9K1208X0C(X8)
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. '00h' command sets the pointer to 'A' area(0~255byte), '01h' command sets the pointer to 'B' area(256~511byte), and '50h' command sets the pointer to 'C' area(512~527byte). With these commands, the starting column address can be set to any of a whole page(0~527byte). '00h' or '50h' is sustained until another address pointer command is inputted. '01h' command, however, is effective only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with '01h' command, the address pointer returns to 'A' area by itself. To program data starting from 'A' or 'C' area, '00h' or '50h' command must be inputted before '80h' command is written. A complete read operation prior to '80h' command is not necessary. To program data starting from 'B' area, '01h' command must be inputted right before '80h' command is written.
Table 2. Destination of the pointer
Command 00h 01h 50h Pointer position 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte Area 1st half array(A) 2nd half array(B) spare array(C)
"A" area (00h plane) 256 Byte "B" area (01h plane) 256 Byte "C" area (50h plane) 16 Byte
"A"
"B"
"C" Internal Page Register
Pointer select commnad (00h, 01h, 50h)
Pointer
Figure 4. Block Diagram of Pointer Operation
(1) Command input sequence for programming 'A' area
The address pointer is set to 'A' area(0~255), and sustained Address / Data input 00h 80h 10h 00h 80h Address / Data input 10h
'A','B','C' area can be programmed. It depends on how many data are inputted.
'00h' command can be omitted.
(2) Command input sequence for programming 'B' area
The address pointer is set to 'B' area(256~511), and will be reset to 'A' area after every program operation is executed. Address / Data input 01h 80h 10h 01h 80h Address / Data input 10h
'B', 'C' area can be programmed. It depends on how many data are inputted.
'01h' command must be rewritten before every program operation
(3) Command input sequence for programming 'C' area
The address pointer is set to 'C' area(512~527), and sustained Address / Data input 50h 80h 10h 50h 80h Address / Data input 10h
Only 'C' area can be programmed.
'50h' command can be omitted.
17
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Pointer Operation of K9K1216X0C(X16)
Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. '00h' command sets the pointer to 'A' area(0~255word), and '50h' command sets the pointer to 'B' area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). '00h' or '50h' is sustained until another address pointer command is inputted. To program data starting from 'A' or 'B' area, '00h' or '50h' command must be inputted before '80h' command is written. A complete read operation prior to '80h' command is not necessary.
Table 3. Destination of the pointer
Command 00h 50h Pointer position 0 ~ 255 word 256 ~ 263 word Area main array(A) spare array(B)
"A" area (00h plane) 256 Word "B" area (50h plane) 8 Word
"A"
"B" Internal Page Register
Pointer select command (00h, 50h)
Pointer
Figure 5. Block Diagram of Pointer Operation
(1) Command input sequence for programming 'A' area
The address pointer is set to 'A' area(0~255), and sustained Address / Data input 00h 80h 10h 00h 80h Address / Data input 10h
'A','B' area can be programmed. It depends on how many data are inputted.
'00h' command can be omitted.
(2) Command input sequence for programming 'B' area
The address pointer is set to 'B' area(256~263), and sustained Address / Data input 50h 80h 10h 50h 80h Address / Data input 10h
Only 'B' area can be programmed.
'50h' command can be omitted.
18
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
System Interface Using CE don't-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte(x8 device), 264word(x16 device) page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 6. Program Operation with CE don't-care.
CLE
CE don't-care
CE
WE ALE I/Ox
80h Start Add.(4Cycle)
Data Input
Data Input
10h
tCS CE
tCH CE
tCEA
tWP WE
RE
tREA tOH
I/O0~15
out
Figure 7. Read Operation with CE don't-care.
CLE
CE don't-care
CE
RE ALE R/B tR
WE I/Ox
00h Start Add.(4Cycle) Data Output(sequential)
19
K9K1208Q0C K9K1208D0C K9K1208U0C
Device
K9K1216Q0C K9K1216D0C K9K1216U0C
I/O I/Ox I/O 0 ~ I/O 7 I/O 0 ~ I/O 15
1)
FLASH MEMORY
DATA Data In/Out ~528byte ~264word
K9K1208X0C(X8 device) K9K1216X0C(X16 device)
NOTE: 1. I/O8~15 must be set to "0" during command or address input. I/O8~15 are used only for data bus.
Command Latch Cycle
CLE tCLS tCS CE tCLH tCH
WE
tWP
tALS ALE tDS I/Ox
tALH
tDH
Command
Address Latch Cycle
tCLS CLE
tCS CE
tWC
tWC
tWC tCH
tWP WE tALS ALE tDS I/OX tDH tWH tALH tALS
tWP tWH tALH tALS
tWP tWH tALH tALS
tWP tALH
tDS
tDH
tDS
tDH
tDS
A25
tDH
A0~A7
A9~A16
A17~A24
20
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Input Data Latch Cycle
tCLH CLE
tCH CE
tALS ALE
tWC
WE tDS I/Ox
tWH tDH
tDS
tDH
tWP
tWP
tWP tDH
tDS
DIN 0 DIN 1 DIN n tRC
Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
CE tREA RE
tREH tRP
tRHZ* I/Ox tRR R/B Dout Dout
tREA
tREA
tCHZ* tOH
tRHZ* tOH Dout
NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
21
K9K1208Q0C K9K1208D0C K9K1208U0C
Status Read Cycle
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
tCLR CLE tCLS tCS CE tCH tCEA tWHR1 RE tDS I/Ox 70h tDH tIR tREA tRHZ tOH Status Output tCHZ tOH tCLH
tWP WE
READ1 OPERATION(READ ONE PAGE)
CLE
CE tWC WE tWB tAR ALE tR RE N Address tRR I/OX
00h or 01h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25 Dout N Dout N+1 Dout N+2
tCHZ tOH
tRC
tRHZ tOH
Dout m
1)
Column Address
Page(Row) Address Busy
R/B
X8 device : m = 528 , Read CMD = 00h or 01h X16 device : m = 264 , Read CMD = 00h
22
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Read1 Operation(Intercepted by CE)
CLE
CE
WE tWB tAR ALE tR RE tRR I/OX
00h or 01h
tCHZ tOH tRC
A0 ~ A7
A9 ~ A16
A17 ~ A24
A25
Dout N
Dout N+1
Dout N+2
Column Address
Page(Row) Address Busy
R/B
Read2 Operation(Read One Page)
CLE
CE
WE tWB ALE
tR tAR tRR
RE
I/OX
50h
A0 ~ A7
A9 ~ A16 A17 ~ A24
A25
Dout n+M
n+m
R/B M Address
A0~A3 : Valid Address A4~A7 : Dont care
Selected Row
512
16 Start address M
23
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Page Program Operation
CLE
CE
WE tWB ALE tPROG
RE
Din Din 10h N 527 1 up to 528 Byte Data Program Command Serial Input
I/OX
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24 Page(Row) Address
A25
tWC
tWC
tWC
70h Read Status Command
I/O0
Sequential Data Column Input Command Address
24
R/B
I/O0=0 Successful Program I/O0=1 Error in Program
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Copy-Back Program Operation
CLE
CE tWC WE tWB tWB tPROG
ALE tR RE
I/OX
00h
A0~A7 A9~A16 A17~A24 Column Address Page(Row) Address
A25
8Ah
A0~A7 A9~A16 A17~A24 Column Address Page(Row) Address
A25
10h
70h
I/O0
Read Status Command
Busy
Copy-Back Data Input Command
I/O0=0 Successful Program I/O0=1 Error in Program
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE tWC WE tWB ALE tBERS
RE
I/OX
60h
A9 ~ A16 A17 ~ A24 Page(Row) Address
A25
DOh
70h
Busy
I/O 0
R/B
R/B
Auto Block Erase Setup Command Erase Command
Busy
Read Status Command
I/O0=0 Successful Erase I/O0=1 Error in Erase
25
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE tAR RE tREA I/Ox
90h Read ID Command 00h Address. 1cycle ECh Maker Code Device Code* Device Code
Device K9K1208Q0C K9K1208D0C K9K1208U0C K9K1216Q0C K9K1216D0C K9K1216U0C
Device Code* 36h 76h 76h XX46h XX56h XX56h
26
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operations are available : random read, serial page read. The random read mode is enabled when the page address is changed. The 528 bytes(X8 device) or 264 words(X16 device) of data within the selected page are transferred to the data registers in less than 10s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address[column 511/ 527(X8 device) 255 /263(X16 device) depending on the state of GND input pin]. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512 ~527 bytes(X8 device) or 256~263 words(X16 device) may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A0~A3(X8 device) or A0~A2(X16 device) set the starting address of the spare area while addresses A4~A7 are ignored in X8 device case or A3~A7 must be "L" in X16 device case. The Read1 command is needed to move the pointer back to the main area. Figures 8, 9 show typical sequence and timings for each read operation.
Figure 8. Read1 Operation
CLE CE WE ALE R/B RE I/Ox
00h Start Add.(4Cycle) (00h Command) Main array Data Output(Sequential)
tR
X8 device : A0 ~ A7 & A9 ~ A25 X16 device : A0 ~ A7 & A9 ~ A25
1)
(01h Command) 1st half array 2st half array
Data Field
Spare Field
Data Field
Spare Field
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 01h command is only available on X8 device(K9K1208X0C).
27
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Figure 9. Read2 Operation
CLE CE WE ALE R/B RE I/Ox
50h Start Add.(4Cycle) X8 device : A0 ~ A3 & A9 ~ A25 X16 device : A0 ~ A2 & A9 ~ A25 X8 device : A4 ~ A7 Don't care X16 device : A3 ~ A7 are "L" Data Output(Sequential) Spare Field
tR
Main array
Data Field
Spare Field
28
K9K1208Q0C K9K1208D0C K9K1208U0C
PAGE PROGRAM
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive bytes/words up to 528(X8 device) or 264(X16 device), in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes(X8 device) or 264 words(X16 device) of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 10. Program Operation
R/B I/Ox
80h Address & Data Input
tPROG
10h
70h
I/O0
Pass
Fail
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with "00h" command with the address of the source page moves the whole 528bytes/264words(X8 device:528bytes, X16 device:264words) data into the internal buffer. As soon as the Flash returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page followed. The data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the memory array is internally partitioned into four different planes, copy-back program is allowed only within the same memory plane. Thus, A14 and A25, the plane address, of source and destination page address must be the same."When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back operations could also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation."
Figure 11. Copy-Back Program Operation
R/B I/Ox
00h Add.(4Cycles) Source Address
tR
tPROG
8Ah
Add.(4Cycles) Destination Address
70h
I/O0
Pass
Fail
29
K9K1208Q0C K9K1208D0C K9K1208U0C
BLOCK ERASE
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A14 to A25 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
Figure 12. Block Erase Operation
R/B I/Ox
60h
tBERS
Address Input(3Cycle) Block Add. : A9 ~ A25
D0h
70h
I/O0
Pass
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before serial access cycle.
Table4. Read Status Register Definition
I/O # I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8~15 Device Operation Write Protect Not use Reserved for Future Use Status Program / Erase Definition "0" : Successful Program / Erase "1" : Error in Program / Erase "0" "0" "0" "0" "0" "0" : Busy "0" : Protected Don't care "1" : Ready "1" : Not Protected
30
K9K1208Q0C K9K1208D0C K9K1208U0C
READ ID
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 13 shows the operation sequence.
Figure 13. Read ID Operation
CLE tCEA CE WE tAR ALE RE I/Ox
00h Address. 1cycle
tWHR1
tREA
90h
ECh Maker code
Device Code* Device code
Device K9K1208Q0C K9K1208D0C K9K1208U0C K9K1216Q0C K9K1216D0C
Device Code* 36h 76h 76h XX46h XX56h XX56h
RESET
K9K1216U0C
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 14 below.
Figure 14. RESET Operation
R/B I/Ox
FFh
tRST
Table5. Device Status
After Power-up Operation Mode Read 1 After Reset Waiting for next command
31
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
> In high state of LOCKPRE pin, Block lock mode and Power on Auto read are enabled, otherwise it is regarded as NAND Flash without LOCKPRE pin.
Block Lock Mode
Block Lock mode is enabled while LOCKPRE pin state is high, which is to offer protection features for NAND Flash data. The Block Lock mode is divided into Unlock, Lock, Lock-tight operation. Consecutive blocks protects data by allowing those blocks to be locked or lock-tighten with no latency. This block lock scheme offers two levels of protection. The first allows software control(command input method) of block locking that is useful for frequently changed data blocks, while the second requires hardware control(WP low pulse input method) before locking can be changed that is useful for protecting infrequently changed code blocks. The followings summarized the locking functionality. - All blocks are in a locked state on power-up. Unlock sequence can unlock the locked blocks. - The Lock-tight command locks blocks and prevents from being unlocked. And Lock-tight state can be returned to lock state only by Hardware control(WP low pulse input).
1. Block lock operation
1) Lock
- Command Sequence: Lock block Command(2Ah) - All blocks default to locked by power-up and Hardware control(WP low pulse input) - Partial block lock is not available; Lock block operation is based on all block unit - Unlocked blocks can be locked by using the Lock block command, and a lock block's status can be changed to unlock or lock-tight using the appropriate commands
WP CLE
CE
WE I/Ox
2Ah Lock Command
32
K9K1208Q0C K9K1208D0C K9K1208U0C
2) Unlock
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
- Command Sequence: Unlock block Command(23h) + Start block address + Command(24h) + End block address - Unlocked blocks can be programmed or erased. - An unlocked block's status can be changed to the locked or lock-tighten state using the appropriate commands. - Only one consecutive area can be released to unlock state from lock state; Unlocking multi area is not available. - Start block address must be nearer to the logical LSB(Least Significant Bit) than End blcok address. - One block is selected for unlocking block when Start block address is same as End block address.
WP CLE
CE
WE
ALE I/Ox
23h Unock Command Add.1 Add.2 Add.1 Add.2 Add.3
Add.3
24h Unlock Command
Start Block Address 3cycles
End Block Address 3 cycles
3) Lock-tight
- Command Sequence: Lock-tight block Command(2Ch) - Lock-tighten blocks offer the user an additional level of write protection beyond that of a regular lock block. A block that is locktighten can't have it's state changed by software control, only by hardware control(WP low pulse input); Unlocking multi area is not available - Only locked blocks can be lock-tighten by lock-tight command.
WP CLE
CE
WE I/Ox
2Ch Lock-tight Command
33
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
WPx = H & Unlock block Command (23h) + Start Block Address + Command (24h) + End Block Address
Lock unlock Lock WPx = H & Lock block command (2Ah) Block Lock reset WPx = L (>100ns) Lock WPx = H & Lock-tight block command (2Ch) WPx = H & Unlock block Command (23h) + Start Block Address + Command (24h) + End Block Address
Power-up
Block Lock reset WPx = L (>100ns) Lock-tight
Lock
unlock
WPx = H & Lock-tight block command (2Ch)
Lock
Lock-tight unlock Lock-tight
Figure 15. State diagram of Block Lock
Program/Erase OPERATION(In Locked or Lock-tighten Block)
R/B I/Ox
60h(80h) Address(&Data Input)
tLBSY
D0h(10h)
Locked or Lock-tighten Block address
On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10s(tLBSY)
34
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
2. Block Lock Status Read
Block Lock Status can be read on a block basis, which may be read to find out whether designated block is available to be programmed or erased. After writing 7Ah command to the command register. and block address to be checked, a read cycle outputs the content of the Block Lock Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Blcok Lock Status Read is prohibited while the device is busy state. Refer to table 6 for specific Status Register definitions. The command register remains in Block Lock Status Read mode until further commands are issued to it. In high state of LOCKPRE pin, write protection status can be checked by Block Lock Status Read(7Ah) while in low state by Status Read(70h).
IO7~IO3 Read 1) block case Read 2) block case Read 3) block case Read 4) block case X X X X
IO2(Unlock) 0 1 0 1
IO1(Lock) 1 1 0 0
IO0(Lock-tight) 0 0 1 1
(1)Lock (2)unlock (1)Lock
(3)Lock-tight (4)unlock (3)Lock-tight (1)Lock (2)Unlock (3)Lock-tight
Table6. Block Lock Status Register definitions
WP CLE
CE
WE
ALE tWHR2 RE I/Ox
7Ah Read Block Lock status Command
Add.1
Add.2
Add.3
Dout Block Lock Status
Block Address 3cycle
35
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Power-On Auto-Read
The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. LOCKPRE pin controls activation of auto- page read function. Auto-page read function is enabled only when LOCKPRE pin is logic high state. Serial access may be done after power-on without latency. Power-On Auto Read mode is available only on 3.3V device(K9K12XXU0C).
Figure 16. Power-On Auto-Read (3.3V device only)
~ 1.8V VCC CLE CE WE ALE LOCKPRE R/B RE I/OX
1st 2nd 3rd
tR
....
n th
36

K9K1208Q0C K9K1208D0C K9K1208U0C
READY/BUSY
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can be determined by the following guidance.
Rp VCC
ibusy 1.8V device - VOL : 0.1V, VOH : VccQ-0.1V 2.65V device - VOL : 0.4V, VOH : VccQ-0.4V 3.3V device - VOL : 0.4V, VOH : 2.4V VOH
Ready Vcc R/B open drain output
CL
VOL Busy tf tr
GND Device
Figure 17. Rp vs tr ,tf & Rp vs ibusy
37
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
@ Vcc = 1.8V, Ta = 25C , CL = 30pF
FLASH MEMORY
tr,tf [s]
300n
1.7
Ibusy
3m
Ibusy [A]
Ibusy [A]
200n 100n
2m tr
0.85 60 90 0.57 1.7 120
30 1.7
0.43 1.7
1m
tf
1.7
1K
2K
3K Rp(ohm)
4K
@ Vcc = 2.65V, Ta = 25C , CL = 30pF
tr,tf [s]
300n
Ibusy
1.1
200n 100n
30 2.3
2m
90 0.75 2.3 120
tr tf
60 2.3
1m
2.3 0.55
1K
2K
3K Rp(ohm)
4K
@ Vcc = 3.3V, Ta = 25C , CL = 100pF
2.4 400
tr,tf [s]
300n
Ibusy
1.2 200 300
3m
200n tr 100n
100 3.6 tf
0.8 0.6
2m 1m
3.6
3.6
3.6
1K
2K
Rp value guidance
Rp(min, 1.8V part) = VCC(Max.) - VOL(Max.) IOL + IL VCC(Max.) - VOL(Max.) IOL + IL VCC(Max.) - VOL(Max.) IOL + IL
3K Rp(ohm) 1.85V =
4K
3mA + IL 2.5V
Rp(min, 2.65V part) =
=
3mA + IL 3.2V
Rp(min, 3.3V part) =
=
8mA + IL
where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr
38
Ibusy [A]
2.3
3m
K9K1208Q0C K9K1208D0C K9K1208U0C
K9K1216Q0C K9K1216D0C K9K1216U0C
FLASH MEMORY
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10s is required before internal circuit gets ready for any command sequences as shown in Figure 18. The two step command sequence for program/erase provides additional software protection.
Figure 18. AC Waveforms for Power Transition
1.8V device : ~ 1.5V 2.65V device : ~ 2.0V 3.3V device : ~ 2.5V VCC High 1.8V device : ~ 1.5V 2.65V device : ~ 2.0V 3.3V device : ~ 2.5V
WP
WE
39
10s

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