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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Document Title 128M x 8 Bit NAND Flash Memory Revision History
Revision No
0.0 0.1 0.2
FLASH MEMORY
History
1. Initial issue 1.[Page 31] device code (76h) --> device code (79h) 1.Powerup sequence is added : Recovery time of minimum 1s is required before internal circuit gets ready for any command sequences
Draft Date
Apr. 7th 2001 Jul. 3rd 2001
Remark
Jul. 23th 2001
2.5V VCC High
2.5V
W P
W E
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added. 3. [Page28] Only address A 14 to A25 is valid while A9 to A13 is ignored --> Only address A14 to A26 is valid while A 9 to A13 is ignored 0.3 (page 30) Sep. 13th 2001 A14 and A15 must be the same between source and target page --> A14 , A15 and A26 must be the same between source and target page
Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site. http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
128M x 8 Bit NAND Flash Memory
Features
* Voltage Supply : 2.7V~3.6V * Organization - Memory Cell Array : (128M + 4,096K)bit x 8bit - Data Register : (512 + 16)bit x8bit multipled by eight planes * Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte * 528-Byte Page Read Operation - Random Access : 12 s(Max.) - Serial Page Access : 50ns(Min.) * Fast Write Cycle Time - Program time : 200s(Typ.) - Block Erase Time : 2ms(Typ.) * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years * Command Register Operation * Intelligent Copy-Back Operation * Package : - K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 : 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) * Simultaneous Four Page/Block Program/Erase
FLASH MEMORY
General Description
The K9K1G08U0M is a 128M(134,217,728)x8bit NAND Flash Memory with a spare 4.096K(4,194,304)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 200s on the 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K1G08U0M's extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K1G08U0M-YCB0/YIB0 is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
Pin Configuration
N.C N.C N.C N.C N.C N.C R/ B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
Pin Description
Pin Name I/O0 ~ I/O7 CLE ALE CE RE WE WP R/B VCC VSS N.C Pin Function Data Input/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Ready/Busy output Power(+2.7V~3.6V) Ground No Connection
48-pin TSOP1 Standard Type 12mm x 20mm
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Figure 1. Functional Block Diagram
VCC VSS A9 - A 26 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders
FLASH MEMORY
1,024M + 32M Bit NAND Flash ARRAY
A0 - A7
(512 + 16)Byte x 262,144 Page Register & S/A
A8
Command Command Register
Y-Gating
I/O Buffers & Latches
VCC VSS I/0 0 I/0 7
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
Output Driver
CLE ALE WP
Figure 2. Array Organization
1 Block = 32 Pages (16K + 512) Byte
256K Pages (=8,192 Blocks)
1st half Page Register (=256 Bytes)
2nd half Page Register (=256 Bytes)
1 Page = 528 Bytes 1 Block = 528 B x 32 Pages = (16K + 512) Bytes 1 Device = 528B x 32Pages x 8,192 Blocks = 1,056 Mbits 8 bit
512B Bytes
16 Bytes
Page Register
512 Bytes 16 Bytes
I/O 0 ~ I/O 7
I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A9 A17 A25
I/O 1 A1 A10 A18 A26
I/O 2 A2 A11 A19 *L
I/O 3 A3 A12 A20 *L
I/O 4 A4 A13 A21 *L
I/O 5 A5 A14 A22 *L
I/O 6 A6 A15 A23 *L
I/O 7 A7 A16 A24 *L Column Address Row Address (Page Address)
NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L must be set to "Low". * The device ignores any additional input of address cycles than reguired.
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Product Introduction
FLASH MEMORY
The K9K1G08U0M is a 1,026Mbit(1,107,296,436 bit) memory organized as 262,144 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by two NAND structures, totaling 16,384 NAND structures of 16 cells. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 8,192 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K1G08U0M. The K9K1G08U0M has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 128M byte physical space requires 27 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific c ommands into the command register. Table 1 defines the specific commands of the K9K1G08U0M. The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 128Mbit separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining the conventional 512 byte structure. The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block ou t of selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burstreading and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function Read 1 Read 2 Read ID Reset Page Program (True)
(2)
1st. Cycle 00h/01h (1) 50h 90h FFh 80h 80h
(2)
2nd. Cycle 10h 11h 8Ah 8Ah D0h D0h -
3rd. Cycle 10h 11h -
Acceptable Command during Busy
O
Page Program (Dummy)(2) Copy-Back Program(True)
00h 03h 60h 60h----60h 70h 71h (3)
Copy-Back Program(Dummy) (2) Block Erase Multi-Plane Block Erase Read Status Read Multi-Plane Status
O O
NOTE : 1. The 00h command defines starting address of the 1st half of registers. The 01h command defines starting address of the 2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation. Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation. 3. The 71h command should be used for read status of Multi Plane operation. Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Memory Map
FLASH MEMORY
The device is arranged in eight 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory array into plane 0~3 or plane 4~7 separately. For example, multi-plane program/erase operations into plane 2,3,4 and 5 are prohibited.
Figure 3. Memory Array Map
Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block)
Block 0 Page 0 Page 1
Block 1 Page 0 Page 1
Block 2 Page 0 Page 1
Block 3 Page 0 Page 1
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Block 4092 Page 0 Page 1
Block 4093 Page 0 Page 1
Block 4094 Page 0 Page 1
Block 4095 Page 0 Page 1
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
Plane 4 (1024 Block)
Plane 5 (1024 Block)
Plane 6 (1024 Block)
Plane 7 (1024 Block)
Block 4096 Page 0 Page 1
Block 4097 Page 0 Page 1
Block 4098 Page 0 Page 1
Block 4099 Page 0 Page 1
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Block 8188 Page 0 Page 1
Block 8189 Page 0 Page 1
Block 8190 Page 0 Page 1
Block 8191 Page 0 Page 1
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Pin Description
Command Latch Enable(CLE)
FLASH MEMORY
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising ed ge of WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode. However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. The WE must be held high when outputs are activated.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
Ready/Busy(R/B)
The R/ B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS K9K1G08U0M-YCB0 K9K1G08U0M-YIB0 Storage Temperature TSTG Symbol VIN VCC Temperature Under Bias TBIAS Rating
FLASH MEMORY
Unit V C C
-0.6 to + 4.6 -0.6 to + 4.6 -10 to +125 -40 to +125 -65 to +150
NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V +0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. CC, 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
(Voltage reference to GND, K9K1G08U0M-YCB0 Parameter Supply Voltage Supply Voltage Symbol VCC VSS
:TA=0 to 70C, K9K1G08U0M-YIB0:TA=-40 to 85C)
Min 2.7 0 Typ. 3.3 0 Max 3.6 0 Unit V V
Dc and Operating Characteristics(Recommended operating conditions otherwise noted.)
Parameter Operating Current Sequential Read Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOL(R/B) IOH=-400A IOL=2.1mA VOL=0.4V Test Conditions tRC=50ns, CE = VIL, IOUT=0mA CE=VIH, WP= 0V/V CC CE=VCC-0.2, WP = 0V/V CC VIN=0 to 3.6V VOUT=0 to 3.6V Min 2.0 -0.3 2.4 8 Typ 10 10 10 10 10 Max 30 30 30 1 50 10 10 VCC+0.3 0.8 0.4 mA V A mA Unit
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Valid Block
Parameter Valid Block Number Symbol NVB Min 8,052 Typ. -
FLASH MEMORY
Max 8,192 Unit Blocks
NOTE : 1. The K9K1G08U0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for an appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correcti on.
AC Test Condition
(K9K1G08U0M-YCB0 :TA=0 to 70C, K9K1G08U0M-YIB0:TA=-40 to 85C, VCC=2.7V~3.6V unless otherwise) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (3.0V +/-10%) Output Load (3.3V +/-10%) Value 0.4V to 2.4V 5ns 1.5V 1 TTL GATE and CL=50pF 1 TTL GATE and CL=100pF
Capacitance(TA=25C, VCC=3.3V, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V V I N=0V Min Max 20 20 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE H L H L L L L X X X X ALE L H L H L L L X X X
(1)
CE L L L L L L L X X X H
WE
RE H H H H H
WP X X H H H X Data Input Write Mode Read Mode
Mode Command Input Address Input(4clock) Command Input Address Input(4clock)
H H X X X X H X X X X
Sequential Read & Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by
X H H L 0V/VCC(2)
X
NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby.
Program / Erase Characteristics
Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time Main Array Spare Array Symbol tPROG tDBSY Nop tBERS Min Typ 200 1 2 Max 500 10 1 2 3 Unit s s cycle cycles ms
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
AC Timing Characteristics for Command / Address / Data Input
Parameter CLE setup Time CLE Hold Time CE setup Time CE Hold Time WE Pulse Width ALE setup Time ALE Hold Time Data setup Time Data Hold Time Write Cycle Time WE High Hold Time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH Min 0 10 0 10 25 (1) 0 10 20 10 50 15
FLASH MEMORY
Max Unit ns ns ns ns ns ns ns ns ns ns ns
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter Data Transfer from Cell to Register ALE to RE Delay( ID read ) ALE to RE Delay(Read cycle) CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High Hold Time Output Hi-Z to RE Low Last RE High to Busy(at sequential read) CE High to Ready(in case of interception by CE at read) CE Access Time CE High Hold Time(at the last serial read) (2) WE High to RE Low Device Resetting Time(Read/Program/Erase) Symbol tR tAR1 tAR2 tCLR tRR tRP tWB tRC tREA tRHZ tCHZ tREH tIR tRB tCRY tCEA tCEH tWHR tRST Min 10 50 50 20 30 50 15 15 0 100 60 Max 12 100 35 30 20 100 50 +tr(R/B) (1) 45 5/10/500 (3) Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/ B pin. 2. To break the sequential read cycle, CE must be held high for longer time than tCEH. 3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
NAND Flash Technical Notes
Invalid Block(s)
FLASH MEMORY
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The i nformation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to be a valid block. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The i nvalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invali d block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update) Invalid Block(s) Table
No
*
Check "FFh" ? Yes
Check "FFh" at the column address 517 of the 1st and 2nd page in the block
No
Last Block ?
Yes
End
Figure 4. Flow chart to create invalid block table.
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
NAND Flash Technical Notes (Continued)
Error in write or read operation
FLASH MEMORY
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the ac tual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Erase Failure Write Program Failure Single Bit Failure
Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Read back ( Verify after Program) --> Block Replacement or ECC Correction Verify ECC -> ECC Correction
Read
ECC
: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification operation is not needed. Start Write 00h
Write 80h
Write Address
Write Address
Write Data
Wait for tR Time
Write 10h
Verify Data
No
*
Program Error
Read Status Register
Yes Program Completed
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ?
No
*
*
Program Error
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.
Yes
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Start Write 60h Write Block Address Write D0h Read Status Register
FLASH MEMORY
Read Flow Chart
Start Write 00h Write Address Read Data ECC Generation
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Erase Completed
No
Reclaim the Error
No
Verify ECC Yes Page Read Completed
*
Erase Error
*
: If erase operation results in an error, map out the failing block and replace it with another block.
Block Replacement
1st (n-1)th nth (page)
{ {
Block A 2 an error occurs. Buffer memory of the controller. Block B 1
1st (n-1)th nth (page)
* Step1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2 Copy the nth page data of the Block 'A' in the buffer memory to the nth page of another free block. (Block 'B') * Step3 Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block 'B'. * Step4 Do not erase or program to Block 'A' by creating an 'invalid Block' table or other appropriate scheme.

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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Pointer Operation of K9K1G08U0M
FLASH MEMORY
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. '00h' command sets the pointer to 'A' area(0~255byte), '01h' command sets the pointer to 'B' area(256~511byte), and '50h' command sets the pointer to 'C' area(512~527byte). With these commands, the starting column address can be set to any of a whole page(0~527byte). '00h' or '50h' is sustained until another address pointer command is inputted. '01h' command, however, is effec tive only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with '01h' command, the address pointer returns to 'A' area by itself. To program data starting from 'A' or 'C' area, '00h' or '50h' command must be inputted before '80h' command is written. A complete read operation prior to '80h' command is not necessary. To program data starting from 'B' area, '01h' command must be inputted right before '80h' command is written.
"A" area (00h plane)
"B" area (01h plane) 256 Byte
"C" area (50h plane) 16 Byte
Table 2. Destination of the pointer Command 00h 01h 50h Pointer position 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte Area 1st half array(A) 2nd half array(B) spare array(C)
256 Byte
"A"
"B"
"C" Internal Page Register
Pointer select commnad (00h, 01h, 50h)
Pointer
Figure 5 Block Diagram of Pointer Operation
(1) Command input sequence for programming 'A' area
The address pointer is set to 'A' area(0~255), and sustained Address / Data input 00h 80h 10h 00h 80h Address / Data input 10h
'A','B','C' area can be programmed. It depends on how many data are inputted.
'00h' command can be omitted.
(2) Command input sequence for programming 'B' area
The address pointer is set to 'B' area(256~512), and will be reset to 'A' area after every program operation is executed. Address / Data input 01h 80h 10h 01h 80h Address / Data input 10h
'B', 'C' area can be programmed. It depends on how many data are inputted.
'01h' command must be rewritten before every program operation
(3) Command input sequence for programming 'C' area
The address pointer is set to 'C' area(512~527), and sustained Address / Data input 50h 80h 10h 50h 80h Address / Data input 10h
Only 'C' area can be programmed.
'50h' command can be omitted.
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
System Interface Using CE don't-care.
FLASH MEMORY
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 6. Program Operation with CE don't-care.
CLE
CE don't-care
CE
WE ALE
I/O0~7
80h
Start Add.(4Cycle)
Data Input
Data Input
10h
tCS CE
tCH CE
tCEA
tREA tWP WE I/O0~7 out RE
Figure 7. Read Operation with CE don't-care.
CLE
CE don't-care
CE
Must be held low during tR.
RE ALE R/B tR
WE I/O0~7
00h
Start Add.(4Cycle)
Data Output(sequential)
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
* Command Latch Cycle
FLASH MEMORY
CLE tCLS tCS CE tCLH tCH
tWP WE
tALS ALE tDS I/O0~7
tALH
tDH
Command
* Address Latch Cycle
tCLS CLE
tCS CE
tWC
tWC
tWC
tWP WE tALS ALE tDS I/O0~7 tDH tWH tALH tALS
tWP tWH tALH tALS
tWP tWH tALH tALS
tWP tALH
tDS
tDH
tDS
tDH
tDS
tDH
A0~A7
A9~A16
A17~A24
A25,,A26
15
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
* Input Data Latch Cycle
tCLH CLE
FLASH MEMORY
tCH CE
tALS ALE
tWC
tWP WE tDS I/O0~7 tWH tDH
tWP
tDH
tWP tDH
tDS
tDS
DIN 0
DIN 1
DIN 511
* Serial Access Out Cycle after Read(CLE=L, WE=H, ALE=L)
tREH RE tRHZ*
CE
tRC tCHZ*
tREA
tREA
tREA
tRHZ* I/O0~7 tRR R/B Dout Dout
Dout
NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
16
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
* Status Read Cycle
tCLR CLE tCLS tCS CE tCH tWP WE tWHR RE tDS I/O0~7 70h tDH tIR tREA tCEA tCLH
FLASH MEMORY
tCHZ*
tRHZ* Status Output
Read1 Operation(Read One Page)
CLE tCEH CE tWC WE tWB tAR2 ALE tR RE tRR I/O0~7
00h or 01h A0 ~ A 7 A 9 ~ A16 A17 ~ A24 A25,A 2 6 Dout N Dout N+1 Dout N+2
tCHZ
tCRY
tRC
tRHZ
Dout 527
Column Address
Page(Row) Address Busy
tRB
R/B
17
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Read1 Operation(Intercepted by CE)
CLE
FLASH MEMORY
CE
WE tWB tAR2 ALE tR RE tRR I/O0~7
00h or 01h
tCHZ
tRC
A0 ~ A 7
A9 ~ A 16
A 17 ~ A 24
A25,A 2 6
Dout N
Dout N+1
Dout N+2
Column Address
Page(Row) Address Busy
R/B
Read2 Operation(Read One Page)
CLE
CE
WE tWB ALE
tR tAR2 tRR
RE
I/O0~7
50h
A 0 ~ A7
A 9 ~ A16
A17 ~ A24
A25, A26
Dout 511+M
Dout 527
R/B M Address
A0~A3 : Valid Address A4~A7 : Dont care
Selected Row
512
16 Start address M
18
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Sequential Row Read Operation ( Within a Block )
FLASH MEMORY
CLE
CE
WE
ALE
RE
I/O0~7
00h
A0 ~ A7 A9 ~ A16 A17 ~ A24 A 25,A2 6
Dout N
Dout N+1
Dout 527
Dout 0
Dout 1

Dout 527
R/B
M
Busy
Ready
Busy
M+1
N
Output
Output
Page Program Operation
CLE
CE
WE tWB ALE tPROG
RE
Din 10h 527 1 up to 528 Byte Data Program Serial Input Command Din N
I/O0~7
80h
A0 ~ A7 A 9 ~ A16 A17 ~ A24 Page(Row) Address
A25,A26
tWC
tWC
tWC
70h Read Status Command
I/O0
Sequential Data Column Input Command Address
R/B
I/O0=0 Successful Program I/O0=1 Error in Program
19
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
FLASH MEMORY
CLE
CE tWC WE tWB ALE tBERS
RE
I/O0~7
60h
A9 ~ A 16 A 1 7 ~ A 24 A 25,A2 6 Page(Row) Address
DOh
70h
I/O 0
R/B
Auto Block Erase Setup Command Erase Command
Busy
Read Status Command
I/O 0=0 Successful Erase I/O0=1 Error in Erase
20
Multi-Plane Page Program Operation
CLE
CE
tWC
WE
tWB tDBSY tWB tPROG
ALE
RE
I/O 0~7
80h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26 11h Program 1 up to 528 Byte Data Com mand (D umm y) Serial Input
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Max. three time s repe ata ble
La st P lane In put & Prog ram
tDBSY : typ. 1us
max. 10us
Ex.) Four-Plane Page Program into Plane 0~3 or Plane 4~7 tDBSY tDBSY tDBSY tPROG
R/B
21
Address & Data Input 11h 80h A 0 ~ A7 & A9 ~ A26 528 Byte Data Address & Data Input A0 ~ A7 & A 9 ~ A26 528 Byte Data 11h 80h Ad dress & Data In put A 0 ~ A7 & A9 ~ A26 528 Byte Data 11h
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26
Din N
Din 527
D in N
Din 527
71h 10h Program Confirm Comm and (True)
I/O Read M ulti-Plane Status Comm and
Sequential Data Input Command
Column Address
Page (Ro w) Add ress
R/B
I/O0~7
80h
80h
Add ress & Data Inp ut A0 ~ A7 & A9 ~ A 26 5 28 Byte Data
FLASH MEMORY
10h
7 1h
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Multi-Plane Block Erase Operation into Plane 0~3 or Plane 4~7
FLASH MEMORY
CLE
CE tWC WE tWB ALE tBERS
RE
I/O0~7
60h
A9 ~ A 16 A 1 7 ~ A 24 A25,A26 Page(Row) Address
DOh
71h
I/O 0
Block Erase Setup Command
Erase Confirm Command Read Multi-Plane StatusCommand
Max. 4 times repeatable
* For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command.
Ex.) Four-Plane Block Erase Operation R/B I/O0~7
Address Address 60h Address D0h
R/B
Busy
tBERS
71h
60h
Address A9 ~ A26
60h
60h
22
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Read ID Operation
FLASH MEMORY
CLE
CE
WE
ALE
RE tREA I/O 0 ~ 7
90h Read ID Command 00h Address. 1cycle ECh 79h A5h C0h Multi Plane Code
Maker Code Device Code
ID Defintition Table 90 ID: Access command = 90H
Value 1 Byte 2 n d Byte 3 rd Byte 4 th Byte
st
Description Maker Code Device Code Must be don't -cared Supports Multi Plane Operation
ECh 79h A5h C0h
23
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Copy-Back Program Operation
FLASH MEMORY
CLE
CE tWC WE tWB tWB tPROG
ALE tR RE
I/O0~7
00h
A0~A7 A9~A16 A17~A24 A25,A26 Column Address Page(Row) Address
8Ah
A0~A7 A9~A16 A17~A24 A25,A26 Column Address Page(Row) Address
10h
70h
I/O0
Read Status Command
Busy
Copy-Back Data Input Command
24
Busy
I/O 0=0 Successful Program I/O 0=1 Error in Program
R/B
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Device Operation
PAGE READ
FLASH MEMORY
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 12s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE . High to low transitions of the RE clock output the data stating from the selected column address up to the last column address. After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 12s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the Read2 command. Addresses A 0 to A 3 set the starting address of the spare area while addresses A4 to A 7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 8 to 11 show typical sequence and timings for each read operation.
Figure 8. Read1 Operation CLE CE WE ALE R/B RE I/O0~7
00h Start Add.(4Cycle) A0 ~ A7 & A 9 ~ A26 Data Output(Sequential)
tR
(00h Command)
(01h Command)*
1st half array
2st half array
1st half array
2st half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
25
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Figure 9. Read2 Operation CLE CE WE ALE R/B RE I/O0~7
50h Start Add.(4Cycle) A0 ~ A 3 & A9 ~ A26 ( A4 ~ A7 : Dont Care)
1st half array 2nd half array
FLASH MEMORY
tR
Data Output(Sequential) Spare Field
Data Field
Spare Field
Figure 10. Sequential Row Read1 Operation tR tR
R/B I/O0 ~ 7
tR
00h 01h
Start Add.(4Cycle) A 0 ~ A7 & A9 ~ A 26
Data Output 1st
Data Output 2nd (528 Byte)
Data Output Nth (528 Byte)
( 00h Command)
1st half array 2nd half array
( 01h Command)
1st half array 2nd half array
Block
1st 2nd Nth
1st 2nd Nth
Data Field
Spare Field
Data Field
Spare Field
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given.
26
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Figure 11. Sequential Row Read2 Operation tR tR
FLASH MEMORY
R/B I/O0~7
Start Add.(4Cycle) A0 ~ A3 & A 9 ~ A26 (A 4 ~ A7 : Dont Care)
tR
50h
Data Output 1st
Data Output 2nd (16Byte)
Data Output Nth (16Byte)
1st Block Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done i n any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 12). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 12. Program & Read Status Operation tPROG R/B I/O0~7
80h
Address & Data Input A0 ~ A7 & A 9 ~ A26 528 Byte Data
10h
70h
I/O0
Pass
Fail
27
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
BLOCK ERASE
FLASH MEMORY
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A 14 to A26 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation tBERS
R/B I/O0~7
60h
Address Input(3Cycle) Block Add. : A14 ~ A26
D0h
70h
I/O0
Pass
Fail
Multi-Plane Page Program into Plane 0~3 or Plane 4~7
Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Sin c e the device is equipped with eight memory planes, activating the four sets of 528 byte page registers into plane 0~3 or plane 4~7 enables a simultaneous programming of four pages. Partial activation of four planes is also permitted. After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane, actual True Page Program (10h) instead of dumy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages into plane 0~3 or plane 4~7 are programmed simultaneously, pass/fail status is available for each page when the program operation completes. The extended status bits (I/O1 through I/O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1" when any of the pages fails. Multi-Plane page Program with "01h" pointer is not supported, thus prohibited.
Figure 14. Four-Plane Page Program tDBSY tDBSY tDBSY tPROG
R/B I/O0~7
80h
Address & 11h Data Input A0 ~ A7 & A9 ~ A 26 528 Byte Data 11h
80h
Address & 11h Data Input A0 ~ A7 & A 9 ~ A26 528 Byte Data 11h
80h
Address & 11h Data Input A0 ~ A7 & A 9 ~ A26 528 Byte Data 11h
80h
Address & 10h Data Input A0 ~ A 7 & A9 ~ A 26 528 Byte Data 10h
71h
80h
80h
80h
80h
Data input
Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block)
Block 0 Block 4
Block 1 Block 5
Block 2 Block 6
Block 3 Block 7
Block 4088 Block 4092
Block 4089 Block 4093
Block 4090 Block 4094
Block 4091 Block 4095
28
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Restriction in addressing with Multi Plane Page Program
FLASH MEMORY
While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 15 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure16.
Figure 15. Multi-Plane Program & Read Status Operation
Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block)
Block 0 Page 0 Page 1
Block 1 Page 0 Page 1
Block 2 Page 0 Page 1
Block 3 Page 0 Page 1
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Figure 16. Addressing Multiple Planes
80h
Plane 2
11h
80h
Plane 0
11h
80h
Plane3
11h
80h
Plane 1
10h
Figure 17. Multi-Plane Page Program & Read Status Operation tPROG
Last Plane input
R/B I/O0~7
80h
Address & Data Input A0 ~ A7 & A 9 ~ A26 528 Byte Data
10h
71h
I/O
Pass
Fail
Multi-Plane Block Erase into Plane 0~3 or Plane 4~7
Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane. The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1 through I/O 4).
Figure 18. Four Block Erase Operation R/B I/O0~7
Address (3 Cycle) 60h Address (3 Cycle) 60h Address (3 Cycle) 60h Address (3 Cycle) D0h
tBERS
71h
60h
I/O
Pass
A0 ~ A7 & A 9 ~ A26 Fail
29
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Copy-Back Program
FLASH MEMORY
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read opera tion with "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. As soon as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. A14 , A15 and A26 must be the same between source and target page. Figure19 shows the command sequence for single plane operation. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation."
Figure 19. One Page Copy-Back program Operation R/B I/O0~7 tR tPROG
00h
Add.(4Cycles) A0 ~ A 7 & A 9 ~ A26 Source Address
8Ah
Add.(4Cycles) A0 ~ A7 & A 9 ~ A26 Destination Address
10h
70h
I/O0
Pass
Fail
30
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Multi-Plane Copy-Back Program
FLASH MEMORY
Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 byte page registers enables a simultaneous Multi-Plane CopyBack programming of four pages. Partial activation of four planes is also permitted. First, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal page buffers. Any further read operation for transferring the addressed pages to the corresponding page register must be execute d with "03h" command instead of "00h" command. Any plane may be selected without regard to "00h" or "03h". Up to four planes may be addressed. Data moved into the internal page registers are loaded into the destination plane addresses. After the input of command sequences for reading the source pages, the same procedure as Multi-Plane Page programming except for a replacement address command with "8Ah" is executed. Since no programming process is involved during data loading at the destination plane address , R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). After inputting data for the last plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed simultaneously, pass/fail status is available for each page when the program operation completes. No pointer operation is supported with Multi-Plane Copy-Back Program. Once the Multi-Plane Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished.
Figure 20. Four-Plane Copy-Back Program
Max Three Times Repeatable
Source Address Input
00h
03h
03h
03h
Plane 0 (1024 Block)
Plane 1 (1024 Block)
Plane 2 (1024 Block)
Plane 3 (1024 Block)
Block 0 Block 4
Block 1 Block 5
Block 2 Block 6
Block 3 Block 7
Block 4088 Block 4092
Block 4089 Block 4093
Block 4090 Block 4094
Block 4091 Block 4095
Max Three Times Repeatable
8Ah
11h
8Ah
11h
8Ah
11h
8Ah
10h
Destination Address Input
Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block)
Block 0 Block 4
Block 1 Block 5
Block 2 Block 6
Block 3 Block 7
Block 4088 Block 4092
Block 4089 Block 4093
Block 4090 Block 4094
Block 4091 Block 4095
31
Fig 21. Four-Plane Copy-Back Page Program (Continued)
R/B
I/O0~7
Add .( 4Cyc.) Ad d.( 4Cyc.) 11h A0 ~ A7 & A 9 ~ A25 S ource A ddress A0 ~ A7 & A 9 ~ A25 Destination Add ress 8Ah 03h Add.(4Cyc.) 8Ah Add .(4 Cyc.)
00h
A dd.( 4Cyc.)
0 3h
tR
tR tDBSY tDBSY
tR
tPROG
11h
8A h
Add .(4 Cyc.)
10h A0 ~ A7 & A 9 ~ A25 Destination Add ress
71h
A 0 ~ A7 & A9 ~ A25 So urce A ddress
A 0 ~ A7 & A9 ~ A25 So urce A ddress
A0 ~ A7 & A 9 ~ A25 Destination Add ress
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
32
tDBSY : Typical 1us, Max 10us M 4 times (4 C ax. ycle Destination Address Input) repeatable
tR : Normal Read Busy
M 4 times ( 4 C ax. ycle Source Address Input) repeatable
FLASH MEMORY
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
READ STATUS
FLASH MEMORY
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation.
Table4. Read Staus Register Definition
I/O No. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Status Total Pass/Fail Plane 0 Pass/Fail Plane 1 Pass/Fail Plane 2 Pass/Fail Plane 3 Pass/Fail Reserved Device Operation Write Protect Definition by 70h Command Pass : "0" Must be don't -cared Must be don't -cared Must be don't -cared Must be don't -cared Must be don't -cared Busy : "0" Protected : "0" Ready : "1" Not Protected : "1" Fail : "1" Definition by 71h Command Pass : "0"(1) Pass : "0" Pass : "0"
(2) (2)
Fail : "1" Fail : "1" Fail : "1" Fail : "1" Fail : "1"
Pass : "0"(2) Pass : "0"(2) Must be don't-cared Busy : "0" Protected : "0"
Ready : "1" Not Protected : "1"
NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/
Erase operation, it sets "Fail" flag. 2. The pass/fail status applies only to the corresponding plane.
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacture code(ECh), and the device code (79h), Reserved(A5h), Multi plane operation code(C0h) respectively. A5h must be don't-cared. C0h means that device supports Multi Plane operation. The command register remains in Read ID mode until further commands are issued to it. Figure 22 shows the operation sequence.
Figure 22. Read ID Operation 1 tCLR CLE tCEA CE WE tAR1 ALE RE I/O0~7
tWHR tREA
90h 00h Address. 1cycle ECh Maker code 79h Device code A5h C0h Multi-Plane code
33
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
RESET
FLASH MEMORY
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 23 below.
Figure 23. RESET Operation tRST
R/B I/O0~7
FFh
Table5. Device Status
After Power-up Operation Mode Read 1 After Reset Waiting for next command
34
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
READY/BUSY
FLASH MEMORY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operatio n. The pin is an open-drain driver thereby allowing two or more R/ B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 24). Its value can be determined by the following guidance.
Rp VCC
ibusy
Ready Vcc R/B open drain output 0.8V Busy 2.0V
tf GND Device
tr
Fig 24 Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25C
, CL = 100pF
381
3.3
tr ,tf [s]
1.65
200n tr 100n
96 4.2
189
1.1 0.825
2m
1m
tf
4.2
4.2
4.2
1K
2K
3K Rp(ohm)
4K
Rp value guidance
VCC(Max.) - VOL(Max.) Rp(min) = IOL + IL = 3.2V 8mA + IL
where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr
35
Ibusy [A]
300n
Ibusy
290
3m
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Data Protection
FLASH MEMORY
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10 s is required before internal circuit gets ready for any command sequences as shown in Figure 25. The two step command sequence for program/erase provides additional software protection.
Figure 25. AC Waveforms for Power Transition
2.5V VCC High
2.5V
WP
36
WE
10 s
Package Dimensions
Package Dimensions
48-Pin Lead Plastic Thin Small Out-Line Package Type(I) 48 - TSOP1 - 1220F
FLASH MEMORY
Unit :mm/Inch
0.008-0 .0 01
+0 .00 3
+0.0 7
0.2 0 -0 .03
#1
#48 ( 0.25 ) 0.0 10 12.40 MA X 0.488
0.50 0 .019 7
#24
#25 1.000.05 0.039 0.002 1.20 0.047 MAX 0.05 0.002 MIN
0.25 0.010 TYP
0.125 0 .0 35
0~8 AE
0.45~0.75 0.018~0.030
( 0.50 ) 0.020
37
+0 .0 03 0 .00 5- 0.0 0 1
18.400.10 0.7240.004
+0 .0 75
12.00 0.4 72
0.00 4
0.10
20.00 0.20 0.7870.008
MAX

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