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(R)
L5996
5 BIT DYNAMIC DAC CONTROLLER FOR MOBILE CPU
PRELIMINARY DATA
DYNAMIC DAC DETECTION ON CHIP PROGRAMMABLE OUTPUT FROM 0.925V TO 2.0V WITH 0.05V AND 0.025V BINARY STEPS ULTRA HIGH EFFICIENCY SEPARATE 5V BIAS SUPPLY AVAILABLE FOR HIGH EFFICIENCY PERFORMANCE EXCELLENT OUTPUT ACCURACY 1% OVER LINE, LOAD AND TEMPERATURE VARIATIONS HIGH PRECISION INTERNAL REFERENCE DIGITALLY TRIMMED OPERATING SUPPLY VOLTAGE FROM 4.75V TO 25V VERY FAST LOAD TRANSIENT REMOTE SENSING INPUTS INTERNAL LINEAR REGULATOR 2.5V /150mA, 2% PRECISION POWER MANAGEMENT - PROGRAMMABLE POWER-UP TIME - POWER GOOD OUTPUT, SKIP MODE - OUTPUT OVERVOLTAGE PROTECTION - OUTPUT UNDERVOLTAGE LOCKOUT OPERATING FREQUENCY UP TO 1MHz MEETS INTEL MOBILE PENTIU(R) III
TQFP32 (7mm x 7mm)
Application ADVANCED MICROPROCESSOR SUPPLIES POWERSUPPLYFOR PENTIUM(R) III INTEL MOBILE DESCRIPTION The L5996 is a power supply controller that offers a complete power management for notebook CPUs of the next generation especially for mobile Pentium III. A high precise 5 bit digital to analog converter (DAC) allows to adjust the output voltage from 0.925V to 2.0V. Dynamic DAC code changes are detected on chip in order to switch the output voltage between 1.3V and 1.45V in less tahn 100s.The high precision internal refer-
TYPICAL APPLICATION CIRCUIT
L5996
POWER SECTION 4.75V to 25V PWM SECTIONS VO 0.925V to 2.0V D0 D1 FREQ SETTING SYNC DAC D2 D3 D4 CPU CORE
Pentium(R) III Mobile
NOSKIP
POWER MANAGEMENT & SYSTEM SUPERVISOR 2.5V LIN. REG.
POWER GOOD ENABLE CPU CLK
3.3V
2.5V
D98IN997A
July 1999
1/9
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L5996
DESCRIPTION (Continued) ence, digitally trimmed, assures the selected output voltage to within +/-1% over temperature and battery voltage variations. Thanks to the remote sensing inputs and to the window comparator system, embedded in the error summing structure, the device provides excellent load transient performance. The high peak current gate drive affords to have fast switching to the external power mos, performing an high efficiency. A complete power management include on board a programmable power-up sequencing, power good signal, skip mode operation and undervoltege detection. The L5996 assures a fast protection against load overvoltage and load overcurrent. Linear regulator on-board is available with an output voltage of 2.5V (+/-2%) and a current capability of 150mA, useful for CPU CLOCK BUS.
CSOFT VIN3.3V SSTART 6 WINDOW COMP VID0 20 VID1 21 VID2 22 VID3 23 VID4 24 VIN2.5 13
PIN CONNECTION
POWERGOOD
PWRGND
RSTRAP
HSTRAP
32 31 30 29 28 27 26 25 ENABLE VIN REG5 V5SW DISPROT SSTART HRSNS LRSNS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VPROG VIN2.5 VO2.5 VBG VFB COMP SNSGND VSS 24 23 22 21 20 19 18 17 VID4 VID3 VID2 VID1 VID0 ICURLIM OSC FREQ
NOSKIP
D98IN998
RGATE
HGATE
BLOCK DIAGRAM
HSRC
VFB
9 SLOPE
+ + + ERROR SUMMING
PROGRAMMABLE BANDGAP & REFERENCE
14 2.5V LIN. REG. 15
VO2.5
VCPUCLK
LRSNS HRSNS COMP REG5 RSTRAP HSTRAP VIN Cboot HGATE HSRC
8 7 10
VBG
SOFT START
29 28
VPROG
HRSNS OVER CURRENT COMPARATOR
LRSNS INTERNAL SUPPLY
11
VPROG
27 26
Hside
+ ZERO CROSSING COMPARATOR
3
REG5 C5
Rsense L C Load PWRGND SNSGND RGATE 30 31
CONTROL LOGIC Lside
+ PULSE SKIPPING COMPARATOR + -
LINEAR REGULATOR
4 2
V5SW VIN Vdc 5.5V to 25V
12 OSCILLATOR and SYNC 18 OSC 17 FREQ OVER/UNDER VOLTAGE COMPARATOR
VPROG POWER MANAGEMENT
32 1
PWGOOD
VSS
16
ENABLE 19 ICURLIM
D98IN999
25 NOSKIP
5 DISPROT
5V
ABSOLUTE MAXIMUM RATINGS
Symbol VIN to PWRGND PWRGND to VSS VREFS to PWRGND HSTRAP, HGATE to PWRGND RSTRAP, RGATE to PWRGND EABLE, FREQ, OSC, COMP, VFB, HRSNS, LRSNS VID0-3, NOSKIP Tj Tstg Junction Temperature Range Storage Temperature Range Parameter Value -0.5 to 27 0.5 5 -0.5V to VIN+14V -0.5V to 14V 5 7 -40 to 150 -55 to 150 V V C C Unit V V V
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L5996
THERMAL DATA
Symbol RTh j-amb Parameter Thermal Resistance Junction to Ambient Value 60 Unit C/W
ELECTRICAL CHARACTERISTICS ( VIN = 12V; Ti = 25C, OSC = GND, unless otherwise specified) * = specifications referred to TJ from 0 to 70C.
Symbol VIN IOP ISB Parameter Input Supply Voltage Operating Quiescent Current Stand-By Current RGATE = HGATE = OPEN ENABLE = REG5 ENABLE = GND VIN = 12V VIN = 25V VIN = 7.5V to 25V ILOAD = 0 to 5mA, C REG5 = 4.7F CREG5 = 4.7F VIN = 5.5V VIN 6V V5SW = 4.5 to 5.5V VREG5 4.4V VIN 2.5 = 3.3V C VO 2.5 = 47F IO 2.5 = 10mA Test Conditions Min. Typ. Max. 25 0.9 1.1 Unit V mA DC CHARACTERISTICS
* * *
4.75
80 100 4.9 5.0
150 180 5.1
A A V
INTERNAL REGULATOR (VREG5) VREG5 Output Voltage
IREG5
Total Current Capability
25 60 4.3 25 4.5 4.7
mA mA V mA
Switch-Over Threshold Voltage Current Capability (internal switch on) 2.5V REFERENCE VOLTAGE VO 2.5 Regulated Voltage
* *
2.45
2.5
2.55
V
Regulation over Line and Load 6V < VIN < 25V VIN 2.5 = 3.3V IO 2.5 = 0-150mA IVO 2.5 MAX Current Limit VIN 2.5 = 3.3V PROGRAMMABLE REFERENCE VOLTAGE AND VBG VPROG VFB Accuracy Ouput Voltage Accuracy VID0, VID1, VID2, VID3, VID4 see Table 1. Line and Load Regulation included, VID0, VID1, VID2, VID3, VID4, see Table 1. C VBG = 220nF HIGH LEVEL LOW LEVEL Isink = 400A High Level Low Level OVP = GND Depending on CSS value
2.425
2.5
2.575
V
500
mA V V
* * *
-0.5% -1%
VPROG VPROG
+0.5% +1%
VBG Band Gap reference POWER MANAGEMENT Enable Voltage Disable Voltage Power Good Saturation Voltage NOSKIP Mode (Active high) Output UVLO Threshold Output UVLO Lockout Time
1.240 2.4
1.246
1.252
V V
0.8 0.4 0.8 2.4 60 70 775 80
V V V V % ms/F
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L5996
ELECTRICAL CHARACTERISTICS (continued)
Symbol V8-V7 Parameter Over-Current Threshold Voltage Pulse Skipping Mode Threshold Voltage Zero Crossing Threshold Under-Voltage Threshold Upper Over-Voltage Threshold Lower Over-Voltage Threshold Over-Voltage Propagation Time Under-Voltage Propagation Time SOFT START Soft start source current Soft start clamp voltage OSCILLATOR AND SYNC fosc f
SINK MIN
Test Conditions VSSTART = 3.1V NOSKIP = HIGH
Min.
Typ. 60 11
Max. 72 15 +4
Unit mV mV mV V V V
PROTECTION FUNCTIONS
*
48 7 -4 Vprog -13% Vprog +7%
Vprog -10% Vprog +10% Vprog -4.5%
Vprog -7% Vprog +13%
1.5 1.5
s s
3.2
4 3.1
4.8
A V KHz KHz KHz ns
Fixed frequency Minimum Synchronizzable external frequency Sync pulse width Sync pulse amplitude
OSC =0V; FREQ = REG5 OSC = REG5 FREQ = REG5 FREQ = REG5 OSC = EXTERNAL SIGNAL Rising edge mode
* *
225 180
250 200
275 220 120
200
Operating switching frequency Rext connected between FREQ and GND, OSC connect to REG5 or GND Rext = 680k Rext = 40k HIGH AND LOW SIDE GATE DRIVERS IOH5 R H5 IOH12 R H12 IOL5 RL5 IOL12 R L12 TCC Output high source peak current Output high sink impedance Output high source peak current Output high sink impedance Output low peak current Output low impedance Output low peak current Output low Impedance Dead Time HSTRAP = RSTRAP = REG5 Itest = 100mA, HSTRAP = RSTRAP = REG5 HSTRAP = RSTRAP = 12V Itest = 100mA, HSTRAP - RSTRAP = 12V HSTRAP = RSTRAP = 5V Itest = 100mA, HSTRAP = RSTRAP = 5V HSTRAP = RSTRAP = 12V Itest = 100mA, HSTRAP = RSTRAP = 12V GATE low to high
fosc
*
3
5.5
V
100 1 550 3.5 2 2 500 3 2 2 60
kHz MHz mA A mA A ns
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L5996
FUNCTIONAL PIN DESCRIPTION ENABLE(pin1): Enable input. A high level (>2.4V) enables the device, a low level (<0.8V) shuts it down. As ENABLE drops below 0.8V, the drivers are turned off and all internal functions are disabled except REG5. In this condition the stand by current is less than 80A at VIN = 12V. VIN(pin2): Device supply voltage. Input voltage range at this pin is 4.75V to 25V and the operating current requirement at 12V is 650A. REG5(pin3): 5V Regulator supply. Used also to supply the bootstrap capacitor. A minimum 2.2F ceramic capacitor connected to PWRGND is required. V5SW(pin4): 5V supply line. Connecting to 5V bus(4.75V to 5.5V) the device is no longer powered by VIN but by this pin and the internal linear regulator is disconnected increasing the efficiency. DISPROT (pin5) Disable Protection Functions. A high level (3.3V CMOS LOGIC) on this pin disables the undervoltage and the overvoltage protection. Tie this pin to VSS for normal operation. SSTART(pin6): Soft Start. The soft-start time is programmed by an external capacitor connected between this pin and SGND. The internal current generator forces 4A through the capacitor implementing the soft start function. HRSNS(pin7): Error summing current sense non inverting input. LRSNS(pin8): Error summing current sense inverting input. VFB(pin9): Regulator voltage feedback input. Connect close to the CPU input supply pin realise an accurate voltage regulation. VFB internally is connected to the window comparator that is used to increase the performance during the load transient. COMP(pin10): Regulator stability compensation pin. The compensation is realised internally and normally it is not necessary to connect any external components to this pin.
VPROG(pin11): Reference voltage test pin. This pin provides the DAC output and should be decoupled to ground using a 0.22F ceramic capacitor. No load has to be connected. SNSGND(pin12): Remote ground sense. This pin is internally connected to the low power circuitry and for a precise output voltage regulation can be connected to the output capacitor negative terminal. VIN2.5(pin13): 2.5V linear supply voltage. Is available on-chip a linear regulator useful for the 2.5V bus. A max input voltage of 3.3V is recommended at Iomax (150mA). VO2.5(pin14): 2.5V linear regulator output. The linear regulator is realised with an internal NPN transistor with +/-2% output accuracy. A minimum of 47F capacitor connected versus PWRGND is required. VBG(pin15): Band-gap reference voltage. A min 220nF ceramic capacitor is required to assure the band gap stability and noise immunity. VSS(pin16): Signal ground. This pin could be connected to the PWRGND pin. FREQ(pin17): Connecting an external resistor versus ground is possible to select the switching frequency between 100kHz and 1MHz. Using an Rext=680k the fsw is 100kHz, using an Rext = 40k the fsw is 1MHz. In this condition is recommended to connect the OSC pin to REG5 or to VSS. OSC(pin18): Connecting to REG5 is able to set the switching frequency at 200kHz, connecting to VSS is able to set the switching frequency at 250kHz. An external pulsed signal, with an amplitude higher than 2.4V, could synchronise the device. In all these conditions pin FREQ has to be connected to REG5. OVP/CURLIM(pin19): Over voltage protection and reduced current limit window. If the output voltage reaches the 10% above the programmed voltage (VPROG) this pin is driven low the high side driver is turned off and the low, side driver is turned on. All the internal blocks are active. The device uses OVP function to discharge the output during HIGH_TO_LOW core voltage transition. The pin is driven low also during LOW_TO_HIGH core voltage transition. The pin will stay low as
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L5996
long as the current limit value is reduced with respect to the normal operating value. This is done to limit voltage overshoots during core voltage changes. Making this signal externally available simplifies system debugging. VID0-4(pin20-24): Voltage Identification code input. These open collector compatible inputs are used to program the output voltage as specified in Table 1. Every pin has an internal pull up. If all four pins are high or floating, the output voltage and the 2.5V regulator are suspended and the POWERGOOD is low. NOSKIP(pin25): Pulse skipping mode control. A high level (>2.4V) disables pulse skipping in low load condition, a low level (>0.8V) enables it. HSRC(pin26): High side N-Channel switch source connection. This pin provides the return path for the high side driver. HGATE(pin27): Gate driver output, high side NChannel switch. The driver internal impedance is about 4 at VIN=12V. HSTRAP(pin28):Bootstrap capacitor pin. This pin provide to supply the high side driver sinking the current by the bootstrap capacitor. RSTRAP(pin29): Synchronous rectifier gate driver supply voltage. This pin could be connected to REG5 to reduce the switching losses due to the external Mosfets gate capacitance. This is useful to maintain an high efficiency at light load. RGATE(pin30): Gate driver output, low side NChannel switch. The driver internal impedance is about 3 at VIN=12V. PWRGND(pin31): Power ground. This pin has to be connected closely to the low side mosfet source in order to reduce the noise injected into the IC. POWER GOOD(pin32): Open drain power good output. This pin is pulled low if the output voltage is not within 10% and the 2.5V output is lower than 2.175V (-13%). The pin is pulled low also if REG5, VPROG and VBG have not reached the expected values. This test could be useful in an assembling fault condition.
Table 1. VID [4:0] AND corresponding +VCC_CPU_CORE ranges
VID[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 +VCC_CPU_CORE 2.00V 1.95V 1.90V 1.85V 1.80V 1.75V 1.70V 1.65V 1.60V 1.55V 1.50V 1.45V 1.40V 1.35V 1.30V No CPU VID[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 +VCC_CPU_CORE 1.275V 1.250V 1.225V 1.200V 1.175V 1.150V 1.125V 1.100V 1.075V 1.050V 1.025V 1.000V 0.975V 0.950V 0.925V No CPU
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L5996
Figure 1. Application Circuit
Vin 4.5V to 25V
REG5 SSTART 6 VBG 3 2
VIN 29
RSTRAP HSTRAP HGATE
28 27
15
NOSKIP VSS OSC FREQ
25 16 18 17 5 11 31 26
HSRC
Vo 0.925V to 2.0V
L5996
30
RGATE
DISPROT VPROG
PWRGND
Pentium(R) III Mobile
7 8 5V BUS Vin2 3.3V V5SW 4 12 9 13 19 20/24 1 14 32
HRSNS LRSNS SNSGND VFB Vo2.5 Vo2 2.5V/150mA PWRGOOD ENABLE VID 5
ICURLIM
D98IN1000B
Figure 2. Output voltage transition between 1.3V and 1,5V measured at 200mA load current.
CH1: VID 2 transition. CH2: Output voltage transition between 1.3V and 1.5V measured at 200mA load current.
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L5996
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09
mm TYP. MAX. 1.60 0.15 1.40 0.37 1.45 0.45 0.20 9.00 7.00 5.60 0.80 9.00 7.00 5.60 0.60 1.00 0(min.), 7(max.) 0.75 0.018 0.002 0.053 0.012 0.004 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.015 0.057 0.018 0.008 0.354 0.276 0.220 0.031 0.354 0.276 0.220 0.024 0.039 0.030
OUTLINE AND MECHANICAL DATA
TQFP32
D D1 D3
24 25 17 16
0.10 mm .004 Seating Plane
A A2 A1
E3
E1
B
32 1 8
9
E
B
e
L1 L
C
K
TQFP32
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L5996
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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