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MK1575-01
CLOCK RECOVERY PLL
Description
The MK1575-01 is a clock recovery Phase-Locked Loop (PLL) designed for clock synthesis and synchronization in cost sensitive applications. The device is optimized to accept a low-frequency reference clock to generate a high-frequency data or graphics pixel clock. External loop filter components allow tailoring of loop frequency response characteristics. For low jitter / phase noise requirements refer to the MK2069 products.
Pre-Configured Input/Output Frequency Combinations:
Telecom T/E Clock Modes (rising edge aligned):
Addr FS2:0
000 001 010 011
Input Clock
8 kHz 8 kHz 8 kHz 8 kHz
Output Clocks (MHz) CLK1 CLK2
3.088 16.384 34.368 44.736 1.544 2.048 17.184 22.368
Clock Type
T1 E1 E3 T3
Features
* Long-term output jitter <2 nsec over 10 sec period * External PLL clock feedback path enable "zero * * * * * * *
delay" I/O clock skew configuration Selectable internal feedback divider provides popular telecom and video clock frequencies (see tables below) Can optionally use external feedback divider to generate other output frequencies. Single 3.3 V supply, low-power CMOS Power-down mode and output tri-state (pin OE) Packaged in 16-pin TSSOP Available in Pb (lead) free package Industrial temperature range available
Video Clock Modes (falling edge aligned):
Addr Input FS2:0 Clock (kHz)
100 101 110 111 15.625 15.734 15.625 15.734
Output Clocks (MHz) CLK1 CLK2
54 54 35.468 28.636 27 27 17.734 14.318
Clock Type
PAL 601 NTSC 601 PAL 4xfsc NTSC 4xfsc
Block Diagram
The standard external clock feedback configuration is shown. Use this configuration for the pre-configured input/output frequency combinations listed above.
CS CB RS
CHGP
Phase Charge Detector Pump
CHPR
Clock Input
REFIN
0
MUX
1
VCO
300 pF
VS Divider CLK2 Divider
CLK1 CLK2
FBIN
0
MUX
1
Divider LUT
FCLK Divider
FCLK
3
FS2:0
External Feedback Clock Connection
OE
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MK1575-01 CLOCK RECOVERY PLL
Pin Assignment
REFIN FS0 VDDA VDDD FS1 GNDA GNDD CHGP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FBIN NC FCLK OE CLK2 FS2 CLK1 CHPR
16 pin 4.40 mil body, 0.65 mil pitch TSSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
REFIN FS0 VDDA VDDD FS1 GNDA GNDD CHGP CHPR CLK1 FS2 CLK2 OE FCLK NC FBIN
Pin Type
Input Input Power Power Input
Pin Description
Reference clock input. Connect the input clock to this pin. Can be Rising or Falling edge triggered as per Detailed Mode Selection Table, page 3. Frequency Selection Input bit 0, selects internal divider values as per Detailed Mode Selection Table, page 3. Power supply connection for internal VCO and other analog circuits. Power supply connection for internal digital circuits and output buffers. Frequency Selection Input bit 1, selects internal divider values as per Detailed Mode Selection Table, page 3.
Ground Ground connection for internal VCO and other analog circuits. Ground Ground connection for internal digital circuits and output buffers. -- -- Output Input Output Input Output -- Input Loop filter connection, active node. Loop filter connection, reference node. Do not connect to ground. Output clock 1. Frequency Selection Input bit 2, selects internal divider values as per Detailed Mode Selection Table, page 3. Output clock 2. Output Enable, tristates CLK1, CLK2, FCLK and powers down PLL when high. Internal pull-up. Feedback clock output, connect to FBIN for the pre-configured frequency combinations listed in the tables on page 1. No internal connection, connect to ground. Feedback clock input. Connect to CLK1, CLK2, FCLK, or the output of an external feedback divider, depending on application. Refer to document text for more information.
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MK1575-01 CLOCK RECOVERY PLL
Detailed Mode Selection Table
Refer to this table when not using the standard external clock feedback configuration shown on page 1.
Address FS2:0
000 001 010 011 100 101 110 111
Internal Divider Settings VS Divider
64 16 8 4 4 4 8 8
CLK2 Divider FCLK Divider
2 8 2 2 2 2 2 2 386 2048 4296 5592 3456 3432 2270 1820
FBIN, REFIN Clock Edge
Rising Rising Rising Rising Falling Falling Falling Falling
CLK1 Output Frequency Range
1.5 - 5 MHz 6 - 20 MHz 12 - 40 MHz 24 - 80 MHz 24 - 80 MHz 24 - 80 MHz 12 - 40 MHz 12 - 40 MHz
Block Diagram, Showing Device Configuration Options
CS CB RS
CHGP
Phase Charge Detector Pump
CHPR
Clock Input
REFIN
0
MUX
1
VCO
300 pF
VS Divider CLK2 Divider
CLK1 CLK2
FBIN
0
MUX
1
Divider LUT
FCLK Divider
FCLK
3
FS2:0
FB Divider Optional External Feedback Divider
OE
Feedback Clock Options (only connect one output)
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MK1575-01 CLOCK RECOVERY PLL
Functional Description
The MK1575-01 is a PLL (phase-locked loop) based clock generator that generates output clocks synchronized to an input reference clock. The device can be used in the standard configuration as described on page 1, or optionally can use an external divider in the clock feedback path to produce other frequency multiplication factors. External components are used to control the PLL loop response. The use of external loop components enables a lower PLL loop bandwidth which is needed when accepting low frequency input clocks such as those listed in the tables on page 1.
page 3) the output clock frequency can be increased. Refer to the Output Frequency Calculation table below.
CLK1 to FBIN
When no external feedback divider is used, this option configures the device as a zero-delay buffer and the frequency of CLK1 is the same as the input reference clock. Including an external divider in the feedback path will increase the output clock frequency. Refer to the Output Frequency Calculation table below.
CLK2 to FBIN
Like the above configuration, this option configures the device as a zero-delay buffer when no external feedback divider is used, and the frequency of CLK2 is the same as the input reference clock. Including an external divider in the feedback path will increase the output clock frequency. Refer to the Output Frequency Calculation table below.
PLL Clock Feedback Options
FCLK to FBIN
This is the standard configuration that is used for the pre-configured input / output frequency combinations listed on page 1. By including an external divider in the feedback path ("FB Divider" in the Block Diagram of
Frequency and Bandwith Calculations
Feedback Path Option Output Clock Frequency CLK1 CLK2 FCLK VCO Frequency
"N" Factor
FCLK to FBIN CLK1 to FBIN CLK2 to FBIN
f IN x FB x FCLK
FCLK f IN x FB x --------------CLK2 f IN x FB --------------------CLK2
f IN x FB f IN x FB -------------------FCLK CLK2 f IN x FB x --------------FCLK
f IN x FB x FCLK
2
VS x FCLK x FB
f IN x FB
f IN x FB x VS
VS x FB
f IN x FB x CLK2
f IN x FB
f IN x FB x CLK2 x VS
2
VS x CLK2 x FB
Notes: 1) FB = 1 when no feedback divider is used. 2) Refer to the Detail Mode Selection Table on page 3 for possible divider combinations. 3) The VCO frequency needs to be considered in all applications (see table below). 4) The external loop filter also needs to be considered. 5) Minimum VCO frequency = 96 MHz. 6) Maximum VCO frequency = 320 MHz. 7) To minimize output jitter, use the highest possible VCO frequency allowed by the application.
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MK1575-01 CLOCK RECOVERY PLL
Setting PLL Loop Bandwidth and Damping Factor
The frequency response of the MK1575-01 PLL may be approximated by the following equation:
( R S K O I CP ) ----------------------------------------2 N
Normalized PLL Bandwidth
=
applications, a higher damping factor is usually desirable. A higher damping factor will create less passband gain peaking which will minimize the gain of network clock wander amplitude. A higher damping factor may also increase output clock jitter when there is excess digital noise in the system application, due to the reduced ability of the PLL to respond to, and therefore compensate for, phase noise ingress.
Notes on setting the value of CP
The associated damping factor is calculated as follows:
RS K I O CP C S = ------- -----------------------------------2 N
As another general rule, the following relationship should be maintained between components C1 and C2 in the external loop filter: CP
S = ------
Damping factor,
C
Where: KO = Icp = N = VCO gain in Hz/Volt (use 340 MHz/V) Charge pump current, 12.5 A Total feedback divide from VCO, (Refer to N Value table, below) External loop filter capacitor in Farads Loop filter resistor in Ohms Where: CP
20
= C B + 300 pF
CB = External bypass capacitor in Farads Note that the MK1575-01 contains an internal 300 pF filter cap which is connected in parallel with external device CB. This helps to reduce output clock jitter. In some applications external device CB will not be required. CP establishes a second pole in the PLL loop filter. For higher damping factors (>1), calculate the value of CP based on a CS value that would be used for a damping factor of 1. This will minimize baseband peaking and loop instability that can lead to output jitter. CP also helps to damp VCO input voltage modulation caused by the charge pump correction pulses. A CP value that is too low will result in increased output phase noise at the phase detector frequency due to this. In extreme cases where input jitter is high, charge pump current is high, and CP is too small, the VCO input voltage can hit the supply or ground rail resulting in non-linear loop response. The best way to set the value of CP is to use the External Loop Filter Solver at www.icst.com/products/telecom/telecom.htm.
CS = RS =
The above bandwidth equation calculates the "normalized" loop bandwidth which is approximately equal to the - 3dB bandwidth. This approximate calculation does not take into account the effects of damping factor or the third pole imposed by CP. It does, however, provide a useful approximation of filter performance. To prevent jitter on the output clocks due to modulation of the PLL by the input reference frequency, the following general rule should be observed: PLL Bandwidth
f Phase Detector -------------------------------20
In general, the loop damping factor should be 0.7 or greater to ensure output stability. For video applications, a low damping factor (0.7 to 1.0) is generally desired for fast genlocking. For telecom
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MK1575-01 CLOCK RECOVERY PLL
Loop Filter Capacitor Type
Clock Jitter and input-to-output skew performance of the MK1575-01 can be affected by loop filter capacitor type. Cost vs. performance trade-offs can be made when choosing capacitor types. Performance
differences are best determined through experimentation. Recommended capacitors can be found at http://www.icst.com/products/telecom/
Example Loop Filter Component Values for Pre-Configured Frequency Combinations Listed on Page 1.
Addr Input Frequency
8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 15.625 kHz 15.734 kHz 15.625 kHz 15.734 kHz
Output Frequency N Factor (MHz) CLK1 CLK2
RS
CS
CB
Loop Loop Passband BW Damp Peaking (-3dB)
363 Hz 199 Hz 425 Hz 181 Hz 405 Hz 173 Hz 390 Hz 219 Hz 758 Hz 760 Hz 760 Hz 721 Hz 2.5 4.46 3.24 4.67 3.16 4.56 2.62 4.69 0.72 0.73 0.73 0.7 0.19 dB 0.06 dB 0.12 dB 0.05 dB 0.13 dB 0.06 dB 0.17 dB 0.05 dB 2.16 dB 2.15 dB 2.15 dB 2.42 dB
Notes
000 000 001 001 010 010 011 011 100 101 110 111
3.088 3.088
1.544 1.544
24704 24704 32768 32768 34368 34368 22368 22368 13824 13728 18160 14560
15 k 6.8 k 18 k 8.2 k 18 k 8.2 k 12 k 6.8 k
1 F 10 F 1 F 10 F 1 F 10 F 1 F 10 F
2.2 nF 4.7 nF 2.2 nF 4.7 nF 2.2 nF 4.7 nF 1 nF 4.7 nF
1 2 1 2 1 2 1 2 3 3 3 3
16.384 2.048 16.384 2.048 34.368 17.184 34.368 17.184 44.736 22.368 44.736 22.368 54 54 27 27
10 k 0.068 F 3.3 nF 10 k 0.068 F 3.3 nF 10 k 0.068 F 3.3 nF 10 k 0.068 F 4.7 nF
35.468 17.734 28.636 14.318
Notes: 1) This loop filter selection is optimized for cost and component size. It provides stable clock outputs and moderate input reference jitter attenuation. This configuration could be used when producing an internal system clock, one which will not be used as a data transmit clock when locked to a recovered data clock. 2) This loop filter selection is optimized for low pass-band peaking. This configuration should be used when generating data transmit clock that is locked to a recovered data clock. This will ensure that the data clock conforms with Belcore GR-1244-CORE wander transfer specifications. 3) A loop bandwidth of 700 Hz and damping factor of 0.7 is typical for video genlock applications. This combination assures minimal Hsync frequency modulation of the pixel clock yet genlocking. 4) Example vendors and part numbers for above capacitor selections: 0.15 F 0.68 F 10 F 10 nF 33 nF
MDS 1575-01 K In te grated Circuit Systems
Panasonic ECP-U1C154MA5 (SMT film type, 1206 size, available from DigiKey) Panasonic ECP-U1C684MA5 (SMT film type, 1206 size, available from DigiKey) MuRata GRM42-2X5R106K10 Panasonic ECH-U1C103JB5 (SMT film type, 805 size, available from DigiKey) Panasonic ECH-U1C333JB5 (SMT film type, 1206 size, available from DigiKey) 6
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MK1575-01 CLOCK RECOVERY PLL
Input-to-Output Skew Induced by Loop Filter Leakage
Leakage across the loop filter, due to PCB contamination or poor quality loop filter capacitors, can increase input-to-output clock skew error. Concern regarding input-to-output skew error is usually limited to "zero delay" configurations, where CLK1 or CLK2 is directly connected to FBIN. In sever cases of loop filter leakage, however, output clock jitter can also be increased. The capacitors CS and CP in the external loop filter maintain the VCO frequency control voltage between charge pump pulses, which by design coincide with phase detector events. VCO frequency or phase adjustments are made by these charge pump pulses, pumping current into (or out of) the external loop filter capacitors to adjust the VCO control voltage as needed. Like the capacitors, the CHGP pin (pin 8) is a high-impedance PLL node; the charge pump is a current source, which is high impedance by definition, and the VCO input is also high impedance. During normal (locked) operation, in the event of current leakage in the loop filter, the charge pump will need to deliver equal and opposite charge in the form of longer charge pump pulses. The increased length of the charge pump pulse will be translated directly to increased input-to-output clock skew. This can also result in higher output jitter due to higher reference clock feedthrough (where the reference clock is fREFIN), depending on the loop filter attenuation characterisitcs. The Input-to-Output skew parameters in the DC Electrical Specifications assume minimal loop filter leakage. Additional skew due to loop filter leakage may be calculated as follows:
I Leakage Leakage Induced I/O Skew (sec) = ------------------------------I CP x F REFIN
1) Do not open the clock feedback path with the MK1575-01 enabled. If the MK1575-01 is enabled and does not get a feedback clock into pin FBIN, the output frequency will be forced to the maximum value by the PLL. If an external divider is in the feedback path and it has a delay before becoming active, hold the OE pin high until the divider is ready to work. This could occur, for example, if the divider is implemented in a FPGA. Holding OE high powers down the MK1575-01 and dumps the charge off the loop filter. 2) If an external divider is used in the feedback path, use a circuit that can operate well beyond the intended output clock frequency.
Power Supply Considerations
As with any integrated clock device, the MK1575-01 has a special set of power supply requirements:
* The feed from the system power supply must be
filtered for noise that can cause output clock jitter. Power supply noise sources include the system switching power supply or other system components. The noise can interfere with device PLL components such as the VCO or phase detector.
* Each VDD pin must be decoupled individually to
prevent power supply noise generated by one device circuit block from interfering with another circuit block.
* Clock noise from device VDD pins must not get onto
the PCB power plane or system EMI problems may result. This above set of requirements is served by the circuit illustrated in the Optimum Power Supply Connection, below. The main features of this circuit are as follows:
* Only one connection is made to the PCB power
plane.
* The capacitors and ferrite chip (or ferrite bead) on
the common device supply form a lowpass `pi' filter that remove noise from the power supply as well as clock noise back toward the supply. The bulk capacitor should be a tantalum type, 1 F minimum. The other capacitors should be ceramic type.
Avoiding PLL Lockup
In some applications, the MK1575-01 VCO can "lock up" at it's maximum operating frequency. To avoid this problem observe the following rules:
* The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce interaction between the device circuit blocks.
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MK1575-01 CLOCK RECOVERY PLL * The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin as possible. There should be no vias between the decoupling capacitor and the supply pin.
4) Because each input selection pin includes an internal pull-up device, those inputs requiring a logic high state ("1") can be left unconnected. The pins requiring a logic low state ("0") can be grounded.
Optimum Power Supply Connection
Connection Via to 3.3V Power Plane Ferrite Chip 0.1 F BULK 1 nF VDDA Pin
Loss of Reference Clock
If a loss occurs on the REFIN clock, the output frequency will decrease at a rate of df 4250 = dt C x VS Hz/s
0.01 F
10
0.01 F
VDDD Pin
where: C = C1 + C2 VS = value of VS divider (from the table on page 3) If the input is held low, the output will stop high or low, or might toggle at several Hz.
Low Frequency Operation Series Termination Resistor
Output clock PCB traces over 1 inch should use series termination to maintain clock signal integrity and to reduce EMI. To series terminate a 50 trace, which is a commonly used PCB trace impedance, place a 33 resistor in series with the clock line as close to the clock output pin as possible. The nominal impedance of the clock output is 20. The output frequency can be extended below 1.5 MHz by adding a divider in the output path. In this configuration, it is desirable to take the feedback signal from CLK1 rather than the output of the divider. However, if zero delay operation is required, the feedback signal must come from the divider output.
700
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following printed circuit board layout recommendations should be observed. 1) Each 0.01F power supply decoupling capacitor should be mounted as close to the VDD pin as possible. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite chip and bulk decoupling from the device is less critical. 2) The loop filter components (RZ, CS and CB) must also be placed close to the CHGP and VIN pins. CB should be closest to the device. Coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. 3) To minimize EMI the 33 series termination resistor, if needed, should be placed close to the clock output.
600
500
400 MHz 300 200 100 0 0 0.5 1 1.5 Vin 2 2.5 3 3.5
MK1575-01 Typical VCO Transfer Curve
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MK1575-01 CLOCK RECOVERY PLL
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1575-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature (industrial version) Ambient Operating Temperature (commercial version) Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V -40 to +85C 0 to +70C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (industrial version) Ambient Operating Temperature (commercial version) Power Supply Voltage (measured in respect to GND)
Min.
-40 0 +3.15
Typ.
Max.
+85 +70
Units
C C V
+3.3
+3.45
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70 C
Parameter
Operating Voltage Supply Current
Symbol
VDD IDD
Conditions
Clock outputs unloaded, VDD = 3.3 V OE = VDD
Min.
3.15
Typ.
3.3 10
Max.
3.45
Units
V mA
Supply Current in Power Down Charge Pump Current Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance, except X1
IDD ICP VIH VIL IIH IIL CIN
100 12.5 2 0.8
A A V V A A pF +10 +10
VIH = VDD VIL = 0
-10 -10 7
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MK1575-01 CLOCK RECOVERY PLL
Parameter
Output High Voltage (CMOS Level) Output High Voltage
Symbol
VOH VOH
Conditions
IOH = -4 mA IOH = -8 mA CLK1, CLK2 IOH = -4 mA FCLK
Min.
VDD-0.4 2.0 2.0
Typ.
Max.
Units
V V V
Output Low Voltage
VOL
IOL = 8 mA CLK1, CLK2 IOL = 4 mA FCLK
0.4 0.4 43 18 20
V V mA mA
Short Circuit Current Nominal Output Impedance
IOS ZOUT
CLK1, CLK2 FCLK
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature 0 to +70 C
Parameter
Input Clock Frequency (into pins REFIN or FBIN) Internal VCO Frequency Output Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle Jitter, Absolute Peak-to-peak
Symbol
fREF fVCO fCLK tOR tOF tDC tJ
Conditions
Min.
Typ.
Max.
20
Units
MHz MHz MHz ns ns % ps
96 0.8 to 2.0 V 2.0 to 0.8 V At VDD/2 Single cycle measurement; Deviation from mean 10 S trigger delay 45 .6 .6 50 150
320 80 1.1 1.1 55
Long Term Timing Jitter, pk-pk VCO Gain
tJLT KO
1.7 340
3.0
ns MHz/V
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MK1575-01 CLOCK RECOVERY PLL
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
16
Millimeters Symbol
E1 IN D EX AR EA E
Inches Min Max
Min
Max
1
2
D
A 2 A 1
A
A A1 A2 b C D E E1 e L aaa
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004
c
-Ce
b S E A T IN G P LA N E L
aaa C
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MK1575-01 CLOCK RECOVERY PLL
Marking Diagram (commercial)
16 9
Marking Diagram (industrial)
16 9
1575-01G ###### YYWW
1 8
1
157501GI ###### YYWW
8
Marking Diagram (Pb free, commercial)
16 16
9
157501GL ###### YYWW
1 1
Notes: 1. ###### is the lot number. 2. YYWW is the last two digits of the year and the week number that the part was assembled. 3. "L" designates Pb (lead) free package. 4. "I" designates industrial temperature grade.
8
Ordering Information
Part / Order Number
MK1575-01G MK1575-01GTR MK1575-01GI MK1575-01GITR MK1575-01GLF MK1575-01GLFTR
Marking
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel
Package
16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP
Temperature
0 to + 70 C 0 to + 70 C -40 to + 85 C -40 to + 85 C 0 to + 70 C 0 to + 70 C
see Marking Diagrams above
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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