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CXD1914Q
Digital Video Encoder For the availability of this product, please contact the sales office.
Description The CXD1914Q is a digital video encoder designed for DVDs, set top boxes, digital VCRs and other digital video equipment. This device accepts ITU-R601 compatible Y, Cb and Cr data, and the data are encoded to composite video and separate Y/C video (S-video) signals and converted to RGB/YUV signals. Features * NTSC and PAL encoding modes * Composite video and separate Y/C video (S-video) signal output * R, G, B/Y, U and V (BetaCam/SMPTE level) signal output * 8/16-bit pixel data input modes * 13.5 Mpps pixel rate * 10-bit 6-channel DAC * Supports I2C bus (400 kHz) and Sony SIO * Closed Caption (Line 21, Line 284) encoding * Macrovision Pay-Per-View copy protection system : NTSC Rev. 7.0, PAL Rev. 6.1 (Note 1) * VBID encoding * WSS encoding * Supports non-interlace mode * Monolithic CMOS single 5.0 V power supply * 100-pin plastic QFP 100 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VDD -0.3 to +7.0 * Input voltage VI -0.3 to +7.0 * Output voltage VO -0.3 to +7.0 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -40 to +125 (VSS=0 V) Recommended Operating Conditions * Supply voltage VDD 4.75 to 5.25 * Input voltage VIN VSS to VDD * Operating temperature Topr 0 to +70 I/O Pin Capacitance * Input pin * Output pin
V V V C C
V V C
CI CO
11 (Max.) 11 (Max.)
pF pF
Note) Test conditions : VDD=VI=0 V, fM=1 MHz
(Note 1) This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial home use only. Reverse engineering or disassembly is prohibited. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E96Z29-TE
Block Diagram
R/U-OUT G/Y-OUT B/V-OUT
PDCLK YUV/RGB translator
10bit DAC 10bit DAC
1/2 Interpolator
Internal CLK
10bit DAC
SYSCLK Delay
10bit DAC
PD0-7
PD8-15 LPF Modulator LPF
CROMA
COMP-O
10bit DAC 10bit DAC
XRST
Y Dempx, Level Translator U and interpolator 4:2:2 to V 4:4:4 Interpolator
Y-OUT C-OUT VG
BURST FLAG CSYNC SYNC Slope Gen. Sub Carrier Gen. IREF VREF VB
--2--
Closed Caption Encoder (for NTSC) MACRO VISION Signal Gen. VBID & WSS Gen.
VSYNC HSYNC FID CSYNC
SYNC Gen. and Timing Controller
XVRST
TDO TDI JTAG TMS TCK TRST
SO SI/SDA SCK/SCL XCS/SA XIICEN
I2C-Bus and SIO Controller
XTEST1-5 CXD1914Q
CXD1914Q
Pin Description Pin No. Symbol I/O Description Field ID input. This signal indicates the field ID when resetting the vertical sync. "H" indicates 1st field. "L" indicates 2nd field. Test pin. Set "L". Test pin. Set "L". Test pin. Set "L". Test pin. Set "L". Test pin. Set "L". Vertical sync reset input in active low. This pin is pulled up. This is used for synchronizing the phases of the external and internal vertical sync signals. When XVRST= "L", the internal digital sync generator is reset according to the F1 status. System clock input. To generate the correct subcarrier frequency, precise 27 MHz is required. Digital ground. System reset input in active low. Set "L" for 40 clocks (SYSCLK) or more during power-on reset. Pixel data clock signal output for 13.5 MHz. A 13.5 MHz signal frequency divided from the system clock (SYSCLK) is output and used as the clock signal when 16-bit pixel data is input. Digital power supply. Not connected inside the IC. Field ID output. When control register bit "FIDS" = "1", "L" indicates 1st field and "H" indicates 2nd field. When control register bit "FIDS" = "0", "H" indicates 1st field and "L" indicates 2nd field. Vertical sync signal output. Horizontal sync signal output. Composite SYNC output when using RGB output. Digital ground.
1
F1
I
2 3 4 5 6
TVSYNC OSDSW ROSD GOSD BOSD
I I I I I
7
XVRST
I
8 9 10
SYSCLK VSS1 XRST
I -- I
11 12 13
PDCLK VDD1 NC
O -- --
14
FID
O
15 16 17 18 19 20 21 22 23
VSYNC HSYNC CSYNC VSS2 PD0 PD1 PD2 PD3 VDD2
O O O -- I I I I --
8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is input. [PD0 to 7] When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr signal inputs. When control register bit "PIF MODE" = "1", these are Y signal inputs.
Digital power supply.
--3--
CXD1914Q
Pin No. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Symbol PD4 PD5 PD6 PD7 NC NC NC NC NC PD8 / TD0 PD9 / TD1 PD10 / TD2 PD11 / TD3 VSS3 PD12 / TD4 PD13 / TD5 PD14 / TD6 PD15 / TD7 VDD3 XIICEN
I/O I I I I -- -- -- -- -- I/O I/O I/O I/O -- I/O I/O I/O I/O -- I Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC.
Description
8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is input. [PD0 to 7] When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr signal inputs. When control register bit "PIF MODE" ="1", these are Y signal inputs.
Upper 8-bit pixel data inputs/test data bus when 16-bit pixel data is input. [PD8 to 15] When control register bit "PIF MODE" = "0", these inputs are not used. When control register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs. In the test mode, these are used for the internal circuit test data bus. The test data bus is available only for the device vendor. Digital ground. Upper 8-bit pixel data inputs/test data bus when 16-bit pixel data is input. [PD8 to 15] When control register bit "PIF MODE" = "0", these inputs are not used. When control register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs. In the test mode, these are used for the internal circuit test data bus. The test data bus is available only for the device vendor. Digital power supply. Serial interface mode select input. This pin is pulled up. When XIICEN = "L", Pins 44, 45, 47 and 48 are I2C bus mode. When XIICEN = "H", Pins 44, 45, 47 and 48 are Sony SIO mode. This pin's function is selected by XIICEN (Pin 43). This pin is pulled up. When XIICEN = "H", this pin is Sony SIO mode ; XCS chip select input. When XIICEN = "L", this pin is I2C bus mode ; SA slave address select input which selects the I2C bus slave address. This pin's function is selected by XIICEN (Pin 43). When XIICEN = "H", this pin is Sony SIO mode ; SCK serial clock input. When XIICEN = "L", this pin is I2C bus mode ; SCL input. Digital ground. --4--
44
XCS/SA
I
45 46
SCK/SCL VSS4
I --
CXD1914Q
Pin No. 47
Symbol
I/O
Description This pin's function is selected by XIICEN (Pin 43). When XIICEN = "H", this pin is Sony SIO mode ; SI serial data input. When XIICEN = "L", this pin is I2C bus mode ; SDA input/output. This pin's function is selected by XIICEN (Pin 43). When XIICEN = "H", this pin is Sony SIO mode ; SO serial out output. When XIICEN = "L", this pin is not used and output is high impedance. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. DAC reference current input. Connect resistance "16R" which is 16 times output resistance "R". DAC reference voltage input. Sets the DAC output full-scale width. 10-bit DAC output. This pin outputs the composite signal. Analog power supply. 10-bit DAC output. This pin outputs the chroma (C) signal. Analog ground. Not connected inside the IC. Connect to ground via a capacitor of approximately 0.1 F. Connect to analog power supply via a capacitor of approximately 0.1 F. Not connected inside the IC. 10-bit DAC output. This pin outputs the luminance (Y) signal. Analog power supply. 10-bit DAC output. This pin outputs the B and V signals. Analog ground. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. 10-bit DAC output. This pin outputs the G and Y signals. Analog power supply. 10-bit DAC output. This pin outputs the R and U signals. Analog ground. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. Digital power supply.
SI/SDA
I/O
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
SO NC NC NC NC NC IREF VREF CP-OUT AVDD1 C-OUT AVSS1 NC VB VG NC Y-OUT AVDD2 B-OUT AVSS2 NC NC NC NC G-OUT AVDD3 R-OUT AVSS3 NC NC NC NC NC VDD4
O -- -- -- -- -- I I O -- O -- -- O O -- O -- O -- -- -- -- -- O -- O -- -- -- -- -- -- --
--5--
CXD1914Q
Pin No. 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol TD8 TD9 TD10 XTEST1 XTEST2 XTEST3 XTEST4 XTEST5 VSS5 TDI TMS TDO TCK TRST VDD5 NC NC NC NC
I/O I/O I/O I/O I I I I I -- I I O I I -- -- -- -- --
Description Test data I/Os. These pins should be open. In the test mode, these are used for the internal circuit test data bus. The test data bus is available only for the device vendor. Test mode control signal inputs. These pins are pulled up. When all these pins are "H", the CXD1914Q is not in the test mode, but is in the normal mode. The test mode is available only for the device vendor. Digital ground. Test pin. Set "H". This pin is pulled up. Test pin. Set "H". This pin is pulled up. Test pin. This pin should be open. Test pin. Set "H". Reset signal input for JTAG in active low. This pin is pulled up. Digital power supply. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC. Not connected inside the IC.
--6--
CXD1914Q
Electrical Characteristics DC Characteristics Item Input High voltage Input Low voltage Output High voltage Output Low voltage Output High voltage Output Low voltage Input leak current Input leak current Supply current Symbol VIH VIL VOH1 VOL1 VOH2 VOL2 IIL1 IIL2 IDD Measurement Measurement conditions Min. pins 2.2 1 VDD=5.0 V 5 % 1 VDD=5.0 V 5 % IOH=-2.4 mA VDD-0.8 2 VDD=4.75 to 5.25 V IOL=4.8 mA 2 VDD=4.75 to 5.25 V IOH=-1.2 mA 3 VDD-0.8 VDD=4.75 to 5.25 V IOL=2.4 mA 3 VDD=4.75 to 5.25 V VI=0 to 5.25 V 4 -10 VDD=4.75 to 5.25 V VI=0 V 5 -40 VDD=5.0 V 5 % VDD=5.0 V 5 % (Ta=0 to +70 C, VSS=0 V) Typ. Max. Unit V V V 0.4 V V 0.4 10 -100 -240 856 V A A mA
0.8
Note : 1 PD0-15, TD8-10, XTEST1-5, TRST, TDI, TMS,TCK, SI/SDA, SCK/SCL, XCS/SA, XVRST, XRST, SYSCLK, F1, XIICEN, TVSYNC, OSDSW, ROSD, GOSD, BOSD 2 PDCLK, VSYNC, HSYNC, FID, SO, CSYNC 3 TDO, TD0-10 4 PD0-15, TD8-10, TCK, SI/SDA, SCK/SCL, XRST, F1, SYSCLK, TVSYNC, OSDSW,ROSD, GOSD, BOSD 5 XTEST1-5, TRST, TDI, TMS, XCS/SA, XVRST, XIICEN 6 Not including analog supply current
DAC Characteristics 1 Item Resolution Linearity error Differential linearity error Output full-scale current Output offset voltage Output full-scale voltage Precision guaranteed output voltage range Symbol n EL ED IFS VOS VFS VOC
(AVDD=5 V, R=200 , VREF=2.00V , Ta=25 C) Measurement conditions Min. -2.0 -1.0 9.5 1.9 1.9 Typ. 10 Max. 2.0 1.0 10.5 1 2.1 2.1 Unit bit LSB LSB mA mV V V
10.0 2.0 2.0
--7--
CXD1914Q
AC Characteristics 1. Pixel data interface (1) 8-bit mode
SYSCLK tPDS PD0-7 tPDH
(Ta=0 to +70 C, VDD=4.75 to 5.25 V, VSS=0 V) Item Pixel data setup time to SYSCLK Pixel data hold time to SYSCLK Symbol tPDS tPDH Min. 10 3 Typ. Max. Unit ns ns
(2) 16-bit mode
PDCLK tPDS PD0-15 tPDH
(Ta=0 to +70 C, VDD=4.75 to 5.25 V, VSS=0 V) Item Pixel data setup time to PDCLK Pixel data hold time to PDCLK Symbol tPDS tPDH Min. 20 0 Typ. Max. Unit ns ns
--8--
CXD1914Q
2. Serial port interface
fSCK tPWLSCK SCK tCSS XCS tSIS SI tSIH tCSH tPWHSCK
tSOD SO
tSOH
(Ta=0 to +70 C, VDD=4.75 to 5.25 V, VSS=0 V) Item SCK clock rate SCK pulse width Low SCK pulse width High Chip select setup time to SCK Chip select hold time to SCK Serial input setup time to SCK Serial input hold time to SCK Serial output delay time from SCK Serial output hold time from SCK Symbol fSCK tPWLSCK tPWHSCK tCSS tCSH tSIS tSIH tSOD tSOH Min. DC 100 100 150 150 50 10 3 Typ. Max. 3 Unit MHz ns ns ns ns ns ns ns ns CL=35 pF
30
3. XVRST, F1
SYSCLK
tVS XVRST F1
tVH
Item XVRST, F1 setup time to SYSCLK XVRST, F1 hold time to SYSCLK --9--
Symbol tVS tVH
Min. 10 0
Typ.
Max.
Unit ns ns
CXD1914Q
4. SYSCLK, PDCLK, VSYNC, HSYNC, FID, CSYNC
fSYSCLK tPWHCLK tPWLCLK
SYSCLK tPDCLKD PDCLK tCOD VSYNC, HSYNC, FID, CSYNC tCOH tPDCLKD
(Ta=0 to +70 C, VDD=4.75 to 5.25 V, VSS=0 V) Item SYSCLK clock rate SYSCLK pulse width Low SYSCLK pulse width High PDCLK delay time from SYSCLK Control output delay time from SYSCLK Control output hold time from SYSCLK Symbol fSYSCLK tPWLCLK tPWHCLK tPDCLKD tCOD tCOH Min. 11 11 20 25 3 Typ. 27 Max. Unit MHz ns ns ns ns ns CL=35 pF
--10--
CXD1914Q
Description of Functions The CXD1914Q converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC (RS170A) or PAL (ITU-R624; B, G, H, I) format. The CXD1914Q first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts the Cb and Cr signals into the U and V signals, respectively, interpolates 4 : 2 : 2 to 4 : 4 : 4, and then modulates the signals with the digital subcarrier inside the CXD1914Q to create the chroma (C) signal. The Y and chroma (C) signals are oversampled at double speed to reduce sin (X) / X roll-off, and then added to become the digital composite signal. The 10-bit DAC converts the digital composite, Y/C, U, V, and RGB signals into analog signals. 1. Pixel input format The pixel input format is selected according to the value (bit 4 of address 01H) of control register "PIF MODE" as shown in Table 1-1 below. When "PIF MODE" is "0", the image data (multiplexed Y, Cb, and Cr data) input from PD0 to 7 are sampled at the rising edge of SYSCLK as shown in the chart on the following page. When "PIF MODE" is "1", the image data (PD0 to 7 : Y data, PD8 to 15 : multiplexed Cb and Cr data) input from PD0 to 15 are sampled at the rising edge of PDCLK. PIF MODE 0 (8-bit mode) 1 (16-bit mode) PD15 to 8 N/A Cb/Cr Table 1-1 PD7 to 0 Y/Cb/Cr Y
Also, the pixel input data timing is determined according to bits 3 and 2 (PIX TIM) of control register address 01H as shown in Table 1-2 below. When "PIF MODE" is "0", Cb0 of the image data (Cb0, Y0, Cr0 and Y1) input from PD0 to 7 is sampled at the rising edge of SYSCLK after the fall of HSYNC. (Default : Cb0 is sampled at the rising edge of the second SYSCLK after the fall of HSYNC.) When "PIF MODE" is "1", Y0 and Y1 data are input to PD0 to 7, multiplexed Cb0 and Cr0 data are input to PD8 to 15, and Y0 and Cb0 are sampled at the respective rising edge of PDCLK after the fall of HSYNC. (Default : Y0 and Cb0 are sampled at the rising edge of the second PDCLK after the fall of HSYNC.) PIX TIM 0 0 1 1 0 1 0 1 Timing phase #0 (default) #1 #2 #3 Table 1-2
--11--
CXD1914Q
Pixel Data Input Timing
1 SYSCLK
2
3
4
5
1 PDCLK HSYNC
2
3
[16-bit mode] PD0 to 7 # 0 #1 PD8 to 15 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Y0 Y1 Y2 Y3 Y4 Y5
Y0 # 2 #3 Cb0 [8-bit mode] PD0 to 7 #0 #1 #2 #3 Cb0 Cb0 Y0 Cb0 Y0 Cr0 Y1 Cb0 Y0 Cr0 Cb2 Y0 Cr0 Y1 Y2 Cr0 Y1 Cb2
Y1 Cr0
Y2 Cb2
Y3 Cr2
Y4 Cb4
Cr2 Y1 Cb2 Y2
Y3 Cb2 Y2 Cr2
Cb4 Y2 Cr2 Y3
Y4 Cr2 Y3 Cb4
Cr4 Y3 Cb4 Y4
Y5 Cb4 Y4 Cr4
Cb6 Y4 Cr4 Y5
PD0 PD1 : PD7
Pixel data 0 (LSB) Pixel data 1 : Pixel data 7 (MSB)
PD8 PD9 : PD15
Pixel data 0 (LSB) Pixel data 1 : Pixel data 7 (MSB)
--12--
CXD1914Q
2. Serial interface The CXD1914Q supports both the I2C bus (high-speed mode) and Sony serial interface modes. These modes can be selected by the XIICEN input pin as shown in Table 2-1 below. H SONY SIO Mode SI SCK XCS SO Table 2-1 L Mode SDA SCL SA High-Z
XIICEN SI/SDA SCK/SCL XCS/SA SO
I2C
2-1 I2C bus interface The CXD1914Q becomes an I2C bus slave transceiver, and supports the 7-bit slave address and the high-speed mode (400 Kbits/s). 2-1-1. Slave address Two kinds of slave address (88H, 8CH) can be selected by the SA signal as shown in Table 2-2 below. A6 1 A5 0 A4 0 A3 0 A2 1 A1 SA A0 0 R/W X
Table 2-2
2-1-2. Write cycle
S Slave address W `0' from master to slave from slave to master A start address A write data A write data A P
D7 Start address
D6
D5
D4
D3
D2
D1
D0
ADR [4 : 0]
After the slave address is supplied from the master, the data in the next transfer cycle is set up inside the start address register of this IC as the start address of the control register. In subsequent cycles, the data supplied from the master is written in the addresses indicated by the control register address. The set control register address is automatically incremented with the completed transfer of each byte of data.
--13--
CXD1914Q
2-1-3. Read cycle
S Slave address R `1' from master to slave from slave to master A read data A read data A P
After the slave address is supplied from the master, subsequent cycles change immediately to read cycles and only the ID code (address 0CH, 0DH) is read out. During the read cycle, the start address is automatically set to 0CH. (Note) In the Sony SIO mode, addresses from 00H to 0DH can be read out.
2-1-4. Handling of the general call address (00H) The general call address is ignored and there is no ACK response.
--14--
CXD1914Q
2-2. Sony serial interface The Sony serial interface uses the SCK, XCS, SI and SO signals. The serial interface is active when the XCS signal is Low and transmits and receives signals to and from the host. The first byte after the XCS signal becomes Low is set up as a serial control command. Its data includes a control register address and read/write mode information for the interface. (See 2-2-1. Serial control command format.) The control register address is automatically incremented with the transfer of each byte of data. In the write mode, the SI signal of the serial input data is sampled at the rising edge of the SCK signal. In the read mode, the register value is read out as the SO signal of the serial output data at the falling edge of the SCK signal, and is variable. In this case, the SI signal of the serial input data is ignored.
Serial Interface Timing SCK XCS SI SO Serial Interface Sequence SCK XCS SI 00H FFH 00H Internal address Control register address set Control register address auto-increment Control register address auto-increment 01H 11H CEH 02H D0
LSB
D1
D2
D3
D4
D5
D6
D7
MSB
D0
LSB
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7
MSB
Serial Control Command
Serial Data
D0
D7
Control Register Address 00H 01H 02H
Control Register Data FFH 11H CEH
2-2-1. Serial control command format D7 WR WR D6 D5 D4 D3 D2 D1 D0
ADR [4 : 0]
: Read/write mode When this bit is "1" : The serial interface is write mode, and the SI signal of the serial input data is written in the register. When this bit is "0" : The serial interface is read mode, and the register value is read out as the SO signal of the serial output data.
ADR [4 : 0] : Control register address setting (Initial value of the address) --15--
CXD1914Q
3. XVRST, F1 The XVRST and F1 signals are used to synchronize with the external V sync. The XVRST and F1 signals are sampled at the rising edge of SYSCLK, and the F1 signal is sampled when XVRST is Low. When F1 is High, the internal sync generator is reset to the 1st field, and when F1 is Low, it is reset to the 2nd field. When XVRST is set to High, the digital sync generator starts operation, and the sequence of the 1st or 2nd field starts. In the 16-bit mode, input XVRST with a width of four SYSCLK pulses at the rise of PDCLK.
[8-bit mode] XVRST Timing (1st Field)
SYSCLK
XVRST
F1 "H" VSYNC F-ID HSYNC
Start of 1st field
(NTSC : 4H) (PAL : 1H)
XVRST Timing
(2nd Field)
SYSCLK
XVRST
F1 "L" Start of 2nd field VSYNC F-ID 1/2H HSYNC (NTSC : 266H) (PAL : 313H)
--16--
CXD1914Q
[16-bit mode] XVRST Timing (1st Field)
SYSCLK PDCLK
XVRST
F1 "H" Start of 1st field VSYNC F-ID HSYNC (NTSC : 4H) (PAL : 1H)
XVRST Timing
(2nd Field)
SYSCLK PDCLK
XVRST
F1 "L" Start of 2nd field VSYNC F-ID 1/2H HSYNC (NTSC : 266H) (PAL : 313H)
--17--
CXD1914Q
4. Closed caption The CXD1914Q supports closed caption encoding. ASCII data for closed captions are encoded in line 21 and line 284 by adding a parity bit to every ASCII data set up in control registers 04H, 05H (data #1 and #2 for line 21) and 06H, 07H (data #1 and #2 for line 284). The control registers (04H to 07H) are double-buffered and ASCII data, which are set up by the serial interface, are synchronized with VSYNC. Automatic reset on/off can be selected for ASCII data which has been synchronized with VSYNC by changing the setting of bit 5 (CCRST) of control register address 03H. When CCRST="1", the control registers (04H, 05H or 06H, 07H) are automatically reset in sync with the rise of the next VSYNC. When CCRST="0" (default), the control registers (04H, 05H or 06H, 07H) are not reset, and the data set last is held. Closed Caption Data Renewal Timing
When CCRST="1" Field VSYNC Control registers 04H and 05H set SI/SDA Data 21H Front-end buffer Data 21H Rear-end buffer Data 284H Front-end buffer Data 284H Rear-end buffer DATA A OLD DATA OLD DATA DATA RESET (7'h00) DATA A (7' h00) NEW DATA NEW DATA (7' h00) NEW DATA 4 field 1 field
Field VSYNC
1 field
2 field
Control registers 06H and 07H set SI/SDA Data 284H Front-end buffer Data 284H Rear-end buffer Data 21H Front-end buffer Data 21H Rear-end buffer DATA A OLD DATA OLD DATA DATA RESET (7'h00) DATA A (7' h00) NEW DATA NEW DATA (7' h00) NEW DATA
--18--
CXD1914Q
When CCRST="0" Field VSYNC Control registers 04H and 05H set SI/SDA Data 21H Front-end buffer Data 21H Rear-end buffe Data 284H Front-end buffer Data 284H Rear-end buffe OLD DATA OLD DATA DATA A DATA A NEW DATA NEW DATA NEW DATA 4 field 1 field
Field VSYNC
1 field
2 field
Control registers 06H and 07H set SI/SDA Data 284H Front-end buffer Data 284H Rear-end buffe Data 21H Front-end buffer Data 21H Rear-end buffe OLD DATA OLD DATA DATA A DATA A NEW DATA NEW DATA NEW DATA
Double Buffer for Closed Caption
SI 04H
VSYNC
Load
ASCII data #1
Closed Caption Signal Waveform
HSYNC Color Burst Clock Run-In Start Bits ASCII Data #1 ASCII Data #2
S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2
50 IRE
--19--
CXD1914Q
5. VBID (Video ID) The CXD1914Q supports encoding of Video ID (Provisional Standard EIAJ CPX-1204) to discriminate the aspect ratio. VBID is 14-bit data as shown in Table 5-1, and becomes 20-bit data with the addition of 6-bit CRCC. These data are superimposed and output to lines 20 and 283 during the vertical blanking period of NTSC video signals. The data setting in Table 5-1 below is done by writing data in control registers (08H and 09H) via the serial interface. These control registers (08H and 09H) are double-buffered, and the VBID data are renewed in sync with the VSYNC signal.
bit-No. 1 2 3 4 5 6 4-bit width 4-bit width Contents Transmission aspect ratio Image display format Undefined "1" Full-mode (16 : 9) Letter-box "0" 4:3 Normal
A Word 0 B Word 1 Word 2
Identification information about video and other signals (audio signals, etc.) incidental to image which are transmitted simultaneously Identification signal incidental to Word 0 Identification signal and information incidental to Word 0 Table 5-1
Double Buffer for VBID
SI 08H
VSYNC
Load
Word 0
VBID Data Renewal Timing
VSYNC Control register 08H set SI NEW DATA
Data #1
OLD DATA
NEW DATA
--20--
CXD1914Q
VBID Code Allocation The VBID data are composed of Word 0=6 bits (Word 0-A=3 bits and Word 0-B=3 bits), Word 1=4 bits, Word 2=4 bits, and CRCC=6 bits.
bit 0... Data ...bit 20
0-A Word 0 6 bits
0-B
Word 1 4 bits
Word 2 4 bits
CRCC 6 bits
VBID Signal Waveform
Ref.
bit 1 bit 2 bit 3
...
bit 20
2.235s20ns
11.2s0.6s 1H
49.1s0.5s
6. RGB/YUV output The CXD1914Q has an RGB/YUV output function. RGB and YUV can be switched by setting bit 2 (RGB_ UV) of control register address 03H. Also, the UV level can be selected from BetaCam or SMPTE by setting bit 0 (BTCM) of address 03H. During RGB output, when bit 1 (GSYNC) of control register address 03H is "1", the sync signal is added to the G signal and output ; when bit 1 (GSYNC) is "0", the sync signal is not added. 7. Support of interlace/non-interlace modes The CXD1914Q can be switched to the interlace and non-interlace modes by varying the setting of bit 1 (INTERLS) of control register address 01H. During the non-interlace mode, the 1st field is repeatedly output. Register setting value INTERLS 0 (non-interlace) 1 (interlace) Number of lines/field NTSC PAL 262 312 262.5 312.5 --21--
CXD1914Q
8. WSS (Widescreen Signaling) The CXD1914Q supports WSS encoding to discriminate the aspect ratio. WSS is 14-bit data as shown in Table 6-1. These data are superimposed and output to line 23 during the vertical blanking period of PAL video signals. The data setting in Table 6-1 below is done by writing data in control registers (0AH and 0BH) via the serial interface. These control registers (0AH and 0BH) are double-buffered, and the WSS data are renewed in sync with the VSYNC signal. Group 1 Aspect ratio information (4 bits) b0-b3 0001 1000 0100 1101 0010 1011 0111 1110 Normal Letter-box 14 : 9 Letter-box 14 : 9 Letter-box 16 : 9 Letter-box 16 : 9 Letter-box >16 : 9 Full-mode 14 : 9 Full-mode 16 : 9 Group 2 PAL plus related information (4 bits) b4-b7 bit4 Camera/Film mode bit5-7 Reserved (Color plus) (Helper) (Baseband Helper)
Center Top Center Top Center
b3 is odd parity. Group 3 Subtitle information (3 bits) b8-b10 bit8 TeleText subtitle enable/disable bit9, 10 00 No subtitle 10 Subtitle inside screen 01 Subtitle in black portion 11 Reserved b11-b13 Group 4 Undefined (3 bits)
Reserved
Table 6-1 Double Buffer for WSS
SI 0AH
VSYNC
Load
Group 1, 2
WSS Data Renewal Timing
VSYNC Control register 0AH set SI NEW DATA
Data #1
OLD DATA
NEW DATA
--22--
CXD1914Q
WSS Signal Waveform
bit 0 bit 1 bit 2 bit 3 649
RUN -IN Start Code
...
bit 13 71.4 IRE
256
0 IRE
20 11.03s 10.67s 16.59s
--23--
Fields 1 and 3 Vertical blanking Pre-equalization Vertical sync 3H Post-equalization 3H 3H
524
525
1
2
3
4
5
6
7
8
9
10
11
19
20
21
22
23
HSYNC
VSYNC
Signal Waveform of NTSC Vertical Blanking Interval (Interlace mode)
--24--
Fields 2 and 4 263 264 265 266 267 268 269 270 271 272 273 274
FID
261
262
282
283
284
285
HSYNC
VSYNC
FID CXD1914Q
Fields 1 and 3
(2) (4) (4) (3) 2.5H 2.5H 2.5H (1) (3)
620
621
622
623
624
625
1
2
3
4
5
6
7
8
20
21
22
23
24
HSYNC
VSYNC
FID
(1) (3) (3) (2) Fields 2 and 4 (4) (2)
Signal Waveform of PAL Vertical Blanking Interval (Interlace mode)
--25--
309 310 311 312 313 314 315 316 317 318 319 320 321 Field 1 Field 2 Field 3 Field 4
308
333
334
335
336
HSYNC
VSYNC
FID
Meander gate
CXD1914Q
Field 1 1 Vertical blanking Pre-equalization 3H 3H 3H Vertical sync Post-equalization
523
524
1
2
3
4
5
6
7
8
9
10
11
19
20
21
22
23
HSYNC
VSYNC
FID Field 2 1
"0"
Signal Waveform of NTSC Vertical Blanking Interval (Non-interlace mode)
--26--
263 264 265 266 267 268 269 270 271 272 273
261
262
281
282
283
284
285
HSYNC
VSYNC
FID "0"
CXD1914Q
1 No differentiation is made between Fields 1 and 2 to facilitate the frame description.
Field 1 1
2H
2.5H
2.5H
620
621
622
623
624
1
2
3
4
5
6
7
8
20
21
22
23
24
HSYNC
VSYNC
FID
"0" Field 2 1 2H 2.5H 2.5H
Signal Waveform of PAL Vertical Blanking Interval (Non-interlace mode)
--27--
311 312 313 314 315 316 317 318 319 320
308
309
310
332
333
334
335
336
HSYNC
VSYNC
FID
"0" CXD1914Q
1 No differentiation is made between Fields 1 and 2 to facilitate the frame description.
CXD1914Q
Sync Signal Timing
0.148s
0.148s
2.3s
29.5s
27.1s 1/2H 63.555s
4.67s
NTSC Equalizing Pulse and Sync Pulse Signal Waveform
0.296s
0.296s
2.37s
29.63s
27.3s 1/2H 64s
4.67s
PAL Equalizing Pulse and Sync Pulse Signal Waveform
--28--
CXD1914Q
Control Register Map When "0" or "1" is indicated in the map, fix the respective bits to these values.
BIT Function Selection #1 7 Address 00H FIDS 6 MASK EN 5 PIX EN 4 0 3 BF 2 SET UP 1 0 0 ENC MODE R/W
ENC MODE
Encoding mode 0 : PAL encoding mode 1 : NTSC encoding mode (Default) Setup enable 0 : No setup level, black level=blanking level 1 : 7.5 IRE setup level insertion (Default) Burst flag enable 0 : Disable burst flag 1 : Enable burst flag (Default) Pixel data enable 0 : Disable input pixel data 1 : Enable input pixel data (Default) Mask enable 0 : Pixel data through during vertical blanking 1 : Pixel data reject during vertical blanking (Default) FID polarity select 0 : 1st field "H", 2nd field "L" 1 : 1st field "L", 2nd field "H" (Default)
SET UP
BF
PIX EN
MASK EN
FIDS
--29--
CXD1914Q
BIT Function Selection #2 7 Address 01H INTERLS DAC 0 1 6 MODE 5 4 PIF MODE 3 PIX TIM 2 1
INTERLS
0 1 R/W
: Non-interlace mode : Interlace mode (Default)
PIXTIM
Pixel input timing 0 0 : #0 (Default) 0 1 : #1 1 0 : #2 1 1 : #3 Pixel input format 0 : 8-bit mode, multiplexed Y, Cb, Cr (4 : 2 : 2) (Default) 1 : 16-bit mode, Y and multiplexed Cb, Cr (4 : 2 : 2) DAC output activity 0 0 0 : Non-active 0 0 1 : Comp-Out active 0 1 0 : Inhibit 0 1 1 : Video signal (Y, C, Comp) -Out active (Default) 1 0 0 : Inhibit 1 0 1 : R, G, B-Out and Comp-Out active 1 1 0 : Inhibit 1 1 1 : All outputs active
PIF MODE
DAC MODE
Function Selection #3 7 Address 02H CC MODE 0
6 0
5 0
4 0
3 VBID
2 WSS
1
0 R/W
CC Mode
Closed caption encoding mode 0 0 : Disable closed caption encoding (Default) 0 1 : Enable encoding in 1st field (Line 21) 1 0 : Enable encoding in 2nd field (Line 284) 1 1 : Enable encoding in both fields WSS encoding enable 0 : Disable WSS encoding (Default) 1 : Enable WSS encoding VBID encoding enable 0 : Disable VBID encoding (Default) 1 : Enable VBID encoding --30--
WSS
VBID
CXD1914Q
BIT Function Selection #4 7 Address 03H BTCM 6 5 CCRST UV output level control 0 : SMPTE 1 : BetaCam (Default) GON SYNC enable 0 : Disable (Default) 1 : Enable RGB/YUV output mode switching 0 : YUV (Default) 1 : RGB Closed caption character RESET enable 0 : Disable (Default) 1 : Enable 4 0 3 0 2 1 0 BTCM R/W
RGB_UV GSYNC
GSYNC
RGB_UV
CCRST
Closed Caption Character #1 (Line 21H) 7 Address 04H 6 5 4 3 2 1 0 R/W
ASCII Data #1
(Default : 0H)
Closed Caption Character #2 (Line 21H) 7 Address 05H 6 5 4 3 2 1 0 R/W
ASCII Data #2
(Default : 0H)
Closed Caption Character #1 (Line 284H) 7 Address 06H 6 5 4 3 2 1 0 R/W
ASCII Data #1
(Default : 0H)
Closed Caption Character #2 (Line 284H) 7 Address 07H 6 5 4 3 2 1 0 R/W
ASCII Data #2 --31--
(Default : 0H)
CXD1914Q
BIT VBID #1 7 Address 08H 6 5 4
Word 0-B
3 Word 0
2
1
Word 0-A
0 R/W
VBID #2 7 Address 09H 6 Word 2 5 4 3 2 Word 1 1 0 R/W
WSS #1 7 Address 0AH bit 7 6 Group 2 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 Group 1 bit 1 0 bit 0 R/W
WSS #2 7 Address 0BH 6 5 bit 13 4 Group 4 bit 12 3 bit 11 2 bit 10 1 Group 3 bit 9 0 bit 8 R/W
Device ID #1 7 Address 0CH ID code Device ID #2 7 Address 0DH ID code 6 5 4 ID Code Identification code : 19H 3 2 1 0 RO 6 5 4 ID Code Identification code : 14H 3 2 1 0 RO
(Lower) 14H
(Upper) 19H
--32--
CXD1914Q
Video Signal Timing (NTSC, 7.5 IRE Setup)
MAGENTA
YELLOW
GREEN
WHITE
CYAN
806
806 748 655 597
BLUE
RED
BLACK
WHITE LEVEL
100 IRE 7.5 IRE 256 40 IRE 36
506 448 355 297 BLACK LEVEL BLANK LEVEL
SYNC LEVEL
NTSC Y (luminance) signal output waveform 7.5 IRE setup
YELLOW (227)
GREEN (299)
CYAN (320)
MAGENTA (299)
BLUE (227)
RED (320)
832
622 20 IRE 512 402 COLOR BURST 192 BLANK LEVEL
NTSC C (chroma) signal output waveform 7.5 IRE setup
WHITE
--33--
BLACK
CXD1914Q
Video Signal Timing (NTSC, No Setup)
MAGENTA
YELLOW
GREEN
WHITE
CYAN
806
806 744 643 580
BLUE
RED
BLACK
WHITE LEVEL
100 IRE
482 419 318 BLANK LEVEL
256 40 IRE 36
SYNC LEVEL
NTSC Y (luminance) signal output waveform
YELLOW (245)
GREEN (324)
CYAN (347)
MAGENTA (324)
BLUE (245)
RED (347)
859
622 20 IRE 512 402 COLOR BURST 165 BLANK LEVEL
NTSC C (chroma) signal output waveform
WHITE
--34--
BLACK
CXD1914Q
Video Signal Timing (PAL)
MAGENTA
YELLOW
GREEN
WHITE
CYAN
806
806 744 643 580
BLUE
RED
BLACK
WHITE LEVEL
100 IRE
482 419 318 BLANK LEVEL
256 43 IRE 20
SYNC LEVEL
PAL Y (luminance) signal output waveform
YELLOW (245)
GREEN (324)
CYAN (347)
MAGENTA (324)
BLUE (245)
RED (347)
859
630 21.5 IRE 512 394 COLOR BURST 165 BLANK LEVEL
PAL C (chroma) signal output waveform
WHITE
--35--
BLACK
CXD1914Q
RGB Signal Output Waveform
R signal
YELLOW
GREEN
MAGENTA
WHITE
806 100 IRE 256
806
806
257
257
805
805
256
BLUE
256
BLACK
WHITE LEVEL BLANK LEVEL 256
CYAN
GREEN
WHITE
806 100 IRE 256
806
807
806
806
256
256
256
BLUE
BLACK
WHITE LEVEL BLANK LEVEL WHITE LEVEL BLANK LEVEL SYNC LEVEL WHITE LEVEL BLANK LEVEL SYNC LEVEL 256
G signal
YELLOW
MAGENTA
CYAN
During GON SYNC (NTSC) 806 100 IRE 256 40 IRE 36
During GON SYNC (PAL) 806 100 IRE 256 43 IRE 20
GREEN
WHITE
806
806
257
808
259
803
256
806
BLUE
BLACK
WHITE LEVEL BLANK LEVEL
B signal
YELLOW
MAGENTA
CYAN
100 IRE
256
--36--
RED
RED
RED
CXD1914Q
UV Output Level Color Difference (U) Signal
SMPTE LEVEL
BetaCam LEVEL
MAGENTA
GREEN
GREEN
MAGENTA
YELLOW
BALCK
WHITE
WHITE
YELLOW
782 690 603 643 768
901
512
512
421 334 242 NTSC, No setup 761 677 596 633 750 123 256
381
NTSC, No setup 871
512
512
428 347 263 NTSC, Setup 787 693 605 605 693 153 274
391
NTSC, Setup 787
512
512
419 331 237 PAL 237 331
419
PAL
--37--
BALCK
CYAN
CYAN
BLUE
RED
RED
BLUE
CXD1914Q
Color Difference (V) Signal
SMPTE LEVEL
BetaCam LEVEL
MAGENTA
GREEN
GREEN
MAGENTA
YELLOW
BALCK
WHITE
WHITE
YELLOW
782 738 838
901
555 512 469 512
574
450
286 242 NTSC, No setup 123
186
NTSC, No setup
761 721 813
871
552 512 471 512
570
453
303 263 NTSC, Setup 153
211
NTSC, Setup
787 742 742
787
556 512 468 512
556
468
282 237 PAL 237
282
PAL
--38--
BALCK
CYAN
CYAN
BLUE
RED
RED
BLUE
CXD1914Q
Internal Filter Characteristics
Interpolation Filter Characteristic 0
-10
Attenuation [dB]
-20
-30
-40
-50 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Frequency [MHz]
Chrominance Filter Characteristic 0
-20
Attenuation [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 7 8 9 10 Frequency [MHz]
--39--
CXD1914Q
DAC Application Circuit
CXD1914Q
AVDD VG 0.1F VREF 3.2k IREF AVSS Buff AMP COMP-O Y-OUT C-OUT R/U-OUT G/Y-OUT B/V-OUT LPF 75 200 1k
0.1F VB
VSS
Application Circuit
CXD1914Q (Video encoder)
MPEG decoder
8 PD0 to 7 PD0 to 7
FID
FID
HSYNC
HSYNC
VSYNC
VSYNC
CLK
SYSCLK
27MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
--40--
CXD1914Q
Package Outline
Unit : mm
100PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05
81
50
+ 0.4 14.0 - 0.1 17.9 0.4
15.8 0.4
A 100 31
1
0.65
+ 0.15 0.3 - 0.1
30 0.13 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0.8 0.2
0 to 10
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g
--41--

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