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STV5342
TELETEXT DECODER WITH 4 INTEGRATED PAGES
. . . . . . . . . . .
COMPLETE TELETEXT DECODER INCLUDING ON-CHIP 4 PAGES MEMORY, REDUCING EMC RADIATIONS UPWARD SOFTWARE AND HARDWARE COMPATIBLE WITH PREVIOUS SGS-THOMSON's DECODER SDA5243 AUTOMATIC SELECTION OF UP TO SIX NATIONAL LANGUAGES 4 SIMULTANEOUS PAGE REQUESTS DISPLAY OF THE 25TH STATUS ROW MICROPROCESSOR CONTROL VIA AN I2C BUS (SLAVE ADDRESS 0010001 R/W) DATA ACQUISITION AVAILABLE FROM LINES 2 TO 22 OR FROM A COMPLETE FIELD HIGH QUALITY DISPLAY USING A CHARACTER MATRIX OF 12 x 10 DOTS SINGLE + 5V SUPPLY VOLTAGE ON-CHIP MASK PROGRAMMABLE ROM CHARACTER GENERATORS HCMOS PROCESS
DIP40 (Plastic Package) ORDER CODE : STV5342
PIN CONNECTIONS
VDD
1
40
2 RESERVED 3 4
5 TTD TTC 6
39 38 37
36 35
7 8 9
10 11 12
34 33 32
31 30 29
DESCRIPTION The STV5342 is a HCMOS integrated circuit which performs all the processing of logical data within a 625 lines system teletext decoder. It is designed to operate in conjunction with one-chip : the SAA5231 integrated chip which extracts Teletext information embedded in a composite video signal. Up to 4 pages of display data can be stored in internal memory. A complete system also comprises a microprocessor controlling the STV5342 via a 2-wires serial bus. An on-chip ROM memory contains the character sets. The STV5342 performs automatic selection of one of up to six natural languages. Data bytes may be decoded in either 7-Bit plus parity or in full 8-Bit formats. The chip set also supports facilities for reception and display of higher-level protocol data.
April 1994
ODD/EVEN F6
VCS
RESERVED
SAND TCS/SCS R
13 14 15
16 17
28 27 26
25 24
G B COR
BL AN Y
18 19 20
23 22 21
5342-01.EPS
SCL SDA
V SS
1/20
STV5342
PIN DESCRIPTION
Pin 1 2 to 5 22 to 40 6 Symbol VDD RESERVED TTD Teletext data input Function +5V Description Positive supply voltage Not used An A.C. coupled teletext data input supplied by the SAA5231 chip is latched to VSS between 4 and 8s after each TV line. A 6.9375MHz clock signal, supplied by the SAA5231 chip, is internally A.C. coupled, clamped and buffered. High for even numbered and low for odd numbered frames. The value is valid 2s before the end of lines 311 and 624. The 6MHz clock signal, supplied by the SAA5231 chip is internally A.C. coupled, clamped and buffered. Active high VCS input. Three level output pulse to the SAA5231 device. Phase lock, blanking signal, and color burst components are contained in this signal. Scan composite input signal (SCS) for the display synchronization or Text composite sync. (TCS) output signal to the SAA5231. Both signals are active low. Character and background colors active-high open-drain outputs. Open-drain active-low output supporting optimal display of characters in "mixed mode" operation. Open-drain active high output for TV-image blanking in normal and mixed-mode operation. Open-drain active-high output with foreground information. Can be used for printer command. Microprocessor clock input via serial bus.
5342-01.TBL
7
TTC
Teletext clock input
8
ODD/EVEN
Interlaced mode state output
9 10 11
F6 VCS SAND
Character display clock signal Video composite synchronization input signal Sandcastle
12
TCS/SCS
Input / output composite synchronization signal
13,14,15 16 17 18 19 20 21
RGB COR BLAN Y SCL SDA VSS
Red, green, blue Contrast reduction Blanking signal output Foreground output Serial clock Serial data input / output 0 Volt
Open-drain microprocessor serial data input/output via serial bus. Ground
2/20
STV5342
BLOCK DIAGRAM
TCS/ VCS SAND SCS
10
11
12
DATA
Pins 22 to 40 and Pins 2 to 5 not used
EXTERNAL MEMORY INTERFACE ADDRESS ADDRESS DATA CTRL CTRL
F6
9
TIME BASE
CLOC K
TTC
7 6
TTD
DATA ACQUISITION & DATA PROCESSING
4 PAGES INTERNAL MEMORY DATA
SCL 19
I 2 C BUS INTERFACE
SDA 20
DISPLAY & CONTROL INTERFACE
13 RED 14 GREEN 15 BLUE 8
VD D
V SS
Y
BLAN
COR ODD/ EVEN
ABSOLUTE MAXIMUM RATINGS
Symbol VDD Power Supply Range Parameter Value -0.3, +6.0 Unit V
INPUT VOLTAGE RANGE : VI VI VCS,SDA,SCL,D0-D7 TTD,F6,TCS/SCS,TT C -0.3, VDD + 0.5 -0.3, +10 V V
OUTPUT VOLTAGE RANGE : VO VO Tstg TA SAND,SDA,ODD/EVEN,R,G,B BLAN,COR, Y, TCS/SCS Storage Temperature Range Operating Ambient Temperature Range -0.3 , VDD -0.3 , VDD -20, +125 -20, +70 V V
o o
5342-02.TBL 5342-03.TBL
C C
ELECTRICAL CHARACTERISTICS VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol VDD IDD Supply Voltage (Pin 1) Supply Current (operating mode) Parameter Min 4.5 Typ 5 15 Max 5.5 40 Unit V mA
3/20
5342-02.EPS
1
21
18
17
16
STV5342
ELECTRICAL CHARACTERISTICS (continued) VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol INPUTS TTD (Pin 6) CEXT VI(p-p) tr , tf tDS tDH II(L) CI VI VI(p-p) VP fTTC fF6 tr , tf II(L) CI VIL VIH tr , tf II(L) CI VIL VIH fSCL tr , tf II(L) CI Ext. Coupling Capacitor Input Voltage p-p Input Rise / Fall Times Input Set-up Time Input Hold Time Input Leakage Current (VI = 0 to VDD) Input capacitance TTC, F6 (Pins 7,9) DC Input Voltage AC Input Voltage F6 AC Input Voltage TTC Input Peak Rel. 50 % Duty TTC Clock Frequency F6 Clock Frequency Clock Rise / Fall Times Input Leakage Current (VI = 0 to 10V) Input Capacitance VCS (Pin 10) Low Level Input Voltage High Level Input Voltage Input Rise / Fall Times Input Leakage Current (VI = 0 to VDD) Input Capacitance SCL (Pin 19) Low Level Input Voltage High Level Input Voltage SCL Clock Frequency Input Rise / Fall Times Input Leakage Current (VI = 0 to VDD) Input Capacitance -10 0 3 1.5 VDD 100 2 +10 7 V V kHz s A pF -10 0 2 0.8 VDD 500 +10 7 V V ns A pF 10 -10 - 0.3 1 1.5 0.2 6.9375 6 80 +10 10 +10 7 7 3.5 V V V V MHz MHz ns A pF 2 10 40 40 -10 +10 7 50 7 80 nF V ns ns ns A pF Parameter Min Typ Max Unit
INPUT/OUTPUTS TCS(output), SCS(input) (Pin12) VIL VIH tr , tf II(L) CI VOL VOH tr , tf CL Low Level Input Voltage High Level Input Voltage Input Rise / Fall Times Input Leakage Current (VI = 0 to VDD and output in high impedance state) Input Capacitance Low Level Output Voltage (IOL = 0.4mA) High Level Output Voltage (-IOH = 0.2mA) Output Rise / Fall Times between 0.6V and 2.2V Load Capacitance 0 2.4 -10 0 3 1.5 8 500 +10 7 0.4 VDD 100 50 V V ns A pF V ns pF
5342-04.TBL
V
4/20
STV5342
ELECTRICAL CHARACTERISTICS (continued) VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol INPUT/OUTPUTS (continued) SDA (Pin 20) VIL VIH tr , tf II(L) CI VOL tf CL VIL VIH II(L) CI VOL VOH tr , tf CL OUTPUTS ODD/EVEN **(Pin 8) VOL VOH tr , tf CL VOL VOI VOH tr1 tr2 tf CL VOL Low Level Output Voltage (IOL = 0.4mA) High Level Output Voltage (-I OH = 0.2mA) Output Rise / Fall Times between 0.6V and 2.2V Load Capacitance SAND (Pin 11) Low Level Output Voltage (IOL = 0.2mA) Middle Level Output Voltage (IOL = 10 A) High Level Output Voltage (-IOH = 0 to 10A) Output Rise Time : l VOL to VOI from 0.4 to 1.1V l VOI to VOH from 2.9 to 4.0V Output Fall Time V OH to VOl from 4.0 to 0.4V Load Capacitance R, G, B, COR, BLAN, Y (Pins 13-18) Low Level Output Voltage : l IOL = 2mA l IOL = 5mA Pull-up Voltage (with R = 1k to VDD) Output Fall Time from 4.5 to 1.5V (with R = 1k to VDD) Skew Delay on Falling Edges (at 3V with R = 1k connected to VDD) Load Capacitance Output Leakage Current (VPU = 0 to VDD output off) V 0 0 0.4 1 VDD 20 20 25 20 V ns ns pF A
5342-05.TBL
Parameter
Min
Typ
Max
Unit
Low Level Input Voltage High Level Input Voltage Input Rise / Fall Times Input Leakage Current (VI = 0 to VDD and output in high impedance state) Input Capacitance Low Level Output Voltage (IOL = 3mA) Output Fall Time between 3.0V and 1.0V Load Capacitance D0-D7 (Pins 22-29) Low Level Input Voltage High Level Input Voltage Input Leakage Current (VI = 0 to VDD and output in high impedance state) Input Capacitance Low Level Output Voltage (IOL = 1.6mA) High Level Output Voltage (-I OH = 0.2mA) Output Rise / Fall Times between 0.6V and 2.2V Load Capacitance
0 3 -10 0
1.5 VDD 2 +10 7 0.5 200 400
V V s A pF V ns pF V V A pF V V ns pF
0 2 -10 0 2.4
0.8 VDD +10 7 0.4 VDD 50 120
0 2.4
0.4 VDD 100 50
V V ns pF V V V ns
0 1.1 4 -
-
0.25 2.9 VDD
-
400 200 50 30 ns pF
VPU tf tSK CL ILO
5/20
STV5342
ELECTRICAL CHARACTERISTICS (continued) VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol TIMING SERIAL BUS (referred to VIH = 3V, VIL = 1.5V) (see Fig. 6) tLOW tHIGH tSU , DAT tHD , DAT tSU , sTO tBUF tHD , STA tSU , STA Low Period Clock High Period Clock Data Set-up Time Data Hold Time Stop Set-up Time from Clock High Start Set-up Time Following a Stop Start Hold Time Start Set-up Time Following Clock Low to High Transition 4 4 250 170 4 4 4 4 s s ns ns s s s
5342-06.TBL
Parameter
Min
Typ
Max
Unit
s
Figure 1 : F6, TTC, TTD Input Internal Connections
F6
9
character display clock input to timing chain
V TTC 7 teletext clock input to data acquistion circuit
50% duty cycle level VP VP
VI(p-p)
TTD C EXT
6
teletext data input to data acquisition circuit clamping pulses from timing circuit from time 4s to 8s of each television line to maintain correct D.C. level following external A.C. coupling F6, TTC, TTD INPUT CIRCUITRY 0 shaded regions equal in area t
INPUT WAVEFORM PARAMETERS
Figure 2 : Teletext Data Input Timing
t CY 144ns typ. TTC t DS t DH 90% 10% tr 80ns max. Data Stable
5342-04.EPS
90% 10% tf 80ns max.
40ns min. 40ns min. TTD Data Stable
data may change
data may change
data may change
Data Stable : 1 if 2V , 0 if 0.8V
6/20
5342-03.EPS
STV5342
Figure 3 : Synchronization Timing
F1 0 TCS 4.67 SAND 1.5 All timings in s 8.5 33.5 Phase lock Phase lock off
5342-05.EPS
continuous internal 1MHz clock 64
Figure 4 : Composite Sync. Waveforms
LSP 0 EP 0 2.33 BP 0 27.33 32 59.33 64 All timings in s 32 34.33 64 4.66 64
TCS (interlaced) 621 (308) TCS (interlaced) 309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 622 (309) 623 (310) 624 (311) 625 (312) 1 2 3 4 5 6
TCS (non-interlaced) 308 309 310 311 312 1 2 3 4 5 6
The timing reference is specified by the descending edge of the signal LSP, with a tolerance spread of 100ns.
7/20
5342-06.EPS
The number positions indicate the end of lines. The Teletext composite synchronization signal (TCS), whether interlacing is present or not, comprise three components. a) the line-synchronization pulses (LSP). b) the equalization pulses (EP) c) the frame-synchronization pulses (BP).
STV5342
Figure 5 : Display Output Timing
A) LINE RATE LSP (TCS) 0 4.66 40s R.G.B.Y (1) 0 16.67 display period 56.67 All timings in s 64
B) FIELD RATE
lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced) display period
R.G.B.Y (1) 0 41
(1) Also BLAN in charac ter and box bla nking
Horizontal directio n(line ) - Vertical direc tion (frame)
Figure 6 : Serial Bus Timing
SDA t BUF t LOW tf
SCL t HD,STA tr t HD,DAT t HIGH t SU,DAT
SDA
5342-08.EPS
t SU,STA
t SU,STO
VIH = 3V , VIL = 1.5V
8/20
5342-07.EPS
291 312 Line numbers
CVBS
SAA5231
DATA SLICER VIDEOTEXT CONTROLLER
17 F6
6
STV5342
27
Figure 7 : Master Synchronization Mode
Sync. Separator 6MHz 9
64
6MHz Oscillator
LINE SYNC
Teletext Data and Clock Separator Phase Detector 22 Video Composite
25 Sync.
15.625kHz 11 SAND
Signal Quality Detector
70A
VCS
10
Vertical Sync. Integrator
ENABLE ACQUISITION SYSTEM CLOCK ACQUISITION FIELD SYNC.
28 TCS/SCS
Scan Composite Sync. 12 TCS Outputs Buffer
TCS
Switch in this position TCS ON Pin 28 Voltage Sensor
Composite Sync. Generator
DISPLAY FIELD SYNC.
ENABLE
I 2 C-Register 1 TCS ON Mode (D2 = 1) (D1/D0)
1
1.2k
VS or
Sync. Output
STV5342
9/20
5342-09.EPS
10/20
L C
STV5342
CVBS
STV5342
20 18
27
VIDEOTEXT CONTROLLER
6MHz Oscillator 17 F6
6 64
Figure 8 : Slave Synchronization Mode
Sync. Separator 9
6MHz
LINE SYNC.
Videotext Data and Clock Separator
Phase Detector 22 15.625kHz 11 SAND
Signal Quality Detector
25
Video Composite Sync. 10 VCS Sync. Integrator Scan Composite Sync. 12 TCS Outputs Buffer TCS
TCS/SCS
ENABLE ACQUISITION INTERNAL CLOCK FIELD SYNC.
Determines F6 and line sync.
28
Composite Sync. Generator
SCS Field Sync.
DISPLAY FIELD SYNC.
SCS
I 2 C-Register 1 DISABLE TCS OFF EXT-SYNC (D2=0) (D1=D0=1)
DATA SLICER
1
SAA5231
Not connected for External synchronization
I2 C - Register 1, Bit D2=0 to disable TCS output buffer and D1=D0=1 to enable external sync. Acquisition only works when external sync. signal is phase synchronous with CBVS input.
5342-10.EPS
10k +12V 47F
1k 1k
10 820 68k 6MHz 8 10pF 1
TEA2014A
150pF
22H 15pF 2 3 10F +12V 10F
4.7F
23nF
15H
27pF
390
7
5 6
APPLICATION DIAGRAM
SYNC VIDEO +12V GND
+12V 23 +5V GND 3 2 V0
L7805
7 - 36
13.875MHz
470
12 V1 1
20
18
11
7
10
1
16 2.2F 2 2.7k
1k
SAA5231
27
15 28 22 17 14 25
21
19
3
4
5
6
8
9
24
26 13
BC558B 3.7k 47nF 47nF 15pF 1nF 470pF 22nF 270pF 100pF 220pF 68nF
+12V 10nF
10k 560pF 1N4148 8 16 18 17 13 7 10
BC548B 82 BLK BC548B 82 R 14 15 BC548B 82 G BC548B 82 B
10k
TS
470
6 12 11 9
SCL
19
470
SDA
20
+5V
STV5342
22H
1
0.1F
21
1k
1k
1k
22F
100
6.8k GND 1.2k 4.7k
STV5342
11/20
5342-11.EPS
STV5342
APPLICATION NOTES ORGANIZATION OF A PAGE-MEMORY The organization of a page-memory is shown in Figure 9. The STV5342 chip provides a display format of 25 rows of 40 characters per row. Row number twenty-four is used by the microprocessor for the display of information. Row zero contains the page header. The organization is as follows : The first seven characters (0 - 6) are used for messages regarding the operational status. The eighth character is an alphanumeric control character either "white" or "green" defining the PAGE MEMORY ORGANIZATION Figure 9
Fixed characters Alphanumerics white for normal, green on searc h
"search" status of the page. When it is "white" the operational state is normal and the header appears white ; when it is "green" the operational state corresponds to "search mode" and the header appears green. The following twenty-four characters give the header of the requested page when the system is in search mode. The last eight characters display the time of day. Row twenty-five comprises ten bytes of control data concerning the received page (see Table 1) and fourteen free bytes which can be used by the microprocessor.
7 Status Characters
24 characters from page header rolling on page search
8 scrolling time characters
ROW
7
1
24
8
0 1 2 3 4 5 6 7 8 9 10 11
MAIN PAGE DISPLAY AREA
12 13 14 15 16 17 18 19 20 21 22 23
this row always free for status 10 14
24 25
5342-12.EPS
10 bytes for received page information
14 bytes free for use by C
12/20
STV5342
8/30 READING 8/30 packet is read at row 23 equivalent address. R8 register must be programmed with D3, D2, D0 = 0 and D2 = 1 (8/30 selection). Table 1 : Row 25 received page control data format
D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0 D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0 D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0 D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0 D4 HAM HAM HAM HAM HAM HAM HAM HAM FOUND 0 D5 0 0 0 0 0 0 0 0 0 PBLF D6 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 COLUMN 0 1 2 3 4 5 6 7 8 9 Page number : - MAG = magazine, PU = page units, PT = page tens. Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens. PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits.
R9 register must be programmed with 23 (17h). R10 register value corresponds to the position of the byte to be read (from 0 to 39). R11A contents the value of the needed byte.
REGISTER MAP (see Table 2) Registers R0 to R10 are write only whilst R11A is a read/write and R11B is a read only register respect to the microprocessor. The automatic succession on a byte basis is indicated by the arrows in Table 2. In the normal operating mode TA, TB and TC should be set to logic level 0. After power-up the contents of the registers are as Table 2 : Register specification
D7 * TA D6 * 7 + P/ 8 BIT * D5 * ACQ. ON/OFF ACQ CCT A1 * * COR OUT COR OUT CONCEAL/ REVEAL * * C5 D5 (R/W) 0 D4 * 8/30 ENABLE ACQ. CCT A0 PRD4 * COR IN COR IN TOP/ BOTTOM * R4 C4 D4 (R/W) 0 D3 * DEW/ FULL FIELD TB D2 EVEN OFF TCS ON START COLUMN SC2 PRD2 * TEXT IN TEXT IN BOX ON 24 8/30 SELECT R2 C2 D2 (R/W) 0 D1 TC T1
follows : all bits in registers R0 to R11A are cleared to zero with the exception of bits D0 and D1 in registers R5 and R6 which are set to logical one. After power-up all the memory bytes are preset to hexadecimalvalue 20 H (space) with the exception of the byte corresponding to row 0 of column 7 of chapter 0 which is set to the value corresponding to "alpha white" hexadecimal value 07 H.
D0 SEL11B T0

R0 R1
Mode 0 Mode 1
*
START START COLUMN COLUMN SC0 SC1 PRD1 A1 PON OUT PON OUT BOX ON 1-23 A1 R1 C1 D1 (R/W) 0 PRD0 A0 PON IN PON IN BOX ON 0 A0 R0 C0 D0 (R/W) VCS signal quality
R2 R3 R4 R5 R6 R7 R8 R9 R10 R11A R11B
Page request adress Page request data Display chapter Display control (normal) Display control (newsflash / subtitle) Display mode Active chapter Active row Active column Active data Status
5342-09.TBL
* * BKGND OUT BKGND OUT STATUS ROW BTM/TOP * * * D7 (R/W) 60Hz
* * BKGND IN BKGND IN CURSOR ON * * * D6 (R/W) 0
PRD3 * TEXT OUT TEXT OUT SINGLE/ DOUBLE HEIGHT CLEAR MEM. R3 C3 D3 (R/W) 0
* Reserved register bits : must be set to 0
13/20
5342-08.TBL
STV5342
REGISTER FUNCTIONS
Register R0 Address 00H Function R11 adressing and pin functions control Bit(s) SEL 11B (D0) TC (D1) EVEN OFF (D2) T1 0 0 1 1 R1 Address 01H T0 0 1 0 1 Description Selection of register 11B (D0 = 1) or 11A (D0 = 0) Test bit, must be cleared in the normal working mode Control of ODD/EVEN pin : EVEN signal output (D2 = 0) or grounded (D2 = 1) 312/313 line MIX - mode with interlace 312/313 line TEXT - mode without interlace 312/312 line Terminal mode without interlace External synchronization TCS/SCS is an input D2 = 1, TCS output on Pin TCS/SCS D2 = 0, SCS input on Pin TCS/SCS Selection of field flyback mode or full channel mode (D3 = 1) Selection of 8/30 packet acquisition (D4 = 1) Control of acquisition operation (D5 = 0 enables acquisition)
TCS ON (D2) Operating mode controls DEW / FULLFIELD (D3) 8/30 ENABLE (D4) ACQUISITION ON / OFF (D5)
7 bits + parity or 8 Selection of received data format either 7 bits with parity bits without parity (D6) (D6 = 0) or 8 bits without parity (D6 = 1). TA (D7) R2 Address 02H R3 Address 03H R4 Address 04H R5 Address 05H Addressing information for a page request Data relative to the requested page (see Table 3) Selection of one of 4 pages to display SC0, SC1, SC2 (D0, D1, D2) TB (D3) A0 - D4 A1 - D5 PRD0 - PRD4 (D0 - D4) A0 - D0 A1 - D1 PON (D0, D1) Display control for normal operation TEXT (D2, D3) COR (D4, D5) BKGND (D6, D7) IN / OUT R6 Address 06H Display control for news-flash subtitle generation See R5 Test bit, must be cleared in the normal working mode Address the first column of the on chip page request RAM to be written. Test bit, must be cleared in the normal working mode. Selection of acquisition circuit (1 of 4) Written data in the page request RAM, starting with the columns addressed by SC0,SC1,SC2. Selection of page to be displayed
Picture on (IN: D0, OUT: D1) Text on (IN: D2, OUT: D3) Contrast reduction on (IN: D4, OUT: D5) Background colour on (IN: D6, OUT: D7) Enable inside/outside the box See R5
BOX ON 0, 1-23,24 (D0, D1, D2) R7 Address 07H TOP/BOTTOM Single/Double Height (D4/D3) Conceal/Reveal (D5) Cursor ON/OFF (D6) STATUS ROW BTM / TOP (D7) R8 Address 08H Active Chapter Address A0 (D0) A1 (D1) 8/30 SELECT(D2)
The "boxing" function is enabled on row 0,1-23 and 24 by D0, D1 and D2 set to one. X0 = Normal 01 = double height Rows 0 to 11 11 = double height Rows 12 to 23 Conceal Reveal Function Cursor position given by row/column value of R9/R10 The 25th row is displayed before the "Main text Area" (lines 0-23) or after (D7 = 0). Selection of chapter to be READ/WRITE To read 8/30 packet R8, D0 and D1 must be "0" and D2 = 1
5342-10.TBL
Display mode
14/20
STV5342
REGISTER FUNCTIONS
Register R9 to R11A Address 09H to 0BH* R11B Address 0BH* Function Bit(s) Description Active row address (R9), active column address (R10). 2 Data contained in R11A read (written) from (to) memory by microprocessor via I C. VCS Signal Quality (D0) 60Hz (D7) Good VCS quality signal detected (D0 = 1) or disturbed (D0 = 0) VCS received with 60Hz frequency (D7 = 1) or 50Hz (D7 = 0). Only valid when VCS is good (D0 = 1)
5342-11.TBL
Status
* Reading of R11A or R11B is determined by register 0, bit D0. Nevertheless, write operation is always performed on R11A register.
Table 3 : Register R3
START COLUMN 0 1 2 3 4 5 6 PRD4 Do care magazine Do care page tens Do care page units Do care hours tens Do care hours units Do care minutes tens Do care minutes units PRD3 HOLD PT3 PU3 X HU3 X MU3 PRD2 MAG2 PT2 PU2 X HU2 MT2 MU2 PRD1 MAG1 PT1 PU1 HT1 HU1 MT1 MU1 PRD0 MAG0 PT0 PU0 HT0 MT0 MU0
5342-12.TBL
HU0
The abbreviations have the same significance as in Table 1 with the exception of the "DO CARE" entries. It is only when this bit is "1" that the corresponding digit is taken into consideration on page request. For example, a page defined as "normal" or one defined as "timed" may be selected. If "HOLD" is low the page is held. The addressing of successive bytes via the I2C bus is automatic.
CHARACTER SETS The complete character set with 8-bit decoding is given in Table 4. Characters in columns 0 and 1 are normally displayed as blanks. Black dots represent the character shape whereas white dots represent the background. Each character can be identified by a pair of corresponding row and column integers : for example the character "3" may be indicated by 3/3. A rectangle may be represented as follows : The characters 8/6, 8/7, 9/5, 9/7 are used as special characters, always in conjunction with 8/5. The 13 national characters are placed in columns with bit 8 = 0.
15/20
* **
16/20
0 0 0 1 1 graphics black graphics red graphics green graphics yellow graphics blue graphics magenta graphics cyan graphics white conceal display continuous graphics separated graphics 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 or 1 0 0 or 1 0
0
STV5342
b8 b7
0
0
B I T S b4 b 3 b 2 b 1
b6 b5
0
column
r o w
2
0
0
0
0
0
alphanumerics
black
0
0
0
1
1
alphanumerics
red
0
0
1
0
2
alphanumerics
green
0
0
1
1
3
alphanumerics
Case using C12 C13 C14 = 001 (German Set)
** *
ESC black background new background
yellow
0
1
0
0
4
alphanumerics
blue
0
1
0
1
5
alphanumerics
magenta
0
1
1
0
6
alphanumerics
cyan
0
1
1
1
7
alphanumerics
**
white
Table 4 : Complete character set (with 8 bit codes) - West European Languages
5342-13.EPS
These control characters are reserved for compatibility with other data codes. These control characters are presumed before each row begins
** ** *
hold graphics
1
0
0
0
8
flash
**
1
0
0
1
9
steady
**
1
0
1
0
10
end box
1
0
1
1
11
start box
**
1
1
0
0
12
normal height
1
1
0
1
13
double
height
1
1
1
0
14
SO
*
release graphics
**
1
1
1
1
15
SI
STV5342
NATIONAL OPTION CHARACTER SETS The basic set of the 96 characters is shown in Table 5.The location of the 13 national characters Table 5 : Basic character set.
2/0 3/0 4/0
National Character
are shown in Table 5 whilst full national character sets are depicted in Table 6.
5/0
6/0
National Character
7/0
2/1
3/1
4/1
5/1
6/1
7/1
2/2
3/2
4/2
5/2
6/2
7/2
2/3
National Character
3/3
4/3
5/3
6/3
7/3
2/4
National Character
3/4
4/4
5/4
6/4
7/4
2/5
3/5
4/5
5/5
6/5
7/5
2/6
3/6
4/6
5/6
6/6
7/6
2/7
3/7
4/7
5/7
6/7
7/7
2/8
3/8
4/8
5/8
6/8
7/8
2/9
3/9
4/9
5/9
6/9
7/9
2/10
3/10
4/10
5/10
6/10
7/10
2/11
3/11
4/11
5/11
National Character
6/11
7/11
National Character
2/12
3/12
4/12
5/12
National Character
6/12
7/12
National Character
2/13
3/13
4/13
5/13
National Character
6/13
7/13
National Character
2/14
3/14
4/14
5/14
National Character
6/14
7/14
National Character
2/15
3/15
4/15
5/15
National Character
6/15
7/15
17/20
5342-14.EPS
STV5342
Table 6 : Character Set for STV5342 West European Languages
7/14 CHARACTER POSITION (COLUMN/ROW) C14 2/3 0 2/4 4/0 5/11 5/12 5/13 5/14 5/15 6/0 7/11 7/12 7/13
1
0
1
0
PHCB (1)
C13
0
0
1
1
0
C12
0
0
0
0
1
LANGUAGE
SWEDISH
ENGLISH
SPANISH
GERMAN
FRENCH
ITALIAN
1
0
1
Note 1 :
Where PHCB are the Page Header Control bits. Other Combinations de fault to English. Only the above ch aracters change with the PHCB. All others characters in the basic set are shown in Table 5.
18/20
5342-15.EPS
STV5342
Figure 10 : Character Format
Alphanumerics and Graphics 'space' character 2/0
Alphanumerics character 2/13
Alphanumerics or blast-thro ugh alphanumerics character 4/8
Alphanumerics character 7/15
Contiguous graphics character 7/6
Separated graphics character 7/6
Separated graphics character 7/15 Background Color
Contiguous graphics character 7/15 Display Color
5342-16.EPS
=
=
19/20
STV5342
PACKAGE MECHANICAL DATA 40 PINS - PLASTIC DIP
a1 I L
b1 b b2 e3 e E
D
40
21
F
1
20
Dimensions a1 b b1 b2 D E e e3 F i L
Min.
Millimeters Typ. 0.63 0.45 1.27
Max.
Min.
Inches Typ. 0.025 0.018 0.050
Max.
0.23
0.31 52.58 16.68 2.54 48.26 14.1 4.445 3.3
0.009
0.012 2.070 0.657 0.100 1.900 0.555 0.175 0.130
DIP40.TBL
15.2
0.598
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
20/20
PM-DIP40.EPS

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