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Preliminary Technical Data
FEATURES
2 pF off capacitance 1 pC charge injection 33 V supply range 120 on resistance Fully specified at +12 V, 15 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 14-lead TSSOP and 12-lead LFCSP Typical power consumption: <0.03 W
2 pF Off Capacitance, 1 pC Charge Injection, 15 V/12 V 4:1 iCMOSTM Multiplexer ADG1204
FUNCTIONAL BLOCK DIAGRAM
ADG1204
S1
S2
D S3 S4 1 OF 4 DECODER
04779-0-001
A0
A1
EN
APPLICATIONS
Automatic test equipment Data aquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Communication systems
Figure 1.
GENERAL DESCRIPTION
The ADG1204 is a CMOS analog multiplexer, comprising four single channels designed on an iCMOS process. iCMOS (industrial-CMOS) is a modular manufacturing process that combines high voltage CMOS (complementary metal-oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 30-V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages, while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth make the parts suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery powered instruments. The ADG1204 switches one of four inputs to a common output, D, as determined by the 3-bit binary address lines, A0, A1, and EN. Logic 0 on the EN pin disables the device. Each switch conducts equally well in both directions when on, and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action. Inherent in the design is low charge injection for minimum transients when switching the digital inputs.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. 6. 2 pF off capacitance (15 V supply). 1 pC charge injection. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V No VL logic power supply required. Ultralow power dissipation: <0.03 W. 14-lead TSSOP and 12-lead 3 mm x 3 mm LFCSP package.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADG1204 TABLE OF CONTENTS
Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 5 Absolute Maximum Ratings............................................................ 7 Truth Table .................................................................................... 7 ESD Caution.................................................................................. 7
Preliminary Technical Data
Pin Configurations and Function Descriptions ............................8 Terminology .......................................................................................9 Typical Performance Characteristics ........................................... 10 Test Circuits..................................................................................... 13 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
11/04--Revision PrD: Preliminary Version
Rev. PrD | Page 2 of 16
Preliminary Technical Data SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = -15 V, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINLor INH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 Transition Time, tTRANS tON (EN) tOFF (EN) Break-before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD IDD ISS 25C 85C Y Version1 VDD to VSS 180 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ A typ A max A typ A max A typ A max Test Conditions/Comments
ADG1204
120 5
160
VS = 10 V, IS = -10 mA; Figure 21 VS = 10 V, IS = -10 mA
25 50 0.01 0.5 0.01 0.5 0.04 1
VS = -5 V, 0 V, +5 V; IS = -10 mA VDD = +10 V, VSS = -10 V VS = 0 V/10 V, VD = 10 V/0 V; Figure 22 VS = 0 V/10 V, VD = 10 V/0 V; Figure 22 VS = VD = 0 V or 10 V; Figure 23
1 1 2
5 5 5 2.0 0.8
0.005 0.5 5 40 40 90 20 40 15 1 1 75 85 0.002 700 2 7 4 0.001 5.0 150 300 0.001 5.0
VIN = VINL or VINH
RL = 50 , CL = 35 pF VS = 10 V; Figure 24 RL = 50 , CL = 35 pF VS = 10 V; Figure 24 RL = 50 , CL = 35 pF VS = 10 V; Figure 24 RL = 50 , CL = 35 pF VS1 = VS2 = 10 V; Figure 25 VS = 0 V, RS = 0 , CL = 1 nF; Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 28 RL = 600 , 5 V rms, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; Figure 29
VDD = +16.5 V, VSS = -16.5 V Digital Inputs = 0 V or VDD Digital Inputs = 5 V Digital Inputs = 0 V or VDD
Rev. PrD | Page 3 of 16
ADG1204
Parameter IGND IGND 25C 0.001 150 300 85C Y Version1 5.0 Unit A typ A max A typ A max
Preliminary Technical Data
Test Conditions/Comments Digital Inputs = 0 V or VDD Digital Inputs = 5 V
1 2
Y Version temperature range is -40C to +125C. Guaranteed by design, not subject to production test.
VDD = +5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 tON tOFF Break-before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) 25C 85C Y Version1 VSS to VDD 220 10 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ pC max dB typ dB typ MHz typ pF typ pF typ pF typ Test Conditions/Comments
VS = 3.3 V, IS = -10 mA; Figure 21
30
VS = 3.3 V, IS = -10 mA VS = 3.3 V, IS = -10 mA VDD = 5.5 V, VSS = -5.5 V VD = 4.5 V, VS = 4.5 V; Figure 22 VD = 4.5 V, VS = 4.5 V; Figure 22 VD = VS = 4.5 V; Figure 23
0.01 0.5 0.01 0.5 0.04 1
1 1 2 2.0 0.8
5 5 5
0.005 0.5 5 160 60 50 1 20 56 60 20 15 100
VIN = VINL or VINH
RL = 300 , CL = 35 pF VS = 3 V; Figure 24 RL = 300 , CL = 35 pF VS = 3 V; Figure 24 RL = 300 , CL = 35 pF VS1 = VS2 = 3 V; Figure 25 VS = 0 V, RS = 0 , CL = 1 nF; Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 28 RL = 50 , CL = 5 pF; Figure 29 f = 1 MHz f = 1 MHz f = 1 MHz
Rev. PrD | Page 4 of 16
Preliminary Technical Data
Parameter POWER REQUIREMENTS IDD ISS 25C 0.001 5.0 0.001 5.0 85C Y Version1 Unit A typ A max A typ A max Test Conditions/Comments VDD = +5.5 V, VSS = -5.5 V Digital Inputs = 0 V or 5.5 V Digital Inputs = 0 V or 5.5 V
ADG1204
1 2
Y Version temperature range is -40C to +125C. Guaranteed by design, not subject to production test.
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 Transition Time, tTRANS tON (EN) tOFF (EN) Break-before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) 25C 85C Y Version1 0 V to VDD 220 1 12 0.01 0.5 0.01 0.5 0.04 1 Unit V typ max typ max typ nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ pF typ pF typ pF typ Test Conditions/Comments
VS = 10 V, IS = -10 mA; Figure 21 VS = 10 V, IS = -10 mA VS = 3 V, 6 V, 9 V; IS = -10 mA VDD = 12 V VS = 1 V/10 V, VD = 10 V/1 V; Figure 22 VS = 1 V/10 V, VD = 10 V/1 V; Figure 22 VS = VD = 1 V or 10 V; Figure 23
1 1 2
5 5 5 2.0 0.8
0.001 0.5 5 40 50 15 15 1 5 75 85 700 2 2 4
VIN = VINL or VINH
RL = 50 , CL = 35 pF VS = 10 V; Figure 24 RL = 50 , CL = 35 pF VS = 8 V; Figure 24 RL = 50 , CL = 35 pF VS = 8 V; Figure 24 RL = 50 , CL = 35 pF VS1 = VS2 = 8 V; Figure 25 VS = 0 V, RS = 0 , CL = 1 nF; Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 28 RL = 50 , CL = 5 pF; Figure 29
Rev. PrD | Page 5 of 16
ADG1204
Parameter POWER REQUIREMENTS IDD IDD 25C 0.001 5.0 150 300 85C Y Version1 Unit A typ A max A typ A max
Preliminary Technical Data
Test Conditions/Comments VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V
1 2
Y Version temperature range is -40C to +125C. Guaranteed by design, not subject to production test.
Rev. PrD | Page 6 of 16
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs Peak Current, S or D Continuous Current, S or D Operating Temperature Range Industrial (B Version) Automotive (Y Version) Storage Temperature Range Junction Temperature 14-Lead TSSOP, JA Thermal Impedance 12-Lead LFCSP, JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) Rating 38 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle max) 30 mA -40C to +85C -40C to +125C -65C to +150C 150C 150.4C/W 30.4C/W
ADG1204
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
TRUTH TABLE
Table 5.
EN 0 1 1 1 1 A1 X 0 0 1 1 A0 X 0 1 0 1 S1 Off On Off Off Off S2 Off Off On Off Off S3 Off Off Off On Off S4 Off Off Off Off On
215C 220C
1
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrD | Page 7 of 16
ADG1204 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
12 EN
A0 EN VSS S1 S2 D NC
1 2 3 4 5 6 7
14 A1 13 GND 12 VDD 11 S3 10 S4 9 8
ADG1204
TOP VIEW
VSS 1 S1 2 S2 3
04779-0-002
PIN 1 INDICATOR
11 A0
10 A1
9 GND 8 VDD 7 S3
04779-0-003
ADG1204
TOP VIEW (Not to Scale)
NC NC
NC = NO CONNECT
Figure 2. TSSOP Pin Configuration
Figure 3. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. TSSOP LFCSP 1 11 2 12 3 4 5 6 7-9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 Mnemonic A0 EN VSS S1 S2 D NC S4 S3 VDD GND A1 Function Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. Source Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Drain Terminal. Can be an input or an output. No Connection. Source Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input.
Rev. PrD | Page 8 of 16
NC 5
S4 6
D4
NC = NO CONNECT
Preliminary Technical Data TERMINOLOGY
IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminals D and S. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, which is measured with reference to ground. CD (Off) The off switch drain capacitance, which is measured with reference to ground.
ADG1204
CD, CS (On) The on switch capacitance, which is measured with reference to ground. CIN The digital input capacitance. tON (EN) The delay between applying the digital control input and the output switching on. See Figure 24, Test Circuit 4. tOFF (EN) The delay between applying the digital control input and the output switching off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. tTRANS The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another.
Rev. PrD | Page 9 of 16
ADG1204 TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
Figure 4. On Resistance as a Function of VD (VS) for Single Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
Figure 9. Leakage Currents as a Function of VD (VS)
Rev. PrD | Page 10 of 16
Preliminary Technical Data
ADG1204
Figure 10. Leakage Currents as a Function of VD (VS)
Figure 13. Leakage Currents as a Function of Temperature
Figure 11. Leakage Currents as a Function of VD (VS)
Figure 14. Supply Currents vs. Input Switching Frequency
Figure 12. Leakage Currents as a Function of Temperature
Figure 15. Charge Injection vs. Source Voltage
Rev. PrD | Page 11 of 16
ADG1204
Preliminary Technical Data
Figure 16. tON/tOFF Times vs. Temperature
Figure 19. On Response vs. Frequency
Figure 17. Off Isolation vs. Frequency
Figure 20. THD + N vs. Frequency
Figure 18. Crosstalk vs. Frequency
Rev. PrD | Page 12 of 16
Preliminary Technical Data TEST CIRCUITS
V
ADG1204
IS (OFF)
S D
04779-0-020
ID (OFF) S D A
04779-0-021
ID (ON)
NC
A
IDS
S
D
A VD
04779-0-022
04779-0-024 04779-0-025
VS
VS
VD
NC = No Connect
Figure 21. Test Circuit 1--On Resistance
Figure 22. Test Circuit 2--Off Leakage
Figure 23. Test Circuit 3--On Leakage
0.1F
VDD VSS
0.1F ADDRESS DRIVE (VIN) S1 S2 S3 S4 D VS1 3V 50% 0V 50%
VDD VSS A1 VS A0
VS4 VOUT RL 50 CL 35pF
VOUT
90% 90%
04779-0-023
+2.4V
EN GND
tTRANSITION tTRANSITION
Figure 24. Test Circuit 4--Address to Output Switching Times
0.1F
VDD VSS
0.1F 3V 0V
VDD VSS A1 VS 50 A0 S1 S2 S3 S4 D GND RL 50 CL 35pF VS1
ADDRESS DRIVE (VIN)
+2.4V
EN
VOUT
VOUT
80%
80%
tBBM
Figure 25. Test Circuit 5--Break-before-Make Time
0.1F
VDD VSS
0.1F ENABLE DRIVE (VIN) 3V 50% 0V 50%
VDD VSS A1 A0 S1 S2 S3 S4 D GND 50 RL 50 CL 35pF VS
V0 OUTPUT VOUT 0V
0.9V0
0.9V0
EN VS
tON(EN)
tOFF(EN)
Delay. Figure 26. Test Circuit 6--Enable to Output Switching Delay
Rev. PrD | Page 13 of 16
ADG1204
VDD VDD RS VS DECODER GND SW OFF S VSS VOUT VSS D CL 1nF VOUT VIN
Preliminary Technical Data
VOUT QINJ = CL x VOUT
SW OFF SW ON SW ON
SW OFF
A1 A2 EN
Figure 27. Test Circuit 7-- Charge Injection
VDD 0.1F
VSS 0.1F NETWORK ANALYZER
VDD 0.1F NETWORK ANALYZER VOUT RL 50
04779-0-026
VIN
SW OFF
VSS 0.1F
VDD S
VSS
VDD S1
VSS
50 D
50 VS VOUT
D S2 VS GND
04779-0-027
R 50
GND
RL 50
OFF ISOLATION = 20 LOG
VOUT VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
VOUT VS
Figure 28. Test Circuit 8--Off Isolation
Figure 30. Test Circuit 10--Channel-to-Channel Crosstalk
VDD 0.1F
VSS 0.1F
VDD
VDD S VSS NETWORK ANALYZER
VSS 0.1F AUDIO PRECISION
0.1F
50 VS D RL 50 VOUT
VDD S IN
VSS RS
D VIN
04779-0-028
VS V p-p RL 600 VOUT
04779-0-030
GND
INSERTION LOSS = 20 LOG
VOUT WITH SWITCH VOUT WITHOUT SWITCH
GND
Figure 29. Test Circuit 9--Bandwidth
Figure 31. Test Circuit 11--THD + Noise
Rev. PrD | Page 14 of 16
04779-0-029
Preliminary Technical Data OUTLINE DIMENSIONS
5.10 5.00 4.90
ADG1204
14
8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 8 0 0.75 0.60 0.45
SEATING COPLANARITY PLANE 0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 32. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimension shown in millimeters
3.00 BSC SQ
0.60 MAX
0.75 0.55 0.35
PIN 1 INDICATOR *1.45 1.30 SQ 1.15
0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
9 8 7
10 11 12
1 2 3
6
5
4
0.25 MIN 0.50 BSC
COPLANARITY 0.08
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 33. 12-Lead Lead Frame Chip Scale Package [VQ_LFCSP] 3 mm x 3 mm Body, Very Thin Quad (CP-12-1) Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model ADG1204YRU ADG1204YCP Temperature Range -40C to +125C -40C to +125C Package Description Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Package Option RU-14 CP-12-1
Rev. PrD | Page 15 of 16
ADG1204 NOTES
Preliminary Technical Data
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04779-0-11/04(PrD)
Rev. PrD | Page 16 of 16

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