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19-3119; Rev 0; 12/03
10V, 12-Bit, Serial, Voltage-Output DAC
General Description
The MAX5312 12-bit, serial-interface, digital-to-analog converter (DAC) provides bipolar 5V to 10V outputs from 12V to 15V power-supply voltages, or a unipolar 5V to 10V output from a single 12V to 15V powersupply voltage. The MAX5312 features excellent linearity with both integral nonlinearity (INL) and differential nonlinearity (DNL) guaranteed to 1 LSB (max). The device also features a fast 10s to 0.5 LSB settling time, and a hardwareshutdown feature that reduces current consumption to 3.5A. The output goes to midscale at power-up in bipolar mode (0V), and to zero scale at power-up in unipolar mode (0V). A clear input (CLR) asynchronously clears the DAC register and sets the output to 0V. The output can be asynchronously updated with the load DAC (LDAC) input. The device features a 10MHz SPITM-/QSPITM-/ MICROWIRETM-compatible serial interface that operates with 3V or 5V logic. Additional features include a serial-data output (DOUT) for daisy chaining and readback functions. The MAX5312 requires a 2V to 5.25V external reference voltage and is available in a 16-pin SSOP package that operates over the extended -40C to +85C temperature range.
Features
Unipolar or Bipolar Output-Voltage Ranges Unipolar: 0 to (+2 x VREF) (Single or Dual Supply) Bipolar: (-2 x VREF) to (+2 x VREF) (Dual Supply) Guaranteed INL 1 LSB (max) Guaranteed Monotonic: DNL 1 LSB (max) 10s Settling Time to 0.5 LSB Low 3.5A Shutdown Current 10MHz SPI-/QSPI-/MICROWIRE-Compatible Serial Interface Power-On Reset Sets DAC Output to 0V Schmitt Trigger Inputs for Direct Optocoupler Interface Serial-Data Output Allows Daisy Chaining of Devices Small 16-Pin SSOP
MAX5312
Ordering Information Applications
Motor Control Industrial Process Controls Industrial Automation Automatic Test Equipment (ATE) Analog I/O Boards Data-Acquisition Systems
PART MAX5312EAE TEMP RANGE -40C to +85C PIN-PACKAGE 16 SSOP
Pin Configuration
TOP VIEW
SCLK 1 DIN 2 CS 3 DOUT 4 DGND 5 VCC 6 SHDN 7 UNI/BIP 8 16 LDAC 15 CLR 14 VDD
MAX5312
13 REF 12 VSS 11 AGND 10 SGND 9 OUT
SSOP SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
ABSOLUTE MAXIMUM RATINGS
VDD to AGND..........................................................-0.3V to +17V VSS to AGND ..........................................................-17V to +0.3V VDD to VSS ..........................................................................+34V VCC to DGND ...........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V SGND to AGND .....................................................-0.3V to +0.3V SCLK, DIN, CS, SHDN, UNI/BIP, CLR, LDAC, DOUT to DGND ..........................-0.3V to (VCC + 0.3V) OUT to AGND ..................................(VSS - 0.3V) to (VDD + 0.3V) REF to AGND............................................................-0.3V to +6V Maximum Current into REF...............................................10mA Maximum Current into Any Pin Excluding REF.................50mA Continuous Power Dissipation (TA = +70C) 16-Pin SSOP (derate 7.1mW/C above +70C) ...........571mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (DUAL SUPPLY)
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 10%, AGND = DGND = SGND = 0V, VREF = 5V, RLOAD = 2k, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Zero-Scale Error Zero-Scale Temperature Coefficient Gain Error Gain-Error Temperature Coefficient ANALOG OUTPUT (OUT) Output Voltage Range Resistive Load to GND Capacitive Load to GND DC Output Resistance SGND INPUT (SGND) Input Impedance REFERENCE INPUT (REF) Reference-Voltage Input Range Input Resistance Reference Bandwidth RREF Code = 555hex, worst-case code Shutdown VREF = 200mVP-P + 5VDC 2.00 15 22 22 200 5.25 V k kHz 92 k RLOAD CLOAD 0.5 (VSS + 1.5V) < VOUT < (VDD - 1.5V) -2 x VREF 2 250 +2 x VREF V k pF N INL DNL Guaranteed monotonic Bipolar, code = 800hex Unipolar, code = 000hex Bipolar Unipolar Bipolar, no load Unipolar, no load Bipolar, no load Unipolar, no load 2 2 0.3 0.5 2 2 12 1 1 1 2 Bits LSB LSB LSB ppm FSR/C LSB ppm FSR/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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10V, 12-Bit, Serial, Voltage-Output DAC
ELECTRICAL CHARACTERISTICS (DUAL SUPPLY) (continued)
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 10%, AGND = DGND = SGND = 0V, VREF = 5V, RLOAD = 2k, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MIN 0.7 x VCC 2.4 0.6 0.8 10 10 1 A 1 V pF TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, SHDN, UNI/BIP, CLR, LDAC) Input-Voltage High VIH +2.7V VCC +3.6V +4.5V VCC +5.5V Input-Voltage Low Input Capacitance VIL C +2.7V VCC +3.6V +4.5V VCC +5.5V +2.7V VCC +3.6V +4.5V VCC +5.5V 0 all digital inputs VCC, +2.7V VCC +3.6V 0 all digital inputs VCC, +4.5V VCC +5.5V DIGITAL OUTPUT (DOUT) Output-Voltage High Output-Voltage Low Tri-State Leakage Current Tri-State Capacitance DYNAMIC PERFORMANCE Voltage-Output Slew Rate Output Settling Time Digital Feedthrough Output-Noise Spectral Density at 10kHz POWER SUPPLIES Positive Analog-Supply Voltage Negative Analog-Supply Voltage Positive Digital-Supply Voltage Positive Analog-Supply Current Negative Analog-Supply Current Digital-Supply Current Power-Supply Rejection Ratio (Note 2) Shutdown Current VDD VSS VCC IDD ISS ICC PSRR Output unloaded, VOUT = FS Output unloaded, VOUT = FS All digital inputs = 0 or VCC Positive analog supply Negative analog supply Positive analog supply Negative analog supply Digital supply 10.80 -10.80 2.7 1.8 0.75 30 0.4 0.6 1.7 2.4 3.5 50 50 10 A 15.75 -15.75 5.5 4 -2 200 V V V mA mA A LSB/V To 0.5 LSB of full scale, code 000 to code FFF CS = high, fSCLK = 10MHz, VOUT = 0V 2.5 10 10 130 V/s s nV-s nV/Hz VOH VOL ISOURCE = 2mA ISINK = 2mA 0.2 10 VCC 0.5 0.4 V V A pF V
MAX5312
Input Current (Note 1)
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3
10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
ELECTRICAL CHARACTERISTICS (SINGLE SUPPLY)
(VDD = +15V 5%, VSS = 0V, VCC = +5V 10%, AGND = DGND = SGND = 0V, VREF = 5V, RLOAD = 10k, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Unipolar Zero-Scale Error Unipolar Zero-Scale Temperature Coefficient Gain Error Gain-Error Temperature Coefficient ANALOG OUTPUT (OUT) Output Voltage Range Resistive Load to GND Capacitive Load to GND DC Output Resistance SGND INPUT (SGND) Input Impedance REFERENCE INPUT (REF) Reference-Voltage Input Range Input Resistance Reference Input Bandwidth Code = 555hex, worst-case code VREF = 200mVP-P + 5VDC 0.7 x VCC 2.4 0.6 0.8 10 10 1 1 VCC 0.5 0.4 0.2 V pF A 2.00 15 22 150 5.25 V k kHz 92 k RLOAD CLOAD 0.5 0 10 250 +2 x VREF V k pF N INL DNL (Note 3) Guaranteed monotonic Code = 14hex Code = 14hex No load No load 2 0.05 2 12 1 1 2 Bits LSB LSB LSB ppm FSR/C LSB ppm FSR/C SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SCLK, DIN, CS, SHDN, UNI/BIP, CLR, LDAC) Input-Voltage High VIH +2.7V VCC +3.6V +4.5V VCC +5.5V Input-Voltage Low Input Capacitance Input Current DIGITAL OUTPUT (DOUT) Output-Voltage High Output-Voltage Low Tri-State Leakage Current VOH VOL ISOURCE = 2mA ISINK = 2mA V V A VIL CIN IIN +2.7V VCC +3.6V +4.5V VCC +5.5V +2.7V VCC +3.6V +4.5V VCC +5.6V 0 VIN VCC, +2.7V VCC +3.6V 0 VIN VCC, +4.5V VCC +5.5V V
4
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10V, 12-Bit, Serial, Voltage-Output DAC
ELECTRICAL CHARACTERISTICS (SINGLE SUPPLY) (continued)
(VDD = +15V 5%, VSS = 0V, VCC = +5V 10%, AGND = DGND = SGND = 0V, VREF = 5V, RLOAD = 10k, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Tri-State Capacitance DYNAMIC PERFORMANCE Voltage-Output Slew Rate Output Settling Time Digital Feedthrough Output-Noise Spectral Density at 1kHz POWER SUPPLIES Positive Analog-Supply Voltage Negative Analog-Supply Voltage Positive Digital-Supply Voltage Positive Analog-Supply Current Negative Analog-Supply Current Digital-Supply Current Power-Supply Rejection Ratio Shutdown Current VDD VSS VCC IDD ISS ICC PSRR Output unloaded, VOUT = 0 Output unloaded, VOUT = 0 All digital inputs = 0 or VCC VDD = 14.5V to 15.5V, code FFF Analog supply Digital supply 2.7 1.8 0.75 30 0.04 1.7 3.5 50 10 10.80 0 5.5 4 -2 200 15.75 V V V mA mA A LSB/V A To 0.5 LSB of full scale, code 14hex to code FFF CS = high, fSCLK = 10MHz, VOUT = 0V 2.5 10 10 130 V/s s nV-s nV/Hz SYMBOL CONDITIONS MIN TYP 10 MAX UNITS pF
MAX5312
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5
10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
TIMING CHARACTERISTICS
(VDD = +15V, VSS = -15V or 0V, VCC = +2.7V to +5.5V, AGND = DGND = SGND = 0, VREF = 5V, RLOAD = 2k, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SCLK Frequency SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time LDAC Pulse Width CS Rise to LDAC Low Setup Time SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Low to DOUT Valid Time CS High to DOUT Disabled Time CS Rise to SCLK Rise Hold Time CS Pulse-Width High CLR Pulse-Width Low tCP tCH tCL tCSS tCSH tDS tDH tLD tLDS tDO1 tCS0 tCSE tCSD tCS1 tCSW tCLR +2.7V VCC +3.6V +4.5V VCC +5.5V 50 200 100 50 CLOAD = 20pF +2.7V VCC +3.6V +4.5V VCC +5.5V CLOAD = 20pF, +2.7V VCC +3.6V CLOAD = 20pF, +4.5V VCC +5.5V 10 120 120 +2.7V VCC +3.6V +4.5V VCC +5.5V For nondaisy-chain use For nondaisy-chain use 100 45 45 40 15 10 20 10 50 100 50 100 80 SYMBOL CONDITIONS MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Output unloaded, digital inputs = VCC or DGND. Note 2: VDD = +14.5V to +15.5V, VSS = -15.5V to -14.5V, code = FFF. Note 3: Measured from code 14hex to FFFhex.
6
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10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
Typical Operating Characteristics
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND = 0, VREF = +5.0V, output unloaded, TA = +25C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
INTERGRAL NONLINEARITY vs. INPUT CODE
MAX5312 toc01
INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE
MAX5312 toc02
DIFFERENTIAL NONLINEARITY vs. INPUT CODE
0.4 0.3 0.2 DNL (LSB)
MAX5312 toc03
0.5 0.4 0.3 0.2 INL (LSB)
0.50 0.45 0.40 INL (LSB) 0.35 0.30 0.25 0.20 0.15 0.10 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.5
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1024 2048 3072 4096 INPUT CODE (DECIMAL)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
5.5
0
1024
2048
3072
4096
VREF (V)
INPUT CODE (DECIMAL)
DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE
MAX5312 toc04
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX5312 toc05
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (WORST-CASE CODES)
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 CODE = 7FFhex CODE = 9FFhex
MAX5312 toc06
0.50 0.45 0.40 DNL (LSB)
1.0 0.8 0.6 0.4 INL (LSB)
1.0
0.35 0.30 0.25 0.20 0.15 0.10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VREF (V)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
UNIPOLAR SETTLING TIME (CLOAD = 250pF, RLOAD = 2k)
MAX5312 toc07
BIPOLAR SETTLING TIME (CLOAD = 250pF, RLOAD = 10k)
MAX5312 toc08
BIPOLAR MAJOR CARRY GLITCH ENERGY, CLOAD = 250pF
MAX5312 toc09
5V/div
CS
5V/div
CS
5V/div
CS
2V/div
VOUT
5V/div 0
VOUT
VOUT 100mV/div
0 t = 10.0s/div t = 4.00s/div
t = 10.0s/div
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7
10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND = 0, VREF = +5.0V, output unloaded, TA = +25C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
BIPOLAR MAJOR CARRY GLITCH CLOAD = 10pF
MAX5312 toc10
UNIPOLAR ZERO-SCALE VOLTAGE vs. TEMPERATURE
MAX5312 toc11
BIPOLAR MIDSCALE VOLTAGE vs. TEMPERATURE
CODE = 800hex
MAX5312 toc12
5V/div
CS
50 49 48 VOUT (mV)
CODE = 014hex
2.5
2.0
VOUT 100mV/div
46 45 44 43
VOUT (mV) -40 85
47
1.5
1.0
0.5
t = 4.00s/div
42 -15 10 35 60 TEMPERATURE (C)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
UNIPOLAR FULL-SCALE VOLTAGE vs. TEMPERATURE
MAX5312 toc13
BIPOLAR POSITIVE FULL-SCALE VOLTAGE vs. TEMPERATURE
MAX5312 toc14
BIPOLAR NEGATIVE FULL-SCALE VOLTAGE vs. TEMPERATURE
CODE = 000hex -9.993 -9.994 VOUT (mV) -9.995 -9.996 -9.997 -9.998
MAX5312 toc15
10.000 9.999 9.998 VOUT (mV) 9.997 9.996 9.995 9.994
CODE = FFFhex
9.998 9.997 9.996 VOUT (mV) 9.995 9.994 9.993 9.992
-9.992
CODE = FFFhex
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
UNIPOLAR SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5312 toc16
BIPOLAR POSITIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE
VSS = -15V 3.5 3.0 IDD (mA) 2.5 2.0 1.5 1.0 0.5
MAX5312 toc17
4.0 3.5 3.0 IDD (mA) 2.5 2.0 1.5 1.0 0.5
VSS = 0V
4.0
0 10.70
11.72
12.74
13.76
14.78
15.80
0 10.70
11.72
12.74
13.76
14.78
15.80
VDD (V)
VDD (V)
8
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10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND = 0, VREF = +5.0V, output unloaded, TA = +25C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
BIPOLAR NEGATIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5312 toc18
UNIPOLAR SUPPLY CURRENT vs. TEMPERATURE
VSS = 0V 2.5 2.0 IDD (mA) 1.5 1.0 IDD (mA) 2.0
MAX5312 toc19
BIPOLAR POSITIVE SUPPLY CURRENT vs. TEMPERATURE
MAX5312 toc20A
0 -0.5 -1.0 ISS (mA) -1.5 -2.0 -2.5 -3.0 -3.5
VDD = 15V
3.0
2.2
2.1
1.9
0.5 0 -14.78 -13.76 -12.74 -11.72 -10.70 -40 -15 10 35 60 85 VSS (V) TEMPERATURE (C)
1.8
-4.0 -15.80
1.7 -40 -15 10 35 60 85 TEMPERATURE (C)
BIPOLAR NEGATIVE SUPPLY CURRENT vs. TEMPERATURE
MAX5312 toc20B
UNIPOLAR SHUTDOWN CURRENT vs. TEMPERATURE
MAX5312 toc21
BIPOLAR SHUTDOWN CURRENT vs. TEMPERATURE
3 SHUTDOWN CURRENT (A) 2 1 0 -1 -2 -3 85 -4 -40 -15 10 35 60 85 TEMPERATURE (C) ISS IDD ICC
MAX5312 toc22
-0.45 -0.50 -0.55 -0.60 ISS (mA) -0.65 -0.70 -0.75 -0.80 -0.85 -0.90 -0.95 -40 -15 10 35 60
5 4 SHUTDOWN CURRENT (A) ICC 3 2 1 0 -1 ISS
4
IDD
85
-40
-15
10
35
60
TEMPERATURE (C)
TEMPERATURE (C)
UNIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT
MAX5312 toc23A
UNIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT
CODE = 014hex 0.125 0.115 0.105 VOUT (V) 0.095 0.085 0.075 0.065 0.055 0.045
MAX5312 toc23B
10.005 CODE = FFFhex 10.000 9.995 9.990 VOUT (V) 9.985 9.980 9.975 9.970 9.965 9.960 0 4 8 12 16
0.135
20
0
0.2
0.4
0.6 IOUT (mA)
0.8
1.0
1.2
IOUT (mA)
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9
10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND = 0, VREF = +5.0V, output unloaded, TA = +25C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
BIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT
MAX5312 toc24A
BIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT
CODE = FFFhex 10.000 9.995 9.990 VOUT (V) 9.985 9.980 9.975 9.970 9.965 9.960 0.01 0 4 8 12 16 20 0
MAX5312 toc24B
UNIPOLAR REF INPUT RESISTANCE vs. INPUT CODE
MAX5312 toc25
-9.965 CODE = 000hex -9.970 -9.975 VOUT (V) -9.980 -9.985 -9.990 -9.995 -10.000 -10.005 -20 -16 -12 -8 -4 0 IOUT (mA)
10.005
1
REF INPUT RESISTANCE (M)
0.1
1024
2048
3072
4096
IOUT (mA)
INPUT CODE (DECIMAL)
BIPOLAR REF INPUT RESISTANCE vs. INPUT CODE
MAX5312 toc26
UNIPOLAR REFERENCE INPUT BANDWIDTH
MAX5312 toc27
BIPOLAR REFERENCE INPUT BANDWIDTH
REF = 0.2VP-P + 5.0VDC 3 0 RESPONSE (dB) -3 -6 -9 -12 -15
MAX5312 toc28
100
6 REF = 0.2VP-P + 5.0VDC 3 0 RESPONSE (dB) -3 -6 -9 -12
6
REF INPUT RESISTANCE (M)
10
1
0.1
0.01 0 1024 2048 3072 4096 INPUT CODE (DECIMAL)
-15 0.01 0.1 1 10 100 1000 FREQUENCY (kHz)
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
UNIPOLAR STARTUP RESPONSE, CLOAD = 10pF
MAX5312 toc29A
UNIPOLAR STARTUP RESPONSE, CLOAD = 250pF
MAX5312 toc29B
20V/div
VDD
20V/div
VDD
VCC 5V/div 5V/div VREF 5V/div VOUT 2V/div 1V/div 5V/div
VCC
VREF
VOUT
t = 10.0s/div
t = 10.0s/div
10
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10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND = 0, VREF = +5.0V, output unloaded, TA = +25C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
BIPOLAR STARTUP RESPONSE, CLOAD = 10pF
MAX5312 toc30A
BIPOLAR STARTUP RESPONSE, CLOAD = 250pF
MAX5312 toc30B
20V/div
VDD
20V/div
VDD
5V/div 10V/div
VCC
5V/div 10V/div
VCC
VSS
VSS
2V/div
VOUT
1V/div
VOUT
t = 10.0s/div
t = 10.0s/div
UNIPOLAR RELEASE FROM HARDWARE-SHUTDOWN RESPONSE
MAX5312 toc31
BIPOLAR RELEASE FROM HARDWARE-SHUTDOWN RESPONSE
MAX5312 toc32
VOUT VOUT 5V/div 5V/div
VSHDN
VSHDN
2V/div
2V/div
t = 100s/div
t = 100s/div
UNIPOLAR SOFTWARE-SHUTDOWN RESPONSE
MAX5312 toc33A
BIPOLAR SOFTWARE-SHUTDOWN RESPONSE
MAX5312 toc33B
CS 5V/div 5V/div
CS
VOUT 5V/div 10V/div
VOUT
t = 40.0s/div
t = 40.0s/div
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11
10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
Pin Description
PIN 1 2 3 4 5 6 7 NAME SCLK DIN CS DOUT DGND VCC SHDN FUNCTION Serial-Clock Input. Data is shifted from DIN into the internal register on the rising edge of SCLK. Data is clocked out at DOUT on the falling edge of SCLK. SCLK is active only while CS is low. Serial-Data Input. DIN is the data input port for the serial interface. Clock data in on the rising edge of SCLK. Active-Low Chip-Select Input. CS activates the serial interface. Drive CS low to initiate serial communication. Serial-Data Output. DOUT is the data output port for the serial interface. Data shifted into DIN appears at DOUT 16.5 clock cycles later, valid on the falling edge of SCLK. DOUT is high impedance when CS is high. Digital Ground Digital Power Input. VCC ranges from +2.7V to +5.5V. Bypass VCC with a 0.1F and 1.0F capacitor to Active-Low Shutdown Input. SHDN places the device into low-power shutdown mode. When shut down REF and DOUT are high impedance, drive SHDN low to place the device into shutdown mode. Unipolar/Bipolar-Select Input. UNI/BIP selects unipolar or bipolar output. In unipolar mode, the analog output range is 0 to (+2 x VREF). In bipolar mode, the analog output range is (-2 x VREF) to (+2 x VREF). Drive UNI/BIP high for unipolar output. Drive UNI/BIP low for bipolar output. Dual supplies are required for bipolar operation. Analog Output. OUT is the output port for the DAC. Read OUT relative to SGND. Signal Ground. SGND is the ground-reference node for the output amplifier's internal feedback resistors. Connect SGND directly to AGND. (See Figure 1.) Analog Ground. AGND is the ground return for VDD and VSS. Negative Power Input. Bypass VSS with a 0.1F and 1.0F capacitor to AGND. If operating with a single supply, connect VSS to AGND. External Reference Input. Apply an external reference voltage of +2V to +5.25V to REF to determine the output voltage range. In unipolar mode, the output range is from 0 to (+2 x VREF). In bipolar mode, the output range is from (-2 x VREF) to (+2 x VREF). Positive Power Input. Bypass VDD with a 0.1F and 1.0F capacitor to AGND. Active-Low Clear Input. CLR clears input and DAC registers and resets the DAC output to 0V. Drive CLR low to assert the clear condition. Active-Low Load Input. Use LDAC to update the DAC register. LDAC is an asynchronous control input. Drive low to force an update.
8
UNI/BIP
9 10 11 12
OUT SGND AGND VSS
13 14 15 16
REF VDD CLR LDAC
12
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10V, 12-Bit, Serial, Voltage-Output DAC
Detailed Description
The MAX5312 12-bit DAC operates from either single or dual supplies. Dual 12V to 15V power supplies provide a bipolar 5V to 10V output, or a unipolar 0 to 10V output. Single 12V to 15V power supplies provide only a unipolar 0 to 10V output. The reference input accepts voltages from 2V to 5.25V. The DAC features INL and DNL less than 1 LSB (max), a fast 10s settling time, and a hardware-shutdown mode that reduces current consumption to 3.5A (max). The device features a 10MHz SPI-/QSPI-/MICROWIRE-compatible serial interface that operates with 3V or 5V logic, an asynchronous load input, and a serial-data output. The device offers a CLR that sets the DAC output to 0V. Figure 1 shows the functional diagram of the MAX5312.
Serial Interface
An SPI-/QSPI-/MICROWIRE-compatible serial interface allows complete control of the DAC through a 16-bit control word. The first 4 bits form the control bits that determine register loading and software-shutdown functions. The last 12 bits form the DAC data. The 16bit word is entered MSB first. Table 1 shows the serial-data format. Table 2 shows the interface commands. The MAX5312 can be programmed while in shutdown. The serial interface contains three registers: a 16-bit shift register, a 12-bit input register, and a 12-bit DAC register (Figure 1). The shift register accepts data from the serial interface. The input register acts as a holding register for data going to the DAC register and isolates the shift register from the DAC register. The DAC register controls the DAC ladder and thus the output voltage. Any update in the DAC register updates the output voltage.
MAX5312
2R VCC
2R VDD SW2
REF 12-BIT DAC
A1 SW1 A2 SW3 DAC REGISTER OUT
12 LDAC
2R
CLR
12 INPUT REGISTER
2R SGND
12 16-BIT SHIFT REGISTER DIN SCLK CS UNI/BIP SHDN DGND VSS SERIAL INTERFACE AND CONTROL DOUT
MAX5312
AGND
Figure 1. Functional Diagram
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13
10V, 12-Bit, Serial, Voltage-Output DAC
Data in the shift register is transferred to the input register during the appropriate software command only. Data in the input register is transferred to the DAC register in one of two ways: using the software command, or through external logic control using the asynchronous load input (LDAC). Table 2 shows the software commands that transfer the data from the shift register to the input and/or DAC registers. The CLR, an external logic control, asynchronously forces the input and DAC registers to zero code, and the output to 0V, in both unipolar and bipolar modes. The interface timing is shown in Figures 2 and 3. Wait a minimum of 100ns after CS goes high before implementing LDAC or CLR. If either of these logic inputs activates during a data transfer, the incoming data is corrupted and needs to be reloaded. For software control only, connect LDAC and CLR high.
MAX5312
DAC Architecture
The MAX5312 uses an inverted DAC ladder architecture to convert the digital input into an analog output voltage. The digital input controls weighted-switches that connect the DAC ladder nodes to either REF or GND (Figure 4). The sum of the weights produces the analog equivalent of the digital-input word and is then buffered at the output.
Table 1. Serial-Data Format
CONTROL BITS MSB C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DATA BITS LSB D0
Table 2. Serial-Interface Programming Commands
CONTROL BITS* C3 0 0 0 0 1 1 C2 0 0 1 1 0 1 C1 0 1 0 1 0 0 C0 0 0 0 0 0 0 INPUT DATA D11-D0 XXXXXXXXXXXX No operation; command is ignored. 12-bit DAC data 12-bit DAC data Load input register from shift register; DAC output unchanged. Load input and DAC registers from shift register; DAC output updated. FUNCTION
XXXXXXXXXXXX Load DAC register from input register; DAC output updated; input register unchanged. XXXXXXXXXXXX Enter shutdown; input and DAC registers unchanged. XXXXXXXXXXXX Exit shutdown; input and DAC registers unchanged.
X = Don't care. *All unlisted commands are reserved commands. Do not use.
CS
COMMAND EXECUTED
SCLK 1 DIN C3 C2 C1 C0 D11 D10 D9 8 D8 D7 9 D6 D5 D4 D3 D2 D1 16 D0 (1)
Figure 2. Serial-Interface Signals
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10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
tCSW CS tCS0 SCLK tCH tDS DIN tCSE DOUT tLDS tLD LDAC MSB tDO1 tDH LSB tCSD tCL tCSS tCP tCSH tCS1
Figure 3. Serial-Interface Timing Diagram
2R
2R
R
R
R
MAX5312
SW2 2R 2R 2R 2R 2R SW1 OUT D0 1 REF AGND 2R SGND DAC REGISTER 0 1 D1 0 1 D10 0 1 D11 0 SW3 2R
UNI/BIP
CONTROL LOGIC
Figure 4. Basic Inverted DAC Ladder ______________________________________________________________________________________ 15
10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
External Reference and Transfer Functions
Connect an external 2V to 5.25V reference to REF (the MAX6350 is recommended). Set the output voltage range with the reference and the input code by using the equations below. Unipolar Output Voltage: VOUT _ UNI = LSBUNI x CODE where LSBUNI = Bipolar Output Voltage: VOUT _ BIP = (LSBBIP x CODE) - (2 x VREF ) where LSBBIP = 4 x VREF 212 2 x VREF 212
Output Amplifiers
The output-amplifier section can be configured as either unipolar or bipolar by the UNI/BIP logic input. With UNI/BIP forced low, SW1 and SW2 in Figure 4 are closed, and SW3 is open. This configuration channels the DAC output through two output stages to generate the 2 x VREF output swing. The first amplifier generates the VREF voltage range and the second amplifier increases it by two. When configured for bipolar operation, the MAX5312 must be driven with dual 12V to 15V power supplies. With UNI/BIP forced high, switches SW1 and SW2 are open, and SW3 is closed. This configuration channels the DAC output through only a single gain stage to generate a 0 to (2 x VREF) output swing. Daisy Chaining SPI-/QSPI-/MICROWIRE-compatible devices can be daisy chained to reduce I/O lines from the host controller (Figure 7). Daisy chain devices by connecting the DOUT of one device to the DIN of the next, and connect the SCLK of all devices to a common clock. Data is shifted out of DOUT 16.5 clock cycles after it is shifted into DIN, and is available on the rising edge of the 17th clock cycle. The SPI-/QSPI-/MICROWIRE-compatible serial interface normally works at up to 10MHz, but must be slowed to 6.0MHz if daisy chaining. DOUT is high impedance when CS is high.
where VOUT_UNI is the unipolar output voltage, VOUT_BIP is the bipolar output voltage, LSBUNI is the unipolar LSB step size, LSBBIP is the bipolar LSB step size, VREF is the reference voltage, and CODE is the decimal equivalent of the binary, 12-bit, DAC input code. In either case, a 000hex input code produces the minimum output (-2 x VREF for bipolar and 0 for unipolar), an 800hex input code produces the midscale output (0 for bipolar and VREF for unipolar), and a FFFhex input code produces the full-scale output (2 x VREF for bipolar and unipolar).
Shutdown
Shutdown is controlled by software commands or by the SHDN logic input. The SHDN logic input can be implemented at any time. The SPI-/QSPI-/MICROWIRE-compatible serial interface remains fully functional, and the device is programmable while shut down. When shut down, the MAX5312 supply current reduces to 3.5A, DOUT is high impedance, and OUT is pulled to SGND through the internal feedback resistors of the output amplifier (Figure 1). When coming out of shutdown, or during device powerup, allow 350s for the output to stabilize.
Table 3. Output Voltage as Input Code Examples
BINARY DAC CODE MSB LSB UNIPOLAR (UNI/BIP_ = HIGH) +2 x VREF (4095 / 4096) +2 x VREF (2049 / 4096) +2 x VREF (2048 / 4096) = VREF +2 x VREF (2047 / 4096) +2 x VREF (1 / 4096) 0 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 ANALOG OUTPUT BIPOLAR (UNI/BIP_ = LOW) +2 x VREF (2047 / 2048) +2 x VREF (1 / 2048) 0 -2 x VREF (1 / 2048) -2 x VREF (2047 / 2048) -2 x VREF (2048 / 2048) = -2 x VREF
16
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10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
1 LSB = 4095 4094 4093 4092
2 x VREF 4096 +2047 +2046 +2045 +2044
1 LSB =
4 x VREF 4096
ANALOG OUTPUT VOLTAGE (LSB)
2049 2048 2047
ANALOG OUTPUT VOLTAGE (LSB)
+1 0 -1
2 x VREF
3 2 1 0 000 001 002 003 7FF 800 801 FFC FFD FFE FFF hex DIGITAL INPUT CODE (LSB)
-2045 -2046 -2047 -2048 000 001 002 003 7FF 800 801 hex DIGITAL INPUT CODE (LSB) FFC FFD FFE FFF
Figure 5. Unipolar Transfer Function
Figure 6. Bipolar Transfer Function
Applications Information
Power Supplies
A single +12V to +15V supply is required to realize a 0 to 10V output swing. A dual 12V to 15V supply is required to realize a 10V output swing, and allows unipolar, 0 to +10V output if UNI/BIP is forced high. A +3V to +5V digital power supply and a +2.000V to +5.250V external reference voltage are also required. Always bring up the reference voltage last. The other power supplies do not require sequencing.
Power-Supply Bypassing and Ground Management
Bypass VDD and VSS with 0.1F and 1.0F capacitors to AGND, and bypass VCC with 0.1F and 1.0F capacitors to DGND. Minimize trace lengths to reduce inductance. Digital and AC transient signals on AGND or DGND can create noise at the output. Connect AGND and DGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a lowinductance ground plane or star connect all groundreturn paths back to AGND. Carefully lay out the traces between channels to reduce AC crosscoupling and crosstalk. Wire-wrapped boards, sockets, and breadboards are not recommended.
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4 x VREF
17
10V, 12-Bit, Serial, Voltage-Output DAC MAX5312
SCLK CS CS CS CS TO OTHER SERIAL DEVICES
MAX5312
SCLK SCLK
MAX5312
SCLK
MAX5312
DIN
DIN
DOUT
DIN
DOUT
DIN
DOUT
Figure 7. Daisy Chaining Devices
Chip Information
TRANSISTOR COUNT: 3280 TECHNOLOGY: BiCMOS
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10V, 12-Bit, Serial, Voltage-Output DAC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX5312
2
1
INCHES DIM A A1 B C E H D E e H L MIN 0.068 0.002 0.010 MAX 0.078 0.008 0.015
MILLIMETERS MIN 1.73 0.05 0.25 MAX 1.99 0.21 0.38 D D D D D INCHES MIN 0.239 0.239 0.278 0.317 0.397 MAX 0.249 0.249 0.289 0.328 0.407 MILLIMETERS MIN 6.07 6.07 7.07 8.07 10.07 MAX 6.33 6.33 7.33 8.33 10.33 N 14L 16L 20L 24L 28L
0.20 0.09 0.004 0.008 SEE VARIATIONS 0.205 0.301 0.025 0 0.212 0.311 0.037 8 5.20 7.65 0.63 0 5.38 7.90 0.95 8 0.0256 BSC 0.65 BSC
N
A C e D B A1 L
NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL DOCUMENT CONTROL NO. REV.
21-0056
C
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SSOP.EPS

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