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Oct 1999
U C T ME N T R OD E TE P EPLAC r at E SOL DED R nte m/tsc OB C e co M EN port il. COM ical Sup w.inters E NO R Techn or ww our ERSIL T 88-IN 1-8
(R)
CA3059, CA3079
Zero-Voltage Switches for 50Hz-60Hz and 400Hz Thyristor Control Applications
Description
The CA3059 and CA3079 zero-voltage switches are monolithic silicon integrated circuits designed to control a thyristor in a variety of AC power switching applications for AC input voltages of 24V, 120V, 208/230V, and 277V at 50Hz-60Hz and 400Hz. Each of the zero-voltage switches incorporates 4 functional blocks (see the Functional Block Diagram) as follows: 1. Limiter-Power Supply - Permits operation directly from an AC line. 2. Differential On/Off Sensing Amplifier - Tests the condition of external sensors or command signals. Hysteresis or proportional-control capability may easily be implemented in this section. 3. Zero-Crossing Detector - Synchronizes the output pulses of the circuit at the time when the AC cycle is at zero voltage point; thereby eliminating radio-frequency interference (RFI) when used with resistive loads. 4. Triac Gating Circuit - Provides high-current pulses to the gate of the power controlling thyristor. In addition, the CA3059 provides the following important auxiliary functions (see the Functional Block Diagram). 1. A built-in protection circuit that may be actuated to remove drive from the triac if the sensor opens or shorts. 10 2. Thyristor firing may be inhibited through the action of an internal diode gate connected to Terminal 1. 3. High-power dc comparator operation is provided by overriding the action of the zero-crossing detector. This is accomplished by connecting Terminal 12 to Terminal 7. Gate current to the thyristor is continuous when Terminal 13 is positive with respect to Terminal 9. The CA3059 and CA3079 are supplied in 14 lead dual-inline plastic packages.
Features
* Relay Control * Valve Control * Synchronous Switching of Flashing Lights * On-Off Motor Switching * Differential Comparator with Self-Contained Power Supply for Industrial Applications * Photosensitive Control * Power One-Shot Control * Heater Control * Lamp Control
Type Features
* 24V, 120V, 208/230V, 277V at 50/60 . . . or 400Hz Operation * Differential Input . . . . . . . . . . . . . . . . . . * Low Balance Input Current (Max) - A. . . * Built-In Protection Circuit for . . . . . . . . Opened or Shorted Sensor (Term 14) * DC Mode (Term 12) . . . . . . . . . . . . . . . . * External Trigger (Term 6) . . . . . . . . . . . * External Inhibit (Term 1) . . . . . . . . . . . . * DC Supply Volts (Max) . . . . . . . . . . . . . * Operating Temperature Range (oC) . . .
CA3059 CA3079
X X 1 X
X X 2 X
* Sensor Range (Rx) - k. . . . . . . . . . . . . 2 - 100 2 - 50 X X X 14 -55 to +125
Ordering Information
PART NUMBER CA3059 CA3079 TEMPERATURE -55oC
o
PACKAGE 14 Lead Plastic DIP 14 Lead Plastic DIP
to
+125oC
o
-55 C to +125 C
Pinouts
CA3059 (PDIP) TOP VIEW
INHIBIT 1 DC SUPPLY 2 HIGH CURRENT 3 NEG. TRIGGER TRIGGER OUT 4 AC IN 5 TRIGGER IN 6 COMMON 7 14 FAIL-SAFE 13 SENSE AMP IN 12 ZCD OVERRIDE 11 R DRIVER (COM) 10 R DRIVER V+ DO NOT USE 1 DC SUPPLY 2 HIGH CURRENT 3 NEG. TRIGGER TRIGGER OUT 4 AC IN 5 DO NOT USE 6 COMMON 7
CA3079 (PDIP) TOP VIEW
14 DO NOT USE 13 SENSE AMP IN 12 DO NOT USE 11 R DRIVER (COM) 10 R DRIVER V+ 9 SENSE AMP REF 8 COMMON
9 SENSE AMP REF 8 COMMON
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
FN490.5
3
CA3059, CA3079 Functional Block Diagram
12 IC RS 5 LIMITER "0" CROSSING DET. POWER SUPPLY CURRENT BOOST 3 RL
IC AC INPUT VOLTAGE 2 1 RP 14
EXTERNAL INHIBIT
MT2
PROTECTION CIRCUIT
TRIAC GATING CIRCUIT INHIBIT ON/OFF SENSING AMPL.
4
G
MT1
100F 15V
+ -
13 RX 8 7
* NTC SENSOR * NEGATIVE TEMPERATURE COEFFICIENT
9
10
11
6 IC
AC INPUT VOLTAGE (50/60 OR 400Hz) V AC 24 120 208/230 277
INPUT SERIES RESISTOR (RS) k 2 10 20 25
DISSIPATION RATING FOR RS W 0.5 2 4 5
NOTE: Circuitry within shaded areas, not included in CA3079 See chart IC = Internal connection - DO NOT USE (Terminal restriction applies only to CA3079)
FOR DC MODE OR 400Hz OPERATION RP
IC RS AC LINE INPUT R1 5K
12
5 D7 D2
CF 100F 15V COMMON
RSENSOR
2
13
COMMON
D13 D3 D6
R2 27K D8 D9
R7 10K Q6 Q2
R3 12K 10 Q3 Q4 Q5 8 TO COMMON R5 9.6K 9 11
R4 10K
D1
D4
D5
Q1 R10 40K
R8 15 3 R6 15K R9 25 FOR INCREASED GATE DRIVE
D12 Q10 D15 D10 D11
Q7
Q8 Q9 4 TO THYRISTOR GATE
FAIL-SAFE INPUT
14 IC
All resistance values are in NOTE: Circuitry within shaded areas not included in CA3079
7 TO COMMON
1 IC INHIBIT INPUT
6 IC FOR EXTERNAL TRIGGER
IC = Internal connection - DO NOT USE (Terminal restriction applies only to FIGURE 1. SCHEMATIC DIAGRAM OF CA3059 AND CA3079
4
Specifications CA3059, CA3079
Absolute Maximum Ratings TA = +25oC
DC Supply Voltage (Between Terminals 2 & 7) CA3059 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V CA3079 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V DC Supply Voltage (Between Terminals 2 & 8) CA3059 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V CA3079 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V Peak Supply Current (Terminals 5 & 7) . . . . . . . . . . . . . . . . . . .50mA Output Pulse Current (Terminal 4) . . . . . . . . . . . . . . . . . . . . . 150mA
Thermal Information
Thermal Resistance JA PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100oC/W Power Dissipation Up to TA = +55oC CA3059, CA3079 . . . . . . . . . . . . . . . . . 950mW Above TA = +55oC CA3059, CA3079 . . Derate Linearly 10mW/oC Ambient Temperature Operating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At distance 1/16" 1/32" (1.59 0.79) from case for 10 seconds max
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETERS
TA = +25oC, For all Types, Unless Otherwise Specified. All voltages are measured with respect to Terminal 7. For Operating at 120VRMS, 50-60Hz (AC Line Voltage) (Note 1) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
DC SUPPLY VOLTAGE (Figure 2A, 2B, 2C) Inhibit Mode At 50/60Hz At 400Hz At 50/60Hz Pulse Mode At 50/60Hz At 400Hz At 50/60Hz Gate Trigger Current (Figures 3, 4A) IGT Terminal 4 VS VS RS = 8k, IL = 0 RS = 10k, IL = 0 RS = 5k, IL = 0 RS = 8k, IL = 0 RS = 10k, IL = 0 RS = 5k, IL = 0 Terminals 3 and 2 Connected, VGT = 1V Terminal 3 open, Gate Trigger Voltage (VGT) = 0 Terminals 3 and 2 Connected, Gate Trigger Voltage (VGT) = 0 With External Power Supply Figure 5a, 5b, 5c IOM Terminal 4 Terminal 3 open, V+ = 12V, VGT = 0 Terminals 3 and 2 Connected, V+ = 12V, VGT = 0 Voltage Ratio of Terminals 9 to 2 CEXT = 0 CEXT = 0, REXT = tN CEXT = 0 CEXT = 0, REXT = tP1 tN1 I4 II VCMR Terminals 9 and 13 Connected CEXT = 0, REXT = 0.465 70 70 6.1 6 6.5 6.8 6.4 6.4 6.7 6.3 105 7 7 V V V V V V mA
PEAK OUTPUT CURRENT (PULSED) (Figures 4, 5) With Internal Power Supply Figure 4a, 4b IOM Terminal 4 50 90 84 124 170 240 0.485 100 12 100 10 0.520 140 140 mA mA mA mA s s s s s s A nA nA V
Inhibit Input Ratio (Figure 6) For Positive dv/dt 50-60Hz 400Hz For Negative dv/dt 50-60Hz 400Hz
V 9/V2 tP
TOTAL GATE PULSE DURATION (Note 2) (Figure 7A, 7B, 7C, 7D)
PULSE DURATION AFTER ZERO CROSSING (50-60Hz) (Figure 7A) For Positive dv/dt For Negative dv/dt OUTPUT LEAKAGE CURRENT (Figure 8) Inhibit Mode INPUT BIAS CURRENT (Figure 9) CA3059 CA3079 Common-mode Input Voltage Range 220 220 1.5 to 5 1000 2000 0.001 10 50 60 -
5
Specifications CA3059, CA3079
Electrical Specifications
PARAMETERS SENSITIVITY (Note 3) (Figures 4(a), 11) Pulse Mode NOTES: 1. The values given in the Electrical Characteristics Chart at 120V also apply for operation at input voltages of 208/230V, and 277V, except for Pulse Duration. However, the series resistor (R S) must have the indicated value, shown in the chart in the Functional Block Diagram, for the specified input voltage. 2. Pulse Duration in 50Hz applications is approximately 15% longer than shown in Figure 7(b). 3. Required voltage change at Terminal 13 to either turn OFF the triac when ON or turn ON the triac when OFF. V13 Terminal 12 open 6 mV TA = +25oC, For all Types, Unless Otherwise Specified. All voltages are measured with respect to Terminal 7. For Operating at 120VRMS, 50-60Hz (AC Line Voltage) (Note 1) (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Maximum Voltage Ratings TA = +25oC
MAXIMUM VOLTAGE RATINGS TA = +25oC TERM. NOTE 3 NO. 1 1 Note 3 2
NOTE 1 NOTE 3 NOTE 3 NOTES 2, 3
MAXIMUM CURRENT RATINGS IIN mA 10 150 IOUT mA 0.1 10
2
3
4
5
6 15 0 0 -14
7 10 -2
8
9
10
11
12
13
14
Note 4 Note 4 Note 4 Note 4 0 -15 0 -15 0 -15 2 -14
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 0 -14 0 -14 0 -14 Note 4 0 -14 0 -14
0 0 Note 5 Note 5 -14 -14
3 4 5 Note 1 6 Note 3 7 8 9 10 11 12 Note 3 13 14 Note 3
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 2 -10 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 7 -7 14 0 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 0.1 50 150 10
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 14 0 10 0 Note 4 20 0 2.5 -2.5 14 0 6 -6 Note 4 Note 4 0.1 2
Note 4 Note 4 Note 4 Note 4 Note 4
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note4 Note 4 Note 4 Note 4 Note 4 Note4 Note 4 Note 4 50 50
Note 4 Note 4 Note4 2 2
This chart gives the range of voltages which can be applied to the terminals listed horizontally with respect to the terminals listed vertically. For example, the voltage range of horizontal Terminal 6 to vertical Terminal 4 is 2V to -10V. NOTES: 1. Resistance should be inserted between Terminal 5 and external supply or line voltage for limiting current into Terminal 5 to less than 50mA. 2. Resistance should be inserted between Terminal 14 and external supply for limiting current into Terminal 14 to less than 2mA. 3. For the CA3079 indicated terminal is internally connected and, therefore, should not be used. 4. Voltages are not normally applied between these terminals; however, voltages appearing between these terminals are safe, if the specified voltage limits between all other terminals are not exceeded. 5. For CA3079 (0V to -10V).
6
CA3059, CA3079
PULSE 0.3K INHIBIT 4.6K RS 5 AC LINE 7 IL 8 ALL RESISTANCE VALUES ARE IN 4 9 10 EXTERNAL LOAD CURRENT 5.75 -75 -50 -25 0 25 50 75
o
4.6K 13 2
120VRMS, 50/60Hz OPERATION INPUT RESISTANCE (RS) = 10k NO EXTERNAL LOAD INTERNAL DC SUPPLY (V) 7.00 INHIBIT MODE 6.75 6.50 6.25 6.00 PULSE MODE
RL CA3059 CA3079 11 100F VS
100
125
AMBIENT TEMPERATURE ( C)
FIGURE 2A. DC SUPPLY VOLTAGE TEST CIRCUIT FOR CA3059 AND CA3079
120VRMS, 50/60Hz OPERATION TA = +25 oC RS = 5k (INHIBIT MODE)
FIGURE 2B. DC SUPPLY VOLTAGE vs AMBIENT TEMPERATURE FOR CA3059 AND CA3079
120VRMS, 50/60Hz OPERATION TA = +25o C
GATE TRIGGER CURRENT (mA)
6.5 INTERNAL DC SUPPLY (V) 6.0 5.5 5.0 4.5 4.0 3.5 RS = 10k (PULSE MODE) 0 1 2 3
130 120 110 100 90 80 70 60 50 40
TERMINALS 2 AND 3 CONNECTED
RS = 10k (INHIBIT MODE)
RS = 5k (PULSE MODE)
TERMINAL 3 OPEN 0 1 2 GATE TRIGGER (V) 3
4
5
6
7
8
EXTERNAL LOAD CURRENT (mA)
FIGURE 2C. DC SUPPLY VOLTAGE vs EXTERNAL LOAD CURRENT FOR CA3059 AND CA3079
FIGURE 3. GATE TRIGGER CURRENT vs GATE TRIGGER VOLTAGE FOR CA3059 AND CA3079
PEAK OUTPUT CURRENT, PULSED (mA)
9 RS 10K 5 AC LINE 7
10
11
120VRMS, 50/60Hz OPERATION GATE TRIGGER, VGT = 0 (V) 175 150 125 100 75 50 -75 -50 -25 0 25 50 75 100
o
CA3059 CA3079 IOM (4) OR IGT(4)
4 1 1%
OSCILLOSCOPE WITH HIGH GAIN INPUT
TERMINALS 2 AND 3 CONNECTED
8
13
2
3 VGT
TERMINAL 3 OPEN 125
AMBIENT TEMPERATURE ( C) 6K 5K 100F
FIGURE 4A. PEAK OUTPUT (PULSED) AND GATE TRIGGER CURRENT WITH INTERNAL POWER SUPPLY TEST CIRCUIT FOR CA3059 AND CA3079
FIGURE 4B. PEAK OUTPUT CURRENT (PULSED) vs AMBIENT TEMPERATURE FOR CA3059 AND CA3079
7
CA3059, CA3079
V+ PEAK OUTPUT, PULSED (mA) 100F 3 RS 10K 5 120VRMS 60Hz 7 10 9 8 5 VGT CA3059 11 IOM(4) 2 5K 6K 300 250 200 150 100 50 0 0 5 10 15 20 EXTERNAL POWER SUPPLY, V+ (V) ALL RESISTANCE VALUES ARE IN 120VRMS, 50/60Hz OPERATION GATE TRIGGER, VGT = 0 (V) TERMINALS 2 AND 3 CONNECTED TERMINAL 3 OPEN
13 4 1 1% OSCILLOSCOPE WITH HIGH GAIN INPUT
FIGURE 5A. PEAK OUTPUT CURRENT (PULSED) WITH EXTERNAL POWER SUPPLY TEST CIRCUIT FOR CA3059
FIGURE 5B. PEAK OUTPUT CURRENT (PULSED) vs EXTERNAL POWER SUPPLY VOLTAGE FOR CA3059
9 RS 10K 250 5 120VRMS 60Hz 7 EXTERNAL SUPPLY V+ = 13V 200 8 R1
10
11
6
CA3059 CA3079
4
13
14 R2
2
PEAK OUTPUT, PULSED (mA)
12V 10V 150 13V 12V 8V
ALL RESISTANCE VALUES IN
100F
FIGURE 6(A). INPUT INHIBIT VOLTAGE RATIO TEST CIRCUIT FOR CA3059 AND CA3079
10V 100 INPUT INHIBIT VOLTAGE RATIO, V9/V2 8V 5V 5V 50 3V 3V 120VRMS, 50/60Hz OPERATION GATE TRIGGER VOLTS (VGT) = 0 TERMINALS 2 AND 3 CONNECTED TERMINAL 3 OPEN -50 -20 10 40 70 100 130 120VRMS, 50/60Hz OPERATION 0.60 0.55 0.50 0.45 0.40 0.35 0.30
0
-50
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (o C)
AMBIENT TEMPERATURE (oC)
FIGURE 5C. PEAK OUTPUT CURRENT (PULSED) vs AMBIENT TEMPERATURE FOR CA3059
FIGURE 6B. INPUT INHIBIT VOLTAGE RATIO vs AMBIENT TEMPERATURE FOR CA3059 AND CA3079
8
CA3059, CA3079
AC LINE + dv/dt tP1 tP RS 10K 120VRMS 60Hz C(EXT) 7 - dv/dt tN1 tN 10 5 CA3059 CA3079 11 4 1M OSC. WITH HIGH GAIN INPUT TOTAL GATE PULSE DURATION (s) GATE PULSE 0V 120VRMS, 50/60Hz OPERATION TA = +25o C tP (POSITIVE dv/dt) 200 tN (NEGATIVE dv/dt) 100
300
9
0 12 REXT 8 6K 13 5K 100F 2 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 EXTERNAL CAPACITANCE (F)
NOTE: Circuitry within shaded area not included in CA3079. All resistance values are in FIGURE 7A. GATE PULSE DURATION TEST CIRCUIT WITH ASSOCIATED WAVEFORM FOR CA3059 AND CA3079
700 600 PULSE DURATION AFTER ZERO CROSSING (s) 500 400 300 200 100 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 EXTERNAL CAPACITANCE (F) tP1 (POSITIVE dv/dt) 120VRMS, 50/60Hz OPERATION TA = +25oC tN1 (NEGATIVE dv/dt)
FIGURE 7B. TOTAL GATE PULSE DURATION vs EXTERNAL CAPACITANCE FOR CA3059 AND CA3079
40 TOTAL GATE PULSE DURATION (s) 120VRMS, 50/60Hz OPERATION TA = +25oC 30
20
tP (POSITIVE dv/dt)
10 tN (NEGATIVE dv/dt) 0 10 EXTERNAL RESISTANCE (k) 100
FIGURE 7C. PULSE DURATION AFTER ZERO CROSSING vs EXTERNAL CAPACITANCE FOR CA3059 & CA3079
100 120VRMS, 50/60Hz OPERATION INPUT RESISTANCE (RS = 100k NO EXTERNAL LOAD 10
FIGURE 7D. TOTAL GATE PULSE DURATION vs EXTERNAL RESISTANCE FOR CA3059
V+ = 6V
OUTPUT LEAKAGE (nA)
2
1
CA3059 CA3079 +3V 9 8 7 13
0.1 -80 -60 -40 -20
0
20
40
60
80 100 120 140
II
AMBIENT TEMPERATURE (oC)
FIGURE 8. OUTPUT LEAKAGE CURRENT (INHIBIT MODE) vs AMBIENT TEMPERATURE FOR CA3059 AND CA3079
FIGURE 9. INPUT BIAS CURRENT TEST CIRCUIT FOR CA3059 AND CA3079
9
CA3059, CA3079
TOTAL GATE PULSE DURATION (s) 220VRMS, 50/60Hz OPERATION INPUT RESISTANCE (RS) = 10k 60Hz, tP (+ dv/dt) TOTAL GATE PULSE DURATION (s) 600 220VRMS, 50/60Hz OPERATION INPUT RESISTANCE (RS) = 20k 60Hz, tP (+ dv/dt)
300
50Hz, tP (+ dv/dt)
200
50Hz, tP (+ dv/dt)
400
100 50Hz, tN (- dv/dt) 0 0 0.02 0.04 0.06 0.08 0.1 EXTERNAL CAPACITANCE (F) 60Hz, tN (- dv/dt)
200 50Hz, tN (- dv/dt) 0 0 0.02 0.04 0.06 0.08 0.1 EXTERNAL CAPACITANCE (F) 60Hz, tN (- dv/dt)
FIGURE 10A.
FIGURE 10B.
600 TIME FROM ZERO CROSSING TO END OF PULSE (s)
TIME FROM ZERO CROSSING TO END OF PULSE (s)
220VRMS, 50/60Hz OPERATION INPUT RESISTANCE (RS) = 10k 60Hz, tN1 (- dv/dt)
50Hz, tN1 (- dv/dt)
600
220VRMS, 50/60Hz OPERATION INPUT RESISTANCE (RS) = 20k 60Hz, tN1 (- dv/dt)
400
400
50Hz, tN1 (- dv/dt) 50Hz, tP1 (+ dv/dt)
200 50Hz, tP1 (+ dv/dt) 0 0 0.02 0.04 0.06
60Hz, tP1 (+ dv/dt)
200
60Hz, tP1 (+ dv/dt)
0.08
0.1
0 0 0.02 0.04 0.06 0.08 0.1 EXTERNAL CAPACITANCE (F)
EXTERNAL CAPACITANCE (F)
FIGURE 10C.
FIGURE 10D.
FIGURE 10. RELATIVE PULSE WIDTH AND LOCATION OF ZERO CROSSING FOR 220V OPERATION FOR CA3059 AND CA3079
SENSOR RESISTANCE, RON - ROFF ()
SENSOR RESISTANCE = 5k 30 18 SENSITIVITY, V13 (mV)
7 6 5 4 3 2 1 0 0 -50 -25 0 25 50 75
THYRISTOR TURN-OFF AREA OF UNCERTAIN OPERATION
20
TERMINALS 7 AND 12 CONNECTED DC GATE CURRENT MODE (CA3058 & CA3059)
12
TERMINAL 14 (V)
AREA OF NORMAL OPERATION
10 TERMINAL 12 OPEN PULSED GATE CURRENT MODE (ALL TYPES) 0 -75 -50 -25 0 25 50 75 (oC) 100 125
6
AREA OF UNCERTAIN OPERATION THYRISTOR TURN-OFF
AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (oC)
FIGURE 11. SENSITIVITY vs AMBIENT TEMPERATURE FOR CA3059 AND CA3079
FIGURE 12. OPERATING REGIONS FOR BUILT-IN PROTECTION CIRCUIT FOR CA3059
10
CA3059, CA3079
10K 2W 120VAC 60Hz 100F 15VDC 5 ON + R1 OFF C1 2 14 13 6 7 3 9 10 11 12 CA3059 G 4 MT1 100F 15VDC 6 1 OFF RL MT2 120VAC 60Hz + R1 C1 ON 5 2 14 9 8 7 13 10 11 12 G CA3059 CA3079 4 MT1 10K 2W 6 1 3 RL MT2
tON = 0.67 R1C1 R1(max. value allowable) = 1m FIGURE 13. LINE-OPERATED ONE-SHOT TIMER
td = 0.67 R1C1 FIGURE 14. LINE-OPERATED THYRISTOR CONTROL TIME DELAY TURN-ON CIRCUIT
ON OFF C1
10K 2W R2 2 5
R1 6 1
RL MT2
120VAC 60Hz
100F 15VDC
+ -
RP
14 13 CA3059
G 4
MT1
td = RT C1 RT = R 1R2 R 1 + R2
NTC SENSOR
6 7 3 9 10 11 12
FIGURE 15. ON/OFF TEMPERATURE CONTROL CIRCUIT WITH DELAYED TURN-ON
12 10 5 120VAC 5K 2W 11 CA3059 RECTIFIER AND TRIAC CONTROL 1 6 9 100F 10K + 2 10 K R6 2M RESET 11 OUTPUT SENSOR 16 R7 5K IN 10 9 6 7 8 R5 1K 1 13 7 13 4 8
SWITCHED LOAD MT2 1K G T2300B MAX LOAD = 2.5A MT1
R2 68K 5 12 11
R3 100K
R1
VDD+
NOTE: Terminal 1 goes "High" (Logic "1") after 2048 pulses are applied to Terminal 10. For 8 hour delay: R1 = 12M C1 = 2F
1
COS/MOS CD4040A 12-STAGE COUNTER
PULSE GENERATOR CA3097E THYRISTOR/ TRANSISTOR ARRAY 3 15 8 10 16
2 4 14 C1
R4 10K
FIGURE 16A. LINE-OPERATED IC TIMER FOR LONG TIME PERIODS
11
CA3059, CA3079
"DAY" SENSOR ILLUMINATION COUNTER RESET (TERMINAL 11 OF CD4040) "CLOCK" PULSES (TERMINAL 9 OF CA3097E) COUNTER OUTPUT (TERMINAL 1 OF CD4040) TERMINAL 6 OF CA3059 AND TERMINAL 5 OF CA3097E TERMINAL 4 OF CA3059 AND POWER IN LOAD "NIGHT"
e.g., 8 HRS
1 PULSE/SEC
FIGURE 16B. TIMING DIAGRAM FOR FIGURE 16A
C1 100F 2 10 120VAC 60Hz 10K 2W 5 RESET SW1 RUN 1K 9 CA3059 TRIAC CONTROL 11 13 14 120pps T2302B MAX LOAD = 2.5A 4 200 6 1 8 7 4 1K ASTABLE SW2 120pps 11 C2 0.001 10 8 16 COS/MOS CD4020A 14-STAGE BINARY COUNTER 211 212 213 214 H G F E D C PROGRAMMING INTERCONNECTIONS B A VSS 8 EXP Kb 7 Kc 9 15 +VDD ( +6.5V) 16 2 10 Ka RESET +VDD ( +6.5V) 10K G TRIAC RL
RECTIFIER PULSE GENERATOR
MONOSTABLE
2 7 2 8 29 210
VDD Kd
a
b
c
d
e
f
g
h
CD4048A EXPANDABLE 8 INPUT GATE
1 OUTPUT
FIGURE 17A. PROGRAMMABLE ULTRA-ACCURATE LINE-OPERATED TIMER.
12
CA3059, CA3079
TIME PERIODS (t = 0.5333 s) 1t a A C NC C NC C NC C NC C NC C NC C NC C C NC C C NOTES: 1. tO = Total time delay = n1 t + n2 t + . . . nnt. 2. C = Connect. For example, interconnect terminal a of the CD4020A and terminal A of the CD4048A. 3. NC = No Connection. For example, terminal b of the CD4020A open and terminal B of the CD4048A connected to +VDD bus. 2t b B NC C C NC NC C C NC NC C C NC NC C C C NC NC C 4t c C NC NC NC C C C C NC NC NC NC C C C C C NC NC C 8t d D NC NC NC NC NC NC NC C C C C C C C C C NC NC C 16t e E NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC C C C 32t f F NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC C C C C 64t g G NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC C C C C 128t h H NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC C 1t 2t 3t 4t 5t 6t 7t 8t 9t 10t 11t 12t 13t 14t 15t 111t 112t 113t 255t tO CD4020A TERMINALS CD4048A TERMINALS
AC SUPPLY VOLTAGE
CA3059 OUTPUT (PIN 4 AND PIN 6)
CD4048A OUTPUT
AC IN LOAD (R L )
FIGURE 17B. "PROGRAMMING" TABLE FOR FIGURE 17(A).
13
CA3059, CA3079 Operating Considerations
Power Supply Considerations for CA3059 and CA3079 The CA3059 and CA3079 are intended for operation as selfpowered circuits with the power supplied from and AC line through a dropping resistor. The internal supply is designed to allow for some current to be drawn by the auxiliary power circuits. Typical power supply characteristics are given in Figures 2(b) and 2(c). Power Supply Considerations for CA3059 The output current available from the internal supply may not be adequate for higher power applications. In such applications an external power supply with a higher voltage should be used with a resulting increase in the output level. (See Figure 4 for the peak output current characteristics.) When an external power supply is used, Terminal 5 should be connected to Terminal 7 and the synchronizing voltage applied to Terminal 12 as illustrated in Figure 5(a). Operation of Built-In Protection for the CA3059 A special feature of the CA3059 is the inclusion of a protection circuit which, when connected, removes power from the load if the sensor either shorts or opens. The protection circuit is activated by connecting Terminal 14 to Terminal 13 as shown in the Functional Block Diagram. To assure proper operation of the protection circuit the following conditions should be observed: 1. Use the internal supply and limit the external load current to 2mA with a 5k dropping resistor. 2. Set the value of RP and sensor resistance (R X) between 2k and 100k. 3. The ratio of RX to RP, typically, should be greater than 0.33 and less than 3. If either of these ratios is not met with an unmodified sensor over the entire anticipated temperature range, then either a series or shunt resistor must be added to avoid undesired activation of the circuit. If operation of the protection circuit is desired under conditions other than those specified above, then apply the data given in Figure 12. External Inhibit Function for the CA3059 A priority inhibit command may be applied to Terminal 1. The presence of at least +1.2V at 10A will remove drive from the thyristor. This required level is compatible with DTL or T2L logic. A logical 1 activates the inhibit function. DC Gate Current Mode for the CA3059 Connecting Terminals 7 and 12 disables the zero-crossing detector and permits the flow of gate current on demand from the differential sensing amplifier. This mode of operation is useful when comparator operation is desired or when inductive loads are switched. Care must be exercised to avoid overloading the internal power supply when operating in this mode. A sensitive gate thyristor should be used with a resistor placed between Terminal 4 and the gate in order to limit the gate current.
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid gradations are in mils (10-3 inch).
The photographs and dimensions represent a chip when it is par of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90o with respect to the face of the chip. Therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14

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