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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
D
D D
D D D D D D D
Single Power Supply 3.3 V 0.3 V - TMS29LF040 2.7 V to 3.6 V - TMS29VF040 5 V 10% - See TMS29F040 Data sheet (Literature Number SMJS820) Organization . . . 524288 By 8 Bits Eight Equal Sectors of 64K Bytes - Any Combination of Sectors Can Be Erased - Any Combination of Sectors Can Be Marked as Read-Only Compatible With JEDEC Electrically Erasable Programmable Read-Only Memory (EEPROM) Command Set Fully Automated On-Chip Erase and Byte-Program Operations 100 000 Program / Erase Cycles Erase-Suspend/ Erase-Resume Operation Compatible With JEDEC Byte-Wide Pinouts Low-Current Consumption - Active Read . . . 20 mA Typical - Active Program / Erase . . . 30 mA Typical All Inputs/Outputs CMOS-Compatible Only
FM PACKAGE ( TOP VIEW )
A12 A15 A16 A18 VCC W A17
4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
5 6 7 8 9 10 11 12 13
A14 A13 A8 A9 A11 G A10 E DQ7
PIN NOMENCLATURE A[0:18] DQ[0:7] E G VCC VSS W Address Inputs Inputs (programming) / Outputs Chip Enable Output Enable Power Supply Ground Write Enable
description
The TMS29LF040 and TMS29VF040 are 524 288 by 8-bit (4 194 304-bit), low-voltage, single-supply, programmable read-only memories that can be erased electrically and reprogrammed. These devices are organized as eight independent 64K-byte sectors and are offered with access times between 80 ns and 150 ns. An on-chip state machine controls the program and erase operations. The embedded-byte program and sector/ chip-erase functions are fully automatic. The command set is compatible with that of JEDEC 4M-bit EEPROMs. A suspend / resume feature allows access to unaltered memory sectors during a sector-erase operation. Data protection of any sector combination is accomplished using a hardware sector-protection feature. Device operations are selected by writing JEDEC-standard commands into the command register using standard microprocessor-write timings. The command register acts as input to an internal state machine that interprets the commands, controls the erase and programming operations, and outputs the status of the device, the data stored in the device, and the device algorithm-selection code. On initial power-up operation, the device defaults to the read mode. The TMS29xF040 is offered in a 32-pin 8 x 14 mm thin small-outline package (DBW suffix), a 32-pin 8 x 20 mm thin small-outline package (DD suffix), and a 32-pin plastic leaded chip carrier (FM suffix) using 1.27 mm (50-mil) lead pitch.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
DBW and DD PACKAGES ( TOP VIEW )
A11 A9 A8 A13 A14 A17 W VCC A18 A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
device symbol nomenclature
TMS29LF040 -10 C5 DBW L
Temperature Range Designator L = Commercial (0C to 70C) E = Extended ( - 40C to 85C) Package Designator DD = Thin Small-Outline Package (8 x 20 mm) DBW = Thin Small-Outline Package (8 x 14 mm) FM = Plastic Leaded Chip Carrier Program / Erase Endurance C5 = 100 000 Cycles Speed Designator 'LF040 -80 = 80 ns -90 = 90 ns -10 = 100 ns -12 = 120 ns -15 = 150 ns
'VF040 -10 = 100 ns -12 = 120 ns -15 = 150 ns
VCC Range Designator L = 3.3 V 0.3 V VCC (Low Voltage) V = 2.7 V - 3.6 V VCC (Very Low Voltage)
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
block diagram
DQ0 - DQ7 VCC VCC Detector
VSS Timer Input/Output Buffers
Command Register W Erase-Voltage Generator State Control Program-Voltage Generator Data Latch
E G
Chip-Enable Output-Enable Logic
A0 - A18
A d d r e s s L a t c h
Column Decoder
Column-Gating 64K x 8-Bit Array 64K x 8-Bit Array 64K x 8-Bit Array 64K x 8-Bit Array
Row-Decoder
64K x 8-Bit Array 64K x 8-Bit Array 64K x 8-Bit Array 64K x 8-Bit Array
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
memory-sector architecture
7FFFFh 64K-Byte Sector 7 70000h 6FFFFh 64K-Byte Sector 6 60000h 5FFFFh 64K-Byte Sector 5 50000h 4FFFFh 64K-Byte Sector 4 40000h 3FFFFh 64K-Byte Sector 3 30000h 2FFFFh 64K-Byte Sector 2 20000h 1FFFFh 64K-Byte Sector 1 10000h 0FFFFh 64K-Byte Sector 0 00000h
Sector 0 Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6 Sector 7
A18 0 0 0 0 1 1 1 1
A17 0 0 1 1 0 0 1 1
A16 0 1 0 1 0 1 0 1
Address Range 00000h - 0FFFFh 10000h - 1FFFFh 20000h - 2FFFFh 30000h - 3FFFFh 40000h - 4FFFFh 50000h - 5FFFFh 60000h - 6FFFFh 70000h - 7FFFFh
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operation
Table 1 summarizes the operation modes. Table 1. Operation Modes
FUNCTIONS MODE Read Output disable Standby and write inhibit Algorithm selection mode Algorithm-selection Write Sector-protect Sector-protect verify Sector-unprotect Sector-unprotect verify Erase operations E VIL VIL VIH VIL VIL VIL VIL VID VIL VIL G VIL VIH X VIL VIH VID VIL VID VIL VIH W VIH VIH X VIH VIL VIL VIH VIL VIH See Note 1 A0 A0 X X VIL VIH A0 X VIL X VIL See Note 1 A1 A1 X X VIL A1 X VIH X VIH See Note 1 A6 A6 X X VIL A6 X VIL VIH VIH See Note 1 A9 A9 X X VID A9 VID VID VID VID See Note 1 DQ0 - DQ7 Data out Hi-Z Hi-Z Mfr. equivalent code 97h Device equivalent code 94h Data in X Data out X Data out See Note 1
X can be VIL or VIH. See Table 3 for valid address and data during write (byte program). Operation at VCC = 3.3 V and TA = 25C. Address pins A12 and A16 = VIH. NOTE 1: See Figure 6 through Figure 9.
read mode To read the output of the TMS29xF040, a low-level logic signal is applied to the E and G pins. When two or more TMS29xF040 devices are connected in parallel, the output of any one device can be read without interference. The E pin is power control and is used for device selection. The G pin is output control and is used to gate the data output onto the bus from the selected device. The address-access time (tAVQV) is the delay from stable address to valid output data. The chip-enable access time (tELQV) is the delay from E = VIL and stable addresses to valid output data. The output-enable access time (tGLQV) is the delay from G = VIL to valid output data when E = VIL and addresses are stable for at least the duration of tAVQV - tGLQV. standby mode The ICC supply current is reduced by applying a logic-high level on E to enter the standby mode. In the standby mode, the outputs are placed in the high-impedance state. Applying a CMOS logic-high level on E reduces the current to 100 A maximum. If the TMS29xF040 is deselected during erasure or programming, the device continues to draw active current until the operation is complete. output disable When either G = VIH or E = VIH, output from the device is disabled and the output pins (DQ0 - DQ7) are placed in the high-impedance state.
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
algorithm selection mode The algorithm-selection mode provides access to a binary code that matches the device with its proper programming- and erase-command operations. This mode is activated when VID (11.5 V to 12.5 V) is placed on address pin A9. Address pins A1 and A6 must be logic low. Two bytes of code are accessed by toggling the address pin A0 from VIL to VIH. All other address pins can be logic low or logic high. The algorithm-selection code also can be read by using the command register, which is useful when VID is not available to be placed on address pin A9. Table 2 lists the binary algorithm-selection codes for the TMS29xF040. Table 2. Algorithm-Selection Codes
ALGORITHM SELECTION Byte 0 Byte 1 A1 = VIL, A6 = VIL, E = VIL, G = VIL A0 0 1 DQ7 1 1 DQ6 0 0 DQ5 0 0 DQ4 1 1 DQ3 0 0 DQ2 1 1 DQ1 1 0 DQ0 1 0 HEX 97h 94h
erasure and programming Erasure and programming of the TMS29xF040 are accomplished by writing a sequence of commands using standard microprocessor write timings. The commands are written to a command register and input to the command-state machine (CSM). The CSM interprets the command entered and initiates program, erase, suspend, and resume operations as instructed. The CSM acts as the interface between the write-state machine (WSM) and the external chip operations. The WSM controls all voltage generation, pulse generation, preconditioning, and verification of the memory contents. Program and sector/chip-erase functions are fully automatic. When the end of a program or erase operation is reached, the device internally resets to the read mode. If a byte-program or chip-erase operation is in progress, additional program/erase commands are ignored until the operation in progress is completed. command definitions Device operating modes are selected by writing specific address and data sequences into the command register. Table 3 defines the valid command sequences. Writing incorrect address and data values or writing them in the incorrect sequence causes the device to reset to the read mode. The command register does not occupy an addressable memory location. The register stores the command sequence along with the address and data needed by the memory array. Commands are written by setting E = VIL and G = VIH and bringing W from VIH to VIL. Addresses are latched on the falling edge of W and data is latched on the rising edge of W. Holding W = VIL and toggling E is an alternative method. See the byte-program and chip/sector-erase sections for a more complete description.
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command definitions (continued) Table 3. Command Definitions
COMMAND Read Reset/Read Algorithm selection Byte program Chip erase Sector erase Sector-erase suspend Sector-erase resume BUS CYCLES 1 2 4 4 4 6 6 1ST CYCLE ADDR DATA RA RD RA RD 5555h F0h 5555h 90h 5555h A0h 5555h 80h 5555h 80h RA RA PA RD RD PD 2AAAh 55h 2AAAh 55h 5555h 10h SA 30h 2AAAh 55h 2AAAh 55h 2AAAh 55h 2AAAh 55h 2AAAh 55h 2ND CYCLE ADDR DATA 3RD CYCLE ADDR DATA 4TH CYCLE ADDR DATA 5TH CYCLE ADDR DATA 6TH CYCLE ADDR DATA
XXXXh F0h 5555h AAh 5555h AAh 5555h AAh 5555h AAh 5555h AAh XXXXh B0h XXXXh 30h
5555h AAh 5555h AAh
Erase-suspend valid during sector-erase operation Erase-resume valid only after erase-suspend
RA = Address of the location to be read PA = Address of the location to be programmed SA = Address of the sector to be erased Addresses A16, A17, and A18 select one of eight sectors RD = Data to be read at selected address location PD = Data to be programmed at selected address location Address pins A15, A16, A17, A18 = VIL or VIH for all bus cycle addresses except for program address (PA), sector address (SA), and read address (RA). No command cycles are required when the device is in read mode. The reset command is required to return to the read mode when the device is in the algorithm-selection mode or if DQ5 goes high.
reset/read command The read mode is activated by writing either of the two reset command sequences into the command register. The device remains in this mode until another valid command sequence is input into the command register. Memory data is available in the read mode and can be read with standard microprocessor read-cycle timing. On power up, the device defaults to the read mode; therefore, a reset command sequence is not required and memory data is available. algorithm-selection command The algorithm-selection command allows access to a binary code that matches the device with the proper programming and erase-command operations. After writing the three-bus-cycle command sequence, the first byte of the algorithm-selection code (97h) can be read from address XX00h. The second byte of the code (94h) can be read from address XX01h (see Table 2). This mode remains in effect until another valid command sequence is written to the device. Sector-protection can be determined using the algorithm-selection command. After issuing the three-bus-cycle command sequence, the sector-protection status can be read on DQ0. Set address pins A0 = VIL and A1 = VIH. The sector address pins A16, A17, and A18 select the sector to be checked. The remaining address pins can be VIL or VIH. If the sector selected is protected, DQ0 outputs a 1. If the sector selected is not protected, DQ0 outputs a 0. This mode remains in effect until another valid command sequence is written to the device. byte-program command Byte-programming is a four-bus-cycle command sequence. The first three bus cycles put the device into the program-setup state. The fourth bus cycle loads the address location and the data to be programmed into the device. The addresses are latched on the falling edge of W and the data is latched on the rising edge of W inthe fourth bus cycle. The rising edge of W starts the byte-program operation. The embedded byte-programming function automatically provides voltage and timing to program and to verify the cell margin. Any further commands written to the device during the program operation are ignored.
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
byte-program command (continued) Programming can be performed at any address location in any order, resulting in logic 0s being programmed into the device. Attempting to program a logic 1 into a bit that was previously programmed to a logic 0 causes the internal pulse counter to exceed the pulse-count limit. This sets the exceed-timing-limit indicator (DQ5) to a logic-high state. Only an erase operation can change bits from logic 0s to logic 1s. When erased, all bits become logic 1. Figure 3 shows a flow chart of the typical byte-programming operation. The status of the device during the automatic programming operation can be monitored for completion using the data-polling feature or the toggle-bit feature. See the operation status section for a full description. chip-erase command Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup state. The next two bus cycles unlock the erase mode and then the sixth bus cycle loads the chip-erase command. This command sequence is required to ensure that the memory contents are not erased accidentally. The rising edge of W starts the chip-erase operation. Any further commands written to the device during the chip-erase operation are ignored. The embedded chip-erase function automatically provides the voltage and timing needed to program and verify all the memory cells prior to electrical erase, and then erases and verifies the cell margin automatically. The user is not required to program the memory cells prior to erase. The status of the device during the automatic chip-erase operation can be monitored for completion using the data-polling feature or the toggle-bit feature. See the operation status section for a full description. Figure 6 shows a flow chart of the typical chip-erase operation. sector-erase command Sector erase is a six-bus-cycle command sequence. The first three bus cycles cause the device to go into the erase-setup state. The next two bus cycles unlock the erase mode, and the sixth bus cycle loads the sector-erase command and the sector-address location to be erased. Any address location within the desired sector can be used. The addresses are latched on the falling edge of W and the sector-erase command (30h) is latched on the rising edge of W in the sixth bus cycle. After a delay of 80 s from the rising edge of W, the sector-erase operation begins on the selected sector(s). Additional sectors can be selected to be erased concurrently during the sector-erase command sequence. For each additional sector to be selected for erase, another bus cycle is issued. The bus cycle loads the next sector-address location and the sector-erase command. The time between the end of the previous bus cycle and the start of the next bus cycle must be less than 80 s; otherwise, the new sector location is not loaded. A time delay of 80 s from the rising edge of the last W starts the sector-erase operation. If there is a falling edge of W within the 80-s time delay, the timer is reset. One to eight sector-address locations can be loaded in any order. The state of the delay timer can be monitored using the sector-erase delay indicator (DQ3). If DQ3 is logic-low, the time delay has not expired. See the operation status section for a description. Any command other than erase suspend (B0h) or sector erase (30h) written to the device during the sector-erase operation causes the device to exit the sector-erase mode and the contents of the sector(s) selected for erase are no longer valid. To complete the sector-erase operation, the sector-erase command sequence must be repeated. The embedded sector-erase function automatically provides needed voltage and timing to program and to verify all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically. Programming the memory cells prior to erase is not required. The status of the device during the automatic sector-erase operation can be monitored for completion by using the data-polling feature or the toggle-bit feature. See the operation status section for a full description. Figure 8 shows a flow chart of the typical sector-erase operation.
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erase-suspend command The erase-suspend command (B0h) allows interruption of a sector-erase operation to read data from unaltered sectors of the device. Erase-suspend is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-suspend command (B0h) is latched on the rising edge of W. Once the sector-erase operation is in progress, the erase-suspend command requests the internal write-state machine to halt operation at predetermined breakpoints. The erase-suspend command is valid only during the sector-erase operation and is invalid during the byte-programming and chip-erase operations. The sector-erase delay timer expires immediately if the erase-suspend command is issued while the delay is active. After the erase-suspend command is issued, the device typically takes between 0.1 s and 15 s to suspend the operation. The toggle bit must be monitored to determine when the suspend has been executed. When the toggle bit stops toggling, data can be read from sectors that are not selected for erase. Reading from a sector selected for erase can result in invalid data. See the operation status section for a full description. Once the sector-erase operation is suspended, further writes of the erase-suspend command are ignored. The erase-resume command (30h) causes the device to restart the suspended sector operation. To erase additional sectors, reissue the six-cycle sector-erase command sequence. Any other command sequence written while in suspend mode causes the device to reset to the read mode. erase-resume command The erase-resume command (30h) restarts a suspended sector-erase operation from where it was halted to completion. Erase resume is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-resume command (30h) is latched on the rising edge of W. When an erase-suspend/erase-resume command combination is written, the internal pulse counter is reset to zero and the exceed-timing-limit indicator (DQ5) is set to logic-low. The erase-resume command is valid only in the erase-suspend state. After the erase-resume command is executed, the device returns to the valid sector-erase state and further writes of the erase-resume command are ignored. After the device has resumed the sector-erase operation, another erase-suspend command can be issued to the device.
operation status
status-bit definitions During operation of the embedded program and erase functions, the status of the device can be determined by reading the data state of designated outputs. The data-polling bit (DQ7) and toggle bit (DQ6) require multiple successive reads to observe a change in the state of the designated output. Table 4 defines the values of the status flags. Table 4. Operation Status Flags
Device Operation Byte-programming in progress Byte-programming exceed time limit Byte-programming complete Sector- / chip-erase in progress Sector- / chip-erase exceed time limit DQ7 DQ7 DQ7 D 0 0 DQ6 T T D T T DQ5 0 1 D 0 1 DQ4 X X D X X DQ3 0 0 D 1 1 1 DQ2 X X D X X 1 DQ1 X X D X X 1 DQ0 X X D X X 1
Sector- / chip-erase complete 1 1 1 1 T= toggle, D = data, X = data undefined, DQ7 = complement of data written to DQ7 DQ4, DQ2, DQ1, and DQ0 are reserved for future use.
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
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data-polling (DQ7) The data-polling status function outputs the complement of the data latched into the DQ7 data register while the write-state machine is engaged in a program or erase operation. Data bit DQ7 changing from complement to true indicates the end of an operation. Data-polling is available only during the byte-programming, chip-erase, sector-erase, and sector-erase timing delay. Data-polling is valid after the rising edge of W in the last bus cycle of the command sequence loaded into the command register. Figure 10 shows a flow chart of the data-polling operation. During a byte-program operation, reading DQ7 outputs the complement of the DQ7 data to be programmed at the selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the program data register. During the erase operations, reading DQ7 outputs a 0. Upon completion of erase operations, reading DQ7 outputs a 1. Also, data-polling must be performed at a sector address that is within a sector being erased; otherwise, the status is invalid. When using data-polling, the address must remain stable throughout the operation. During a data-polling read, while G is low, data bit DQ7 can change asynchronously with the other DQs. Depending on the read timing, the system can read valid data on DQ7, while other DQ pins are still invalid. The data on DQ0-DQ7 is valid with a subsequent read of the device. Figure 11 shows the data-polling timing diagram. toggle bit (DQ6) The toggle-bit status function outputs data on DQ6 that toggles between logic 1 and logic 0 while the write-state machine is engaged in a program or erase operation. When toggle bit DQ6 stops toggling after two consecutive reads to the same address, the operation is complete. The toggle bit is only available during the byte-programming, chip-erase, sector-erase, and sector-erase timing delay. Toggle-bit data is valid after the rising edge of W in the last bus cycle of the command sequence loaded into the command register. Figure 12 shows a flow chart of the toggle-bit status-read algorithm. Depending on the read timing, DQ6 can stop toggling while other DQ pins are still invalid. The data on DQ0-DQ7 is valid with a subsequent read of the device. Figure 13 shows the toggle-bit timing diagram. exceed-time-limit (DQ5) The program and erase operations use an internal pulse counter to limit the number of pulses applied. If the pulse count limit is exceeded, DQ5 is set to a logic 1, indicating that the program or erase operation has failed. DQ7 does not change from complemented data to true data and DQ6 does not stop toggling when read. The device must be reset to continue operation. This condition occurs when attempting to program a logic 1 into a bit that has been programmed previously to a logic 0. Only an erase operation can change bits from 0 to 1. After reset, the device is functional and can be erased and reprogrammed. sector-load-timer bit (DQ3) The sector-load-timer status bit, DQ3, is used to determine whether the time to load additional sector addresses has expired. After completion of a sector-erase command sequence, DQ3 remains at a logic 0 for 80 s. This indicates that another sector-erase command sequence can be issued. If DQ3 is at a logic 1, it indicates that the delay has expired and attempts to issue additional sector-erase commands are ignored. See the sector-erase command section for a description. The data-polling bit and toggle bit are valid during the 80-s time delay and can be used to determine if a valid sector-erase command has been issued. To ensure additional sector-erase commands have been accepted, the status of DQ3 should be read before and after each additional sector-erase command. If DQ3 is at a logic low on both reads, then the additional sector-erase command was accepted.
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data protection
hardware-sector protection feature This feature disables both programming and erase operations on any combination of one to eight sectors. Commands to program or erase a protected sector do not change the data contained in the sector. The data-polling and toggle bits operate for 2 s to 100 s and then return to valid data. This feature is enabled using high-voltage VID (11.5 V to 12.5 V) on address pin A9 and control pin G, and VIL on control pin E. Figure 14 shows a flow chart of the sector-protect operation. The device is delivered with all sectors unprotected. The sector-unprotect mode is available to unprotect protected sectors. Figure 16 is a flow chart of the sector-unprotect operation. sector-protect operation The sector-protect mode is activated when VCC = 3.3 V (operating at TA = 25C), W = VIH, E= VIL, and address pin A9 and control pin G are forced to VID. The sector-select address pins A16, A17, and A18 are used to select the sector to be protected. Address pins A0-A8, A10-A15, and I/O pins DQ0-DQ7 must be stable and can be VIL or VIH. Once the addresses are stable, W is pulsed low for 100 s. The operation begins on the falling edge of W and terminates on the rising edge of W. Figure 15 shows a timing diagram of the sector-protect operation. sector-protect verify Verification of sector-protection is activated when VCC = 3.3 V (operating at TA = 25C), W = VIH, G = VIL, E = VIL, and address pin A9 = VID. Address pins A0 and A6 are set to VIL, and A1 is set to VIH. The sector-address pins A16, A17, and A18 select the sector to be verified. The other address pins can be VIH or VIL. If the sector selected is protected, the DQs output 01h. If the sector selected is not protected, the DQs output 00h. sector-unprotect operation Prior to a sector-unprotect operation, all sectors should be protected using the sector-protect mode. Sector-unprotect mode is activated when VCC = 3.3 V (operating at TA = 25C), W = VIH, and address pin A9 and control pins G and E are forced to VID. Address pins A6, A12, and A16 are set to VIH. The sector-select address pins A17 and A18 can be VIL or VIH. All eight sectors are unprotected in parallel. Once the inputs are stable, W is pulsed low for 10 ms. The unprotect operation begins on the falling edge of W and terminates on the rising edge of W. Figure 17 shows a timing diagram of the sector-unprotect operation. sector-unprotect verify Verification of the sector-unprotection is activated when VCC = 3.3 V (operating at TA = 25C), W = VIH, G = VIL, E = VIL, and address pin A9 = VID. The sector to be verified must be selected. Address pins A1 and A6 are set to VIH, and A0 is set to VIL. The other address pins can be VIH or VIL. If the sector that is selected is protected, the DQs output 01h. If the sector selected is not protected, the DQs output 00h. glitching Pulses of less than 5 ns (typical) on G, W, or E do not issue a write cycle. power supply considerations Each device should have a 0.1-F ceramic capacitor connected between VCC and VSS to suppress circuit noise. Printed-circuit traces to VCC should be appropriate to handle the current demand and minimize inductance.
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
absolute maximum ratings over operating ambient temperature range (unless otherwise noted)
Voltage range with respect to ground: Supply voltage range, VCC (see Note 2) . . . . . . . . . . . . . . . . . . . . . -0.5 V to + 3.6 V All pins except A9, E, G (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to + 3.6 V A9, E, G (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to + 13.5 V Ambient temperature range during read / erase / program, TA Commercial (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Extended (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 2. Minimum dc voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum dc voltage on input and I/O pins is +3.6 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. 3. Minimum dc input voltage on A9, E, and G pins is -0.5 V. During voltage transitions, A9, E, and G may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum dc input voltage on A9, E, and G pins is +12.5 V, which may overshoot to +13.5 V for periods up to 20 ns.
recommended operating conditions
MIN VCC TA Supply voltage Ambient temperature during read/erase/program '29LF040 VCC range '29VF040 VCC range Commercial (L) Extended (E) 3 2.7 0 -40 NOM 3.3 3 MAX 3.6 3.6 70 85 UNIT V C
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
electrical dc characteristics over recommended ranges of supply voltage and ambient temperature
PARAMETER VIH VIL VID VOH VOL II IO IID ICC1 ICC2 ICC3 High-level dc input voltage Low-level dc input voltage CMOS CMOS VCC = 3.3 V VCC = VCC MIN VCC = VCC MIN VCC = VCC MIN VCC = VCC MAX VCC = VCC MAX VCC = VCC MAX E = VIL, E = VIL, VCC = VCC MAX IOH = - 2.0 mA IOH = - 100 A IOL = 4.0 mA VI = VSS to VCC VO = VSS to VCC A9 = 12.5 V G = VIH G = VIH E = VCC 0.3 V TEST CONDITIONS MIN 0.7 * VCC - 0.5 11.5 0.85 * VCC VCC - 0.4 0.45 1 1 50 40 60 100 MAX VCC + 0.3 0.8 12.5 UNIT V V V V V A A A mA mA A
Algorithm-selection and sector-protect/unprotect input voltage High level dc output voltage High-level Low-level dc output voltage (see Note 4) Input current (leakage) Output current (leakage) High-voltage load current VCC active current (see Note 5) VCC active current (see Notes 6) VCC supply current (standby) CMOS-input level CMOS CMOS CMOS
See the recommended operating conditions table. NOTES: 4. 5.8-mA IOL also available 5. ICC current in the read mode, switching at 6 MHz, IOUT = 0 mA 6. ICC current while erase or program operation is in progress
capacitance over recommended ranges of supply voltage and ambient temperature
PARAMETER Ci1 Ci2 Co Input capacitance (All inputs except A9, E, G) Input capacitance (A9, E, G) Output capacitance TEST CONDITIONS VI = 0 V, VI = 0 V, f = 1 MHz f = 1 MHz MIN MAX 7.5 9 12 UNIT pF pF pF
VO = 0 V, f = 1 MHz
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
switching characteristics over recommended ranges of supply voltage and ambient temperature, read-only operation (see Figure 2, Figure 11, Figure 13, Figure 15, and Figure 17)
PARAMETER tAVQV tELQV tGLQV tAVAV tEHQZ tGHQZ tAXQX tWHGL1 tWHGL2 Access time, address Access time, E Access time, G Cycle time, read Disable time, E to high impedance Disable time, G to high impedance Hold time, output from address, E or G change Hold time, G read Hold time, G toggle and data polling ALTERNATE SYMBOL ta(A) ta(E) ta(G) tc(R) tdis(E) tdis(G) th(D) 80 20 20 0 0 10 0 0 10 '29LF040-80 MIN MAX 80 80 35 90 20 20 0 0 10 '29LF040-90 MIN MAX 90 90 40 100 30 30 '29LF040-10 '29VF040-10 MIN MAX 100 100 45 ns ns ns ns ns ns ns ns ns UNIT
PARAMETER tAVQV tELQV tGLQV tAVAV tEHQZ tGHQZ tAXQX Access time, address Access time, E Access time, G Cycle time, read Disable time, E to high impedance Disable time, G to high impedance Hold time, output from address, E or G change
ALTERNATE SYMBOL ta(A) ta(E) ta(G) tc(R) tdis(E) tdis(G) th(D)
'29LF040-12 '29VF040-12 MIN MAX 120 120 50 120 30 30 0 0 10
'29LF040-15 '29VF040-15 MIN MAX 150 150 55 150 35 35 0 0 10
UNIT ns ns ns ns ns ns ns ns ns
tWHGL1 Hold time, G read tWHGL2 Hold time, G toggle and data polling See Figure 1 for ac test output load circuit and voltage waveforms.
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SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
timing requirements controlled by W (see Figure 4, Figure 7, Figure 9, Figure 11, Figure 13, Figure 15, and Figure 17)
ALTERNATE SYMBOL tAVAV tWHWH1 tWHWH2 tWHWH3 tWLAX tWHDX tWHEH tWHWL tWLWH1 tWLWH2 tWLWH3 tGHWL tAVWL tDVWH tAVGH Cycle time, write Cycle time, programming operation Cycle time, sector-erase operation Cycle time, chip-erase operation Hold time, address Hold time, data valid after W high Hold time, E Pulse duration, W high Pulse duration, W low Pulse duration, W low (see Note 7) Pulse duration, W low (see Note 8) Recovery time, read before write Setup time, address Setup time, data Setup time, A0 and A6 low and A1 high to G high (see Note 7) Setup time, A0 low and A1 high to G and E high (see Note 8) Setup time, E Setup time, G Setup time, VCC Setup time, E VID to W (see Note 8) Setup time, G VID to W (see Notes 7 and 8) Transition time, VID (see Notes 7 and 8) tsu(E) trec(R) tsu(A) tsu(D) th(A) th(D) th(E) tw(WH) tw(WL) 45 0 0 20 35 100 10 0 0 35 0 tc(W) tc(W)PR '29LF040-80 MIN 80 20 2 14 30 120 45 0 0 20 45 100 10 0 0 45 0 TYP MAX '29LF040-90 MIN 90 20 2 14 30 120 45 0 0 20 45 100 10 0 0 45 0 TYP MAX '29LF040-10 '29VF040-10 MIN 100 20 2 14 30 120 TYP MAX ns s s s ns ns ns ns ns s ms ns ns ns ns UNIT
tAVGEH tELWL tGHWH tVCEL tEHVWL tGHVWL tHVT
0 0 0 50 4 4 4
0 0 0 50 4 4 4
0 0 0 50 4 4 4
ns ns ns s s s s
NOTES: 7. Sector-protect timing (see Figure 15) 8. Sector-unprotect timing (see Figure 17)
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
timing requirements controlled by W (see Figure 4, Figure 7, Figure 9, Figure 11, Figure 13, Figure 15, and Figure 17) (continued)
ALTERNATE SYMBOL tAVAV tWHWH1 tWHWH2 tWHWH3 tWLAX tWHDX tWHEH tWHWL tWLWH1 tWLWH2 tWLWH3 tGHWL tAVWL tDVWH tAVGH tAVGEH tELWL tGHWH tVCEL tEHVWL tGHVWL Cycle time, write Cycle time, programming operation Cycle time, sector-erase operation Cycle time, chip-erase operation Hold time, address Hold time, data valid after W high Hold time, E Pulse duration, W high Pulse duration, W low Pulse duration, W low (see Note 7) Pulse duration, W low (see Note 8) Recovery time, read before write Setup time, address Setup time, data Setup time, A0 and A6 low and A1 high to G high (see Note 7) Setup time, A0 low and A1 high to G and E high (see Note 8) Setup time, E Setup time, G Setup time, VCC Setup time, E VID to W (see Note 8) Setup time, G VID to W (see Notes 7 and 8) tsu(E) trec(R) tsu(A) tsu(D) th(A) th(D) th(E) tw(WH) tw(WL) 50 0 0 20 50 100 10 0 0 50 0 0 0 0 50 4 4 4 tc(W) tc(W)PR '29LF040-12 '29VF040-12 MIN 120 20 2 14 30 120 50 0 0 20 50 100 10 0 0 50 0 0 0 0 50 4 4 4 TYP MAX '29LF040-15 '29VF040-15 MIN 150 20 2 14 30 120 TYP MAX ns s s s ns ns ns ns ns s ms ns ns ns ns ns ns ns s s s s UNIT
tHVT Transition time, VID (see Notes 7 and 8) NOTES: 7. Sector-protect timing (see Figure 15) 8. Sector-unprotect timing (see Figure 17)
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
timing requirements controlled by E (see Figure 5)
ALTERNATE SYMBOL tAVAV tEHEH1 tEHEH2 tEHEH3 tELAX tEHDX tEHWH tELEH tEHEL tGHEL tAVEL tDVEH tWLEL Cycle time, write Cycle time, programming operation Cycle time, sector-erase operation (see Note 9) Cycle time, chip-erase operation (see Note 10) Hold time, address Hold time, data Hold time, W Pulse duration, E low Pulse duration, E high Recovery time, read before write Setup time, address Setup time, data Setup time, W th(A) th(D) th(W) tw(EL) tw(EH) trec(R) tsu(A) tsu(D) tsu(W) 45 0 0 35 20 0 0 35 0 tc(W) '29LF040-80 MIN 80 20 2 14 30 120 45 0 0 45 20 0 0 45 0 TYP MAX '29LF040-90 MIN 90 20 2 14 30 120 45 0 0 45 20 0 0 45 0 TYP MAX '29LF040-10 '29VF040-10 MIN 100 20 2 14 30 120 TYP MAX ns s s s ns ns ns ns ns ns ns ns ns UNIT
ALTERNATE SYMBOL tAVAV tEHEH1 tEHEH2 tEHEH3 tELAX tEHDX tEHWH tELEH tEHEL tGHEL tAVEL tDVEH Cycle time, write Cycle time, programming operation Cycle time, sector-erase operation (see Note 9) Cycle time, chip-erase operation (see Note 10) Hold time, address Hold time, data Hold time, W Pulse duration, E low Pulse duration, E high Recovery time, read before write Setup time, address Setup time, data th(A) th(D) th(W) tw(EL) tw(EH) trec(R) tsu(A) tsu(D) tc(W)
'29LF040-12 '29VF040-12 MIN 120 20 2 14 50 0 0 50 20 0 0 50 0 30 120 TYP MAX
'29LF040-15 '29VF040-15 MIN 150 20 2 14 50 0 0 50 20 0 0 50 0 30 120 TYP MAX
UNIT ns s s s ns ns ns ns ns ns ns ns ns
tWLEL Setup time, W tsu(W) NOTES: 9. Timing diagram of E-controlled sector-erase operation not enclosed. 10. Timing diagram of E-controlled chip-erase operation not enclosed.
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
0.1 mA IOL
1.50 V
Output Under Test CL = 30 pF (see Note A, Note B, and Note C) - 0.1 mA IOH
3.0 V 1.5 V 0.0 V NOTES: A. CL includes probe and fixture capacitance. B. The ac testing inputs are driven at 3 V for logic high and 0 V for logic low. Timing measurements are made at 1.5 V for logic high and 1.5 V for logic low on both inputs and outputs. Each device should have a 0.1-F ceramic capacitor connected between VCC and VSS as closely as possible to the device pins. C. Input rise and fall 5 ns. 1.5 V
Figure 1. AC Test Output Load Circuit and Voltage Waveforms
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
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read operation
tAVAV Addresses Valid Addresses
tAVQV E tEHQZ tELQV G tGHQZ tGLQV
W tAXQX tWHGL1 DQ0 - DQ7 Valid Data
Figure 2. AC Waveform for Read Operation
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
write operation
Start
Write Bus Cycle 5555H / AAH
Write Bus Cycle 2AAAH / 55H
Write Bus Cycle 5555H / A0H
Write Bus Cycle Program Address / Program Data
Poll Device Status
Operation Complete ?
No
Yes
No Next Address
Last Address ?
Yes End
Figure 3. Byte-Program Algorithm
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write operation (continued)
tAVAV Addresses 5555H tWLAX tAVWL E tELWL tWHEH G tGHWL tWLWH1 W tWHWH1 tDVWH DQ0 - DQ7 AAH 55H A0H PD DQ7 DOUT tWHDX tWHWL 2AAAH 5555H PA PA
NOTES: A. PA = Address of the location to be programmed B. PD = Data to be programmed C. DQ7 = Complement of data written to DQ7
Figure 4. AC Waveform for Byte-Program (W-Controlled) Operation
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
write operation (continued)
tAVAV Addresses 5555H tAVEL tELEH E tELAX 2AAAH 5555H PA PA
tGHEL G
tEHEL tDVEH tWLEL tEHEH1 tEHWH
W
tEHDX DQ0- DQ7 AAH 55H A0H PD DQ7 DOUT
NOTES: A. PA = Address of the location to be programmed B. PD = Data to be programmed C. DQ7 = Complement of data written to DQ7
Figure 5. AC Waveform for Byte-Program (Alternate E-Controlled) Operation
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
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chip-erase operation
Start
Write Bus Cycle 5555H / AAH
Write Bus Cycle 2AAAH / 55H
Write Bus Cycle 5555H / 80H
Write Bus Cycle 5555H / AAH
Write Bus Cycle 2AAAH / 55H
Write Bus Cycle 5555H / 10H
Poll Device Status
Operation Complete ?
No
Yes End
Figure 6. Chip-Erase Algorithm
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
chip-erase operation (continued)
tAVAV Addresses 5555H tAVWL tWLAX E tELWL tWHEH G tGHWL tWHWL tWLWH1 W tDVWH tWHDX DQ0 - DQ7 AAH tVCEL VCC NOTE A: VA = any valid address 55H 80H AAH 55H 10H DQ7=0 DOUT=FFH 2AAAH 5555H 5555H 2AAAH 5555H VA
tWHWH3
Figure 7. AC Waveform for Chip-Erase Operation
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
sector-erase operation
Start
Write Bus Cycle 5555H / AAH
Write Bus Cycle 2AAAH / 55H
Write Bus Cycle 5555H / 80H
Write Bus Cycle 5555H/AAH
Write Bus Cycle 2AAAH / 55H
Write Bus Cycle Sector Address / 30H
No DQ3 = 0 ?
Yes Yes Load Additional Sectors ? No Poll Device Status
No
Operation Complete ? Yes End
Figure 8. Sector-Erase Algorithm
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
sector-erase operation (continued)
tAVAV Addresses 5555H tAVWL tWLAX E tELWL tWHEH G tGHWL tWHWL tWLWH1 W tDVWH tWHDX DQ0 - DQ7 AAH tVCEL VCC 55H 80H AAH 55H 30H DQ7=0 DOUT=FFH 2AAAH 5555H 5555H 2AAAH SA SA
tWHWH2
NOTE A: SA = Sector address to be erased
Figure 9. AC Waveform for Sector-Erase Operation
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
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data-polling operation
Start
Read DQ0 - DQ7 ADDR = VA
DQ7 = Data ?
Yes
No No DQ5 = 1 ?
Yes Read DQ0 - DQ7 ADDR = VA
DQ7 = Data ? No Fail
Yes
Pass
NOTES: A. DQ7 is checked again after DQ5 is checked, even if DQ5 = 1. B. VA = Program address for byte-programming = Selected sector address for sector erase = Any valid address for chip erase
Figure 10. Data-Polling Algorithm
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
data-polling operation (continued)
Addresses AIN AIN AIN
tAVQV tAVQV tAXQX tELQV E tELQV
tGLQV
tGLQV
G
tWHGL2 tGHQZ
W
tWHWH1, 2, or 3
DQ
DIN
DQ7
DQ7
DQ7
DOUT
NOTES: A. B. C. D. E.
DIN = Last command data written to the device = Complement of data written to DQ7 DQ7 DOUT = Valid data output AIN = Valid address for byte-program, sector-erase, or chip-erase operation The data-polling operation is valid for both W- and E-controlled byte-program, sector-erase, and chip-erase operations.
Figure 11. AC Waveform for Data-Polling Operation
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toggle-bit operation
Start
Read DQ0 - DQ7 ADDR = VA
Read DQ0 - DQ7 ADDR = VA
DQ6 = Toggle ?
No
Yes No DQ5 = 1 ?
Yes Read DQ0 - DQ7
DQ6 = Toggle ? Yes Fail
No
Pass
NOTE A: DQ6 is checked again after DQ5 is checked, even if DQ5 = 1.
Figure 12. Toggle-Bit Algorithm
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
toggle-bit operation (continued)
Addresses AIN
tELQV E
tAVQV tELQV
tGLQV tGLQV G tGHWH tWHGL2 W
tWHWH1, 2, OR 3
DQ
DIN
DQ6 = Toggle
DQ6 = Toggle
DQ6 = Toggle
DQ6 = Stop Toggle
DOUT
NOTES: A. B. C. D. E.
DIN = Last command data written to the device DQ6 = Toggle bit output DOUT = Valid data output AIN = Valid address for byte-program, sector-erase, or chip-erase operation The toggle-bit operation is valid for both W- and E-controlled byte-program, sector-erase, and chip-erase operations.
Figure 13. AC Waveform for Toggle-Bit Operation
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sector-protect operation
Start
Select Sector Address A18, A17, A16
X=1
G and A9 = VID E = VIL Apply One 100-s Pulse G, A0, and A6 = VIL W and A1 = VIH
X = X+1
Read Data No
X = 25 ?
No Data = 01H ? Yes
Yes
Sector Protect Failed
Protect Additional Sectors ? No A9 = VIH or VIL Write Reset Command
Yes
End
Figure 14. Sector-Protect Algorithm
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
sector-protect operation (continued)
A18-A16 Sector Address
VID A9 tHVT
A6
A1
A0
tAVGH E
VID G tHVT tGHVWL tWLWH2 tHVT
W tGLQV DQ DOUT
NOTE A: DOUT = 00H if selected sector is not protected, = 01H if the sector is protected
Figure 15. AC Waveform for Sector-Protect Operation
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sector-unprotect operation
Start
Protect All Sectors
X=1
E, G, A9 = VID A6, A12, A16 = VIH Apply One 10-ms Pulse E, G, A0 = VIL W, A6, A1 = VIH Select Sector Address A18, A17, A16
X = X+1
Read Data No
X=1000 ?
No Data = 00H ? Yes
Next Sector Address
Yes
Sector-Unprotect Failed
Last Sector ? Yes A9 = VIH or VIL Write Reset Command
No
End
Figure 16. Sector-Unprotect Algorithm
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
sector-unprotect operation (continued)
A18 - A17 Sector Address
A16
Sector Address
A12
VID A9 tHVT A6 tAVGEH tAVQV
A1
A0
VID E tHVT VID G tHVT tGHVWL W tGLQV DQ DOUT tWLWH3 tHVT tEHVWL
NOTE A: DOUT = 00H if selected sector is not protected, = 01H if the sector is protected
Figure 17. AC Waveform for Sector-Unprotect Operation
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
MECHANICAL DATA
FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER
Seating Plane 0.004 (0,10) 0.140 (3,56) 0.132 (3,35) 0.495 (12,57) 0.485 (12,32) 0.453 (11,51) 0.447 (11,35) 4 1 30 0.129 (3,28) 0.123 (3,12) 0.049 (1,24) 0.043 (1,09) 0.008 (0,20) NOM
5
29
0.020 (0,51) 0.015 (0,38) 0.595 (15,11) 0.585 (14,86) 0.553 (14,05) 0.547 (13,89) 0.030 (0,76) TYP
13
21
14 0.050 (1,27)
20
4040201-4 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-016
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
MECHANICAL DATA
DBW (R-PDSO-G32) PLASTIC THIN SMALL-OUTLINE PACKAGE
1 32 0.020 (0,50)
0.319 (8,10) 0.311 (7,90)
17 16 0.492 (12,50) 0.484 (12,30) 0.559 (14,20) 0.543 (13,80)
0.011 (0,27) 0.007 (0,17)
0.003 (0,08) M
0.006 (0,15) NOM Seating Plane 0.028 (0,70) 0.020 (0,50) 0.003 (0,08)
0.047 (1,20) MAX
0.006 (0,15) 0.002 (0,05) 4073304-2/C 10/97
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
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TMS29LF040, TMS29VF040 524288 BY 8-BIT FLASH MEMORIES
SMJS825D - SEPTEMBER 1995 - REVISED JUNE 1998
MECHANICAL DATA
DD (R-PDSO-G32)
1 32
PLASTIC THIN SMALL-OUTLINE PACKAGE
0.319 (8,10) 0.311 (7,90)
0.020 (0,50)
17 16 0.728 (18,50) 0.720 (18,30)
0.011 (0,27) 0.007 (0,17)
0.005 (0,12) M
0.028 (0,70) 0.020 (0,50) Seating Plane 0.003 (0,08) 0.006 (0,15) NOM 0.795 (20,20) 0.780 (19,80)
0.047 (1,20) MAX
0.006 (0,15) 0.002 (0,05)
4040097 / E 10/97 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
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