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128Mb: x8 DDR400 SDRAM Addendum
DOUBLE DATA RATE (DDR) SDRAM
FEATURES
* * * * 200 MHz Clock, 400 Mb/s/p data rate VDD = +2.65V 0.10V VDDQ = +2.65V 0.10V Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) for masking write data Programmable burst lengths: 2, 4, or 8 Concurrent Auto Precharge option supported Auto Refresh and Self Refresh Modes t RAS lockout (tRAP = tRCD)
MT46V16M8 - 4 Meg x 8 x 4 banks
For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds
GENERAL DESCRIPTION
The DDR400 SDRAM is a high-speed CMOS, dynamic random-access memory that operates at a frequency of 200 MHz (tCK=5ns) with a peak data transfer rate of 400Mb/s. DDR400 continues to use the JEDEC standard SSTL_2 interface and the 2n-prefetch architecture. The standard DDR200/DDR266 data sheets also pertain to the DDR400 device and should be referenced for a complete description of DDR SDRAM functionality and operating modes. However, to meet the faster DDR400 operating frequencies, some of the AC timing parameters, DC levels and operating temperatures are slightly tighter. This addendum data sheet will concentrate on the key differences required to support the enhanced speeds. The Micron 128Mb data sheet provides full specifications and functionality unless specified herein.
* * * * * * * * * * *
OPTIONS
PART NUMBER
16M8 TG
CONFIGURATION
Architecture Configuration Refresh Count Row Addressing Bank Addressing Column Addressing 16 Meg x 8 4 Meg x 8 x 4 banks 4K 4K (A0-A11) 4 (BA0, BA1) 1K (A0-A9)
* Configuration 16 Meg x 8 (4 Meg x 8 x 4 banks) * Plastic Package 66-Pin TSOP (400mil with 0.65mm pin pitch) * Timing - Cycle Time 5ns @ CL = 3(1) * Self Refresh Standard
NOTE: 1. Supports modules with 3-4-4 timing
-5 none
KEY TIMING PARAMETERS
SPEED GRADE -5 NOTE: CLOCK RATE CL = 31 200 MHz DATA-OUT ACCESS DQS-DQ WINDOW2 WINDOW 2.15ns 0.50ns SKEW +0.35ns
1. CL = CAS (Read) Latency 2. With a 50/50 clock duty cycle
128Mb: x8DDR400 SDRAM 128Mbx8DDR400.p65 - Rev. A (1/30/02-B)
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.
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128Mb: x8 DDR400 SDRAM Addendum
66-PIN TSOP PACKAGE DIMENSION 66-PIN TSOP PACKAGE PIN ASSIGNMENT
(TOP VIEW)
22.22 0.08 0.71 0.65 TYP 0.32 .075 TYP 0.10 (2X) SEE DETAIL A
11.76 0.10 10.16 0.08
PIN #1 ID
+0.03 0.15 -0.02
0.10 1.20 MAX
GAGE PLANE
0.25
0.10
+0.10 -0.05 0.80 TYP 0.50 0.10 DETAIL A
x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD DNU NC WE# CAS# RAS# CS# NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
x8 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
NOTE:
1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
128Mb: x8DDR400 SDRAM 128Mbx8DDR400.p65 - Rev. A (1/30/02-B)
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
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128Mb: x8 DDR400 SDRAM Addendum
PIN DESCRIPTIONS
PIN NUMBERS 45, 46 SYMBOL CK, CK# TYPE Input DESCRIPTION Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK#, and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Data Input/Output.
44
CKE
Input
24
CS#
Input
23, 22, 21 47
RAS#, CAS#, WE# DM
Input Input
26, 27 29-32 32, 35, 36 36, 38, 39 40, 29, 41
BA0, BA1
Input
A0, A1, A2 Input A3, A4, A5 A6, A7, A8 A9, A10, A11
2, 5, 8 11, 56, 59 62, 65 51
DQ0-2 DQ3-5 DQ6-7 DQS
I/O
I/O
Data Strobe: Output with read data, input with write data. DQS is edge-aligned with read data, centered in write data. It is used to capture data. (continued on next page)
128Mb: x8DDR400 SDRAM 128Mbx8DDR400.p65 - Rev. A (1/30/02-B)
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
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128Mb: x8 DDR400 SDRAM Addendum
PIN DESCRIPTIONS (continued)
PIN NUMBERS 4, 7, 10, 13, 14, 16, 17, 20, 20, 25, 42, 43, 53, 54, 57, 60, 63 19, 50 3, 9, 15, 55, 61 6, 12, 52, 58, 64 1, 18, 33 4, 48, 66 49 SYMBOL NC TYPE DESCRIPTION No Connect: These pins should be left unconnected.
DNU VDDQ VSSQ VDD VSS VREF
-
Do Not Use: Must float to minimize noise on Vref
Supply DQ Power Supply: +2.65V 0.10V. Isolated on the die for improved noise immunity. Supply DQ Ground. Isolated on the die for improved noise immunity. Supply Power Supply: +2.65V 0.10V. Supply Ground. Supply SSTL_2 reference voltage.
128Mb: x8DDR400 SDRAM 128Mbx8DDR400.p65 - Rev. A (1/30/02-B)
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
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128Mb: x8 DDR400 SDRAM Addendum
READ LATENCY
The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency should be set to 3 clocks, as shown in the CAS Latency Diagram and Mode Register Definition Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Mode Register Definition Diagram
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 0* 0* Operating Mode * M13 and M12 (BA0 and BA1) must be "0, 0" to select the base mode register (vs. the extended mode register).
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6543210 CAS Latency BT Burst Length
Mode Register (Mx)
Burst Length M2 M1 M0 0 0 0 0 1 1 1 1 00 01 10 11 00 01 10 11 M3 = 0 Reserved 2 4 8 Reserved Reserved Reserved Reserved M3 = 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
CAS Latency Diagram
T0 CK# CK COMMAND
READ NOP NOP NOP
T1
T2
T2n
T3
T3n
M3 0 1
Burst Type Sequential Interleaved
CL = 3 DQS DQ
M6 M5 M4 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved Reserved 3 Reserved Reserved Reserved Reserved
Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ TRANSITIONING DATA DON'T CARE
0 0 1 1 1 1
M11 M10 M9 M8 M7 0 0 0 0 0 0 0 1 0 0 -
M6-M0 Valid Valid -
Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved
128Mb: x8DDR400 SDRAM 128Mbx8DDR400.p65 - Rev. A (1/30/02-B)
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
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128Mb: x8 DDR400 SDRAM Addendum
ABSOLUTE MAXIMUM RATINGS*
VDD Supply Voltage Relative to VSS ....... -1V to +3.6V VDDQ Supply Voltage Relative to VSS .... -1V to +3.6V VREF and Inputs Voltage Relative to VSS .. -1V to +3.6V I/O Pins Voltage Relative to VSS . -0.5V to VDDQ +0.5V Operating Temperature, TA (ambient) .. 0C to +50C Storage Temperature (plastic) .......... -55C to +150C Power Dissipation .................................................. 1W Short Circuit Output Current ........................... 50mA *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1-5, 16; refer to DDR200/266 data sheet for all notes) (0C TA +50C; VDD = +2.65V 0.10V, VDDQ = +2.65V 0.10V) PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V VIN VDD, VREF pin 0V VIN 1.35V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: Full drive option - x8 High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) SYMBOL VDD VDDQ VREF VTT VIH(DC) VIL(DC) II IOZ MIN 2.55 2.55 MAX 2.75 2.75 UNITS NOTES V V V V V V A A 36, 41 36, 41, 44 6, 44 7, 44 28 28
0.49 x VDDQ 0.51 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -2 -5 VREF + 0.04 VDD + 0.3 VREF - 0.15 2 5
IOH IOL
-16.8 16.8
- -
mA mA
37, 39
AC INPUT OPERATING CONDITIONS
(Notes: 1-5, 16; refer to DDR200/266 data sheet for all notes) (0C TA +50C; VDD = +2.65V 0.10V, VDDQ = +2.65V 0.10V) PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage SYMBOL VIH(AC) VIL(AC) VREF(AC) MIN VREF + 0.310 - 0.49 x VDDQ MAX - VREF - 0.310 0.51 x VDDQ UNITS V V V NOTES 14, 28, 40 14, 28, 40 6
128Mb: x8DDR400 SDRAM 128Mbx8DDR400.p65 - Rev. A (1/30/02-B)
6
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
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128Mb: x8 DDR400 SDRAM Addendum
CAPACITANCE (TSOP)
(Notes: 1-5, 14-17, 33; refer to DDR200/266 data sheet for all notes) (0C TA 70C; VDDQ = +2.65V 0.10V, VDD = +2.65V 0.10V) PARAMETER Delta Input/Output Capacitance: DQs, DQS, DM DQ0-DQ7 Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE DCIO DCIO DCI1 DCI2 CIO CI1 CI2 CI3 - - - - 4.0 2.0 2.0 2.0 0.50 0.50 0.50 0.25 5.0 3.0 3.0 3.0 pF pF pF pF pF pF pF pF 13, 24 13, 24 13, 29 13, 29 13 13 13 13 SYMBOL MIN MAX UNITS NOTES
128Mb: x8DDR400 SDRAM 128Mbx8DDR400.p65 - Rev. A (1/30/02-B)
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
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128Mb: x8 DDR400 SDRAM Addendum
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1-5, 14-17, 33; refer to DDR200/266 data sheet for all notes) (0C TA 50C; VDDQ = +2.65V 0.10V, VDD = +2.65V 0.10V)
AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and control input pulse width LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data Hold Skew Factor ACTIVE to AUTOPRECHARGE command ACTIVE to PRECHARGE command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command SYMBOL tAC tCH tCL tCK tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIH F t IS F tIH S t IS S tIPW tMRD tQH tQHS tRAP tRAS tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR na tREFC tREFI tVTD tXSNR tXSRD -5 (TSOP) MIN MAX -0.6 +0.6 0.45 0.55 0.45 0.55 5 5 0.45 na 0.45 1.4 -0.50 +0.50 0.4 0.4 0.35 0.75 1.25 0.22 0.22 tCH,tCL +0.60 -0.60 0.75 0.75 na na 1.8 10 tHP tQHS 0.50 20 40 70,000 60 70 20 20 0.9 1.1 0.4 0.6 10 0.25 0 0.4 0.6 15 2 tQH - tDQSQ 140.6 15.6 0 75 200 UNITS ns tCK ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK ns tCK ns tCK ns tCK ns s s ns ns tCK NOTES 30 45,52 26,31 26,31 31
CL = 3
25, 26
34 18,42 18,43 14 14 14 14
25, 26 46 35 50
42
20, 21 19
25 23 23
128Mb: x8DDR400 SDRAM 128Mbx8DDR400.p65 - Rev. A (1/30/02-B)
8
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
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128Mb: x8 DDR400 SDRAM Addendum
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
128Mb: x8DDR400 SDRAM 128Mbx8DDR400.p65 - Rev. A (1/30/02-B) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
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