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APPLICATION NOTE
ST7544 - UNIVERSAL ANALOG FRONT-END
By Joel HULOUX
SUMMARY
I. I.1. I.2. I.3. I.4. I.4.1. I.4.2. I.5. I.5.1. I.5.2. I.6. I.6.1. I.6.2. I.6.3. I.6.4. II. II.1. II.1.1. II.1.2. II.2. II.2.1. II.2.2. II.3. II.3.1. II.3.2. II.3.3. II.4. II.4.1. II.4.2. III. ST7544. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIGNAL TRANSFER BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IIR FILTER OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coefficient Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IIR FILTER PROGRAMMING EXAMPLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FILTER COEFFICIENT CODING IN ST7544 TIME-SLOT FORMAT. . . . . . . . . . . . . . Filter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter Coefficients Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coefficient Coding in Time-Slot Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST7544 APPLICATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRYSTAL OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PERFORMANCE MEASUREMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTERFACING ST7544 WITH DSP56000 (MOTOROLA). . . . . . . . . . . . . . . . . . . . . .
Page
2 2 2 3 4 4 4 7 7 7 12 12 12 12 13 14 14 14 15 15 15 15 15 15 16 17 17 17 17 18 19 22
ANNEXE 1 : Schematics of Application Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANNEXE 2 : Layout of Application Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN654/1294
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ST7544 - UNIVERSAL ANALOG FRONT-END I - ST7544
. . .
I.1 - FEATURES FULL ECHO CANCELLING CAPABILITY FULLY COMPATIBLE WITH THE ST7543 (7543 mode) 16-BIT OVERSAMPLING A/D AND D/A CONVERTERS - Programmable down-sampling frequency from 7200 to 16000Hz - Sampling frequency can be 3, 4, 6, 8, 12, 16 x Symbol rate - Programmable Over sampling frequency (128 or 160 x Sampling frequency) - The ST7544 can work with external oversampling clocks - Programmable Symbol rate (600, 1200, 1600, 2400, 2560, 2743, 2800, 2954, 3000, 3200, 3429 and 3491) - Bit rates of 300 bps, 600bps, 1200 and all multiples of 2400 bps up to 28800 bps can be generated - Dynamic range : 92dB with a sampling frequency 9600Hz, Oversampling ratio 160 - Total harmonic distortion : -89dB ON CHIP REFERENCE VOLTAGE THREE PROGRAMMABLE DIGITAL FILTERS SECTIONS : - Tx interpolation filter - Rx decimation filter Up to 14th order each - Rx reconstruction filter Coefficients loaded into RAM ANCILLARY CONVERTERS FOR EYE-DIAGRAM MONITORING CLOCK SYSTEM BASED ON DIGITAL PHASE LOCKED LOOPS - Separate Tx DPLL and Rx DPLL - Terminal clock input for Tx synchronization on all multiples of 2400Hz (V.Fast synchronization mode) or on sub-multiple of baud rate (7543 synchronization mode) - Bit, Baud, Sampling and Highest synchronous clock outputs - Maximum master clock frequency is 38MHz SINGLE OR DUAL SYNCHRONOUS SERIAL INTERFACE TO DSP SINGLE POWER SUPPLY VOLTAGE : +5V
. . .
LOW POWER CONSUMPTION : - 260mW operating power at the nominal crystal frequency of 36.864MHz - 160mW operating power at the crystal frequency of 18.432MHz - Less than 5mW in the LOW-POWER RESET MODE 1.2MM CMOS PROCESS 44-PIN PLCC OR 44-PIN TPQFP (1.4mm body thickness)
I.1 - GENERAL DESCRIPTION The ST7544 is a single chip Analog Front-End (AFE) designed to implement high speed voicegrade Modems up to 28800 bps with echo cancelling capability. Associated with one or several Digital Signal Processors (DSP), such as the ST189XX family, it provides a powerful solution for the implementation of multi-mode Modems meeting CCITT (V.21, V.22, V.22 bis, V.23, V.26, V.27, V.29, V.32,V.32 bis and V.33) and BELL (103, 202, 212A...) recommendations. It is fully compatible with the ST7543 in 7543 mode and is also well suited emerging applications involving bit rates up to 28800 bps (in the VFast synchronization mode). The transmit section includes a 16-bit over-sampling D/A converter with a programmable interpolating filter. The receive section includes a 16-bit oversampling A/D converter with two programmable filters (one for decimation and the other for reconstruction). Oversampling ratio is selectable to either 128 or 160. Two additional 8-bit D/A converters allow eyediagram monitoring on a scope for modem performance adjustment. Two independantclock generator systems are provided, one synchronized on the Tx rate and the other on the Rx rate. In External Clock Mode, external oversampling clocks can be provided to the chip. Two independant synchronous serial interfaces (SSI) allow several versatile ways of communicating with standard DSPs. To savepower, e.g. in lap-top modem applications, the lowpower reset mode can be used to reduce the power consumption to less than 5mW.
. . . . . .
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ST7544 - UNIVERSAL ANALOG FRONT-END
I.3 - SIGNAL TRANSFER BLOCK DIAGRAM The ST7544 Block Diagram (Figure 1) illustrates three paths as follows : The Transmit D/A Section, the Receive A/D section and the Receive Reconstruction section. Figure 1
TxDO BCLKX SSIA Fsx TxDI
Serial/Parallel Conversion
16-bit data bus synchronized to the Tx clock system
ResSig
RxTx
TxSig
Fsx
2 bits
Txoclk
Fsx Fsx Fsx
4 x Fsx
Status RxS1 RxS2
IIR3
RAM3 4 x Fsx
IIR2
RAM2 4 x Fsx
IIR1
RAM1
or 5 x Fsx
or 5 x Fsx
or 5 x Fsx
Selector
Txoclk
FIR3
Txoclk
FIR2
Txoclk Txoclk
FIR1
Fsx Txoclk Fsr
Control Logic
Txoclk = 128 or 160 x Fsx
A/DC
D/AC
RxSig
FsrSync
Analog Input (Rx Signal + Echo)
FsrSync
RxSig
Analog Output (Tx Signal)
16-bit data bus synchronized to the Rx clock system
Multiplexer
RxDO BCLKR SSIB Fsr RxDI
SSIM
Serial/Parallel Conversion
8 D7:D0
D/AC
8 D15:D8
D/AC
Reg Fsr
Rxoclk
Note : Register with Tristate Output
16-bit data bus Tx
EYEX
EYEY
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7544-04.EPS
ST7544 - UNIVERSAL ANALOG FRONT-END
I.4 - IIR FILTER OPERATION Each IIR filtering section included in the ST7544 can perform up to seven biquadratic transfer functions in cascade, operating at four times the sampling frequency (see Figure 2). Each biquad is defined by five coefficients, A, B, C, D and E (see Figure 3). An additional coefficient F, scales the IIR filter output. Unused biquads are made transparent by programming A to one and the four remaining coefficients to zero. Such biquads should preferably be located in the first sections of the IIR filter in order to reduce the calculation noise. I.4.1 - Coefficient Rounding Initially, coefficients of the filter to be implemented must be exclusively between +2 and -2. To derive the actual usable 12+1 bit coefficients, the rounding process described in Figure 4 must be performed. Each 13 bit coefficient K is split into its doubling factor K2, and its 12 bit basic value K1, as the IIR architecture works with 12 bit coefficients and uses an extra accumulation when coefficient doubling is needed. 12 12 K2 [0,1] and -2 < K1 < +2 The coefficients are loaded into the different IIR filters through 16 bit wide time slots. The format to be used is as follows :
MSB K1 LSB K2 (12-bit) 000 (1 bit) (3-bit) <--------- 16 bit word -------->
words set to zero and the F coefficient word : B(1), C(1), A(1), D(1), E(1), B(2),..., E(7), 0000H , 0000H, F The total number of words sent is therefore 38. I.4.2 - Detailed Operation The architecture of the device supporting the IIR filter is based on 28 bit data path. The basic function is as follows: one coefficient K(N) is multipled by one sample X(N) followed by one accumulation with value clampling. It can be precisely described as follows : FUNCTION PAC K(N), X(N), S LOCAL P P = TRUNC (K1(N) x X(N)/212) S=S+P IF ABS(S) > 227 THEN IF SIGN(S) > 0 THEN CLAMP S TO 227-1 ELSE CLAMP S TO 227 IF K2(N) = 1 THEN S = S + P IF ABS(S) > 227 THEN IF SIGN(S) > 0 THEN CLAMP S TO 227-1 ELSE CLAMP S TO 227 END OF FUNCTION The TRUNC function is a two's complement truncature. As previously mentionned, the second accumulation is controlled by the doubling factor K2(N). The complete process of computing 16 bit output samples (VOUT) from 16 bit input samples (VIN) appears in Figure 5.
To programme one IIR filter it is necessary to send five words per biquad followed by two additional Figure 2 : IIR Filter Diagram
BIQUAD#1
VIN 12 2
BIQUAD#2 V IN (2) V OUT (2)
BIQUAD#7 VIN (7) V OUT (7)
F
V IN (1)
V OUT (1)
V OUT
Coefficients :
A(1), B(1),..., E(1)
A(2), B(2),..., E(2)
A(7), B(7),..., E(7)
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7544-22.EPS
ST7544 - UNIVERSAL ANALOG FRONT-END
Figure 3 : BIQUAD Structure
V IN (N)
A(N)
V 0 (N)
V OUT (N)
Delay
Hn(Z) = A
B(N)
V 1 (N)
D(N)
1 + DZ-1 + EZ-2 1 - BZ-1 - CZ-2
Delay
C(N)
V 2 (N)
E(N)
Equation Set :
V0(N) = B(N) x V1(N) + C(N) x V2(N) + A(N) x VIN(N) VOUT(N) = V0(N) + D(N) x V1(N) + E(N) x V2(N)
N = BIQUAD NUMBER (1:7)
7544-23.EPS
Next Step with : V2(N) = V1(N) V1(N) = V0(N) Figure 4 : IIR Coefficients Rounding
STARTING COEFFICIENT k(N) (-2 < k(N) < +2)
K = A, B, C, D, E or F
-1 < k(N) < +1 Yes
No
K2(N) = 0 K1(N) = ROUND (204 8*k(N))
K2(N) = 1 K1(N) = ROUND (1024*k(N))
7544-24.EPS
K2 = 0 or 1
K1 = 12-Bit Word
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ST7544 - UNIVERSAL ANALOG FRONT-END
Figure 5 : IIR Operating Sequence
NEW INPUT SA MPLE V IN ( 16-bit)
VIN STORAGE IN 28-BIT FORMAT
T = 800 H x V IN
FIRST BIQUAD
N=1
ACCUMULATOR RESET
S= 0
RECURSIVE COEFFICIENTS
PAC B(N), V 1 (N), S PAC C (N), V 2 (N), S PAC A(N), T, S
V0(N) STORED INTO T
T=S
DIRECT COEFFICIENTS
PAC D(N), V 1 (N), S PAC E(N), V 2 (N), S
STATE VARIABLES UP-DATING FOR THE NEXT COMPUTATION
V 2 (N) = V 1 (N) V 1 (N) = Temp
VOUT (N) STORED INTO T
T=S
NEXT BIQUAD
N = N+ 1
No
N<7
Yes OUTPUT SCALING COEFFIECIENT
S=0 PAC F, T, S
IIR OUTPUT SAMPLE STORED INTO T
T =S
TO 7FFFH OR 8000 H
6/28
7544-25.EPS
IIR OUTPUT SAMPLE LOADED INTO V OUT AFTER 16-BIT SATURATION (NEW OUTPUT SAMPLE)
V OUT = T IF GREATER THAN 16-BIT THEN CLAMPED
ST7544 - UNIVERSAL ANALOG FRONT-END
I.5. - IIR FILTER PROGRAMMING EXAMPLE I.5.1 - Example of Configuration one external clock : serial port mode : transmit sampling frequency : receive sampling frequency : bit frame clock frequency : transmit bit clock frequency : receive bit clock frequency : transmit baud clock frequency : receive baud clock frequency : transmit filter : 36.864MHz dual 9600Hz 9600Hz 160*Fsx(r) 14400Hz 14400Hz 2400Hz 2400Hz low-pass (spec table 48) : banp-pass spec table 50) : low-pass (spec table 43) - TxDI and RxDI must be tied to Vdd while the serial interface is not managed by the host processor. - RC network on NLPR pin.Typically RC=10ms (R=100k ,C=100nF) (This time must include the external clock start-up time,and the ST7544 set up time). - SSIM pin tied to DVDD : dual serial port mode. - BFRS pin tied to DVDD : bit frame frequency set to 160 time Fsx(r). I.5.3 - Software Configuration Writing convention : 'x' FRAME x,1 FRAME x,2 FRAME x,3 '#" 'b' 'h' 'XXXX' frame number frame for RAM 1 loading frame for RAM 2 loading frame for RAM 3 loading delimits a programmer's remark (comments) indicates a binary number indicates an hexadecimal number user defined
- receive filter - interpolation filter
I.5.2 Hardware Configuration - XTAL10 and XTAL11 hard-wired to the external clock
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ST7544 - UNIVERSAL ANALOG FRONT-END
# SYNCHRONOUS SERIAL INTERFACE A #FRAME 0.1. Select the correct sampling frequency and set Stb bit in order to select a RAM B9A4h #TxI0 MS =1 coefficient loading mode selected # Stb=0 start bit coefficient loading activated # QS =1 XTAL 10 selected # RAi=11b no RAM accessed # ADi=001b TxCR1 selected # Di =A4h Fsx=9600Hz, Txrclk=2400Hz # TxHSCLK=12.288MHz # Band split mode inactive FFFFh#TxI1 FFFFh#TxI2 FFFFh#TxI3 # #FRAME 1.1 Select RAM 1 and start the coefficient loading of the low-pass filter,and select TxCLK E0F1h#TxI0 MS =1 # stb=1 # QS =1 # RAi=00b RAM 1 selected. # ADi=000b TxCR0 selected. # Di =F1h TxCLK = 14400Hz FFFFh#TxI1 unused 0000h#TxI2 word 1 RAM 1 ( first IIR coefficient) 0000h#TxI3 word 2 RAM 1 # FRAME 2.1 RAM 1 coeff loading,fcomp and fshift prog and Stb ready to select another RAM A340h #TxI0 MS =1 # stb=0 # QS =1 # RAi=00b RAM 1 selected. # ADi=011b TxCR3 selected. # Di =40h fcomp = 2400Hz, fshift=Fsx/2 A000h #TxI1 word 3 RAM 1 0000h #TxI2 word 4 RAM 1 0000h #TxI3 word 5 RAM 1 # # #FRAME 3.1 RAM 1 coefficient loading, no control register access A7FFh #TxI0 B7D8h #TxI1 word 6 RAM 1 42B0h #TxI2 word 7 RAM 1 0118h #TxI3 word 8 RAM 1 # #FRAME 4.1 to 12.1 RAM 1 coefficient loading, no control register access A7FFh #TxI0 XXXXh XXXXh XXXXh
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ST7544 - UNIVERSAL ANALOG FRONT-END
#FRAME 13.1 Last RAM 1 loading frame A7FFh #TxI0 0000h #TxI1 word 36 RAM 1 0000h #TxI2 word 37 RAM 1 0008h #TxI3 word 38 RAM 1 # # #RAM 2 COEFFICIENT LOADING #FRAME 1.2 Select RAM 2 and start the coefficient loading of BP filter EFFFh #TxI0 MS =1 # Stb=1 # QS =1 # RAi=01b RAM 2 selected # ADi=111b FFFFh #TxI1 unused 0000h #TxI2 word 1 RAM 2 0000h #TxI3 word 2 RAM 2 # #FRAME 2.2 RAM 2 coefficient loading,no control register access and rest Stb AFFFh #TxI0 MS =1 # Stb=0 # QS =1 # RAi=01b RAM 2 selected # ADi=111b A000h #TxI1 word 3 RAM 2 0000h #TxI2 word 4 RAM 2 0000h #TxI3 word 5 RAM 2 # #FRAME 13.2 Last RAM 2 loading frame A7FFh #TxI0 0000h #TxI1 word 36 RAM 2 0000h #TxI2 word 37 RAM 2 0008h #TxI3 word 38 RAM 2 # # # #RAM 3 COEFFICIENT LOADING #FRAME 1.3 select RAM 3 and start coeff loading F7FFh #TxI0 MS =1 # Stb=1 # QS =1 # RAi=10b RAM 3 selected # ADi=111b FFFFh #TxI1 unused 0000h #TxI2 word 1 RAM 3 0000h #TxI3 word 2 RAM 3 # #
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ST7544 - UNIVERSAL ANALOG FRONT-END
#FRAME 2.3 RAM 3 coefficient loading,no control register access and rest Stb # # B7FFh #TxI0 A000h #TxI1 word 3 RAM 2 0000h #TxI2 word 4 RAM 2 0000h #TxI3 word 5 RAM 2 # # #FRAME 3.3 to 12.3 RAM 3 coefficient loading, no control register access B7FFh #TxI0 XXXXh XXXXh XXXXh # # #FRAME 13.3 Last RAM 3 loading frame B2C4h #TxI0 MS =1 # Stb=0 # QS =1 # RAi=10b RAM 3 selected # ADi=010b TxCR2 selected # Di =C4h 0dB attenuation on XMIT channel and synchronize the TxCLK clock on TxRCLK 0000h #TxI1 word 36 RAM 2 0000h #TxI2 word 37 RAM 2 0008h #TxI3 word 38 RAM 2 # # # FRAME 14 3FFFh #TxI0 MS =0 Data mode # Stb=0 ready to read ram # QS =1 # RAi=11b No RAM access # ADi=111b No Control register access XXXXh #TxI1 Txsig XXXXh #TxI2 Ressig XXXXh #TxI3 unused # #
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ST7544 - UNIVERSAL ANALOG FRONT-END
# SYNCHRONOUS SERIAL INTERFACE B # #FRAME 0. Select the correct sampling frequency 01A4h #TrI0 ADi=001b RxCR1 selected # Di =A4h Fsr=9600Hz, Rxrclk=2400Hz # RxHSCLK=12.288MHz FFFFh #TrI1 FFFFh #TrI2 FFFFh #TrI3 # #FRAME 1. Select the correct receive bit clock (RxCLK) frequency 00F1h #TrI0 ADi=000b RxCR0 selected # Di =F1h RxCLK=14400Hz FFFFh #TrI1 FFFFh #TrI2 FFFFh #TrI3 # #FRAME 2. No phase shift selected 0200h #TrI0 ADi=010b RxCR2 selected # # Di =00h no phase shift FFFFh #TrI1 FFFFh #TrI2 FFFFh #TrI3 # # #FRAME 3. select interpolation factor 0340h #TrI0 ADi=011b RxCR3 selected # Di =40h interpolation factor = 160 FFFFh #TrI1 FFFFh #TrI2 FFFFh #TrI3 # # #FRAME 4 FFFFh #TrI0 ADi=111b no control register access XXXXh #TrI1 EYEX-EYEY FFFFh #TrI2 reserved FFFFh #TrI3 reserved # #
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ST7544 - UNIVERSAL ANALOG FRONT-END
I.6 - FILTER COEFFICIENT CODING IN ST7544 TIME-SLOT FORMAT I.6.1 FILTER CHARACTERISTICS Type Order Sampling frequency passband edge HP stopband edge HP stopband loss HP passband edge LP stopband edge LP stopband loss LP passband ripple coefficient wordlength : : : : : : : : : : : band-pass filter 11 9.6kHz*5 = 48kHz 300Hz (3dB , butterworth) 200Hz 8dB 3200Hz (Cauer) 4200Hz 60dB 0.1dB 11 bits + sign ELSE EXTRABIT(i)=0 AA(i)=CINT(A(i)*2048) END IF AA(i)=(AA(i)<3)AND 32767 AA(i)=(AA(i) OR EXTRABIT(i)) NEXT END SUB with : INPUT : NbBiquad number of biquadratic function. A() Coefficient in decimal format OUTPUT: AA() Coefficient in ST7544 time-slot format. writing convention: ABS() return an absolute value CINT() convert its argument to an integer. (if the fractional part of an argument is equal to 0.5, it is rounded toward the even number). n left shift of n bit. Note : It is not possible to code -1 or 1 , we therefore do as following +1 = 2 * +0.5 -1 = 2 * -0.5 So IT IS NOT POSSIBLE TO CODE +/- 2 Filter table in Hexadecimal format.
B 000 3D88h B6A0h BEB8h B940h B7E8h B5A0h 0000 C 0000 0000 4D18h 4278h 4210h 46E0h 5278h 0000 A 3C88h 37E0h CE0h B58h E68h F98h 238h 20H D E000h E000h E000h C9A8h CBE8h D520h 1690h 0000 E 0000 0000 0000 A000h A000h A000h A000h 0000
I.6.2 - Filter Coefficients Table
B 0 0.9614815 1.706978 1.959984 1.675779 1.747247 1.789548 0 C 0 0 - 0.7952128 - 0.961496 - 0.7113152 - 0.8925031 - 0.967721 0 A 0.9 0.8414686 0.1985583 0.1774637 0.0346 0.1021413 0.4543867 0.0025201 D -1 -1 -1 - 1.33996 - 1.698336 - 1.627507 0 E 0 0 0 1 1 1 0
0.35224561 1
I.6.3 - Coefficient Coding in ST7544 Time-slot Format Example of subroutine to code the coefficients in the ST7544 time-slot format. SUB CODE(A(),NbBiquad,AA()) LOCAL i,EXTRABIT() FOR i=1 TO NbBiquad IF ABS(A(i))=1 THEN EXTRABIT(i)=-32768 AA(i)=CINT((A(i)/2)*2048)
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ST7544 - UNIVERSAL ANALOG FRONT-END
I.6.4 - Transfer Function Figure 6
TRANSFER FUNCTION Coefficients 11bits plus sign SPECTRAL MAGNITUDE (dB) 10 -10 MAGNITUDE (dB) -30 -50 -70 -90 -110 -130
7544-26.EPS
Figure 7
TRANSFER FUNCTION Coefficients 11 bits plus sign 0.2 -0.2 -0.6 -1.0 -1.4 -1.8 -2.2 -2.6 -3.0
7544-27.EPS
0
2
4
6
8
10
0
1
2 (Thousands) FREQUENCY (Hz)
3
4
(Thousands) FREQUENCY (Hz)
Figure 8
GROUP DELAY (1 SAMPLE= 1/(5*Fsx)) TRANSFER FUNCTION Coefficients 11 bits plus sign 90 80 70 60 50 40 30 20 10
7544-28.EPS
0
1
2 (Thousands) FREQUENCY (Hz)
3
4
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ST7544 - UNIVERSAL ANALOG FRONT-END II - ST7544 APPLICATION BOARD
The ST7544 application board will give you a powerful analog front-end evaluation/development tool. Two applications are available on board : - Appli 1 : Analog front-end, - Appli 2 : Modem analog front-end. Figure 9
Tx^Ana UNIVERSAL ANALOG FRONT-END APPLI_1 1
DIGITAL INTERFACE
Rx^Ana
ST7544
2 UNIVERSAL ANALOG FRONT-END APPLI_2
LINE
7544-29.EPS
- Digital interface gives all necessary signals in order to control and program the ST7544. - The Digital interface connector is fully compatible with ST18933 development tools. - Functionality with 2 crystals available on board, - Eye diagram monitoring, - Single-ended application. - Full differential duplexer application. II.1 - CRYSTAL OSCILLATOR XTAL10 and XTAL11 inputs must be tied to external crystal(s) or external clock(s).These inputs are selected from the TxCtrl register.The maximum clock rate is 38MHz.XTAL10 is the default external clock/crystal input.It is mandatory to short-circuit XTAL10 and XTAL11 when a single external crystal or clock generator is used.The nominal master clock frequency is 36.864MHz but the onchip amplifier is designed for a parallel crystal oscillator with a frequency equal to 18.432MHz. XTAL2 output is to be tied to one or two external crystal (Figures 10 and 11). If an external clock is used, XTAL2 should be left open.
II.1.1 - Single Crystal Oscillator Figure 10
ST7544
XTAL10 XTAL11 Q XTAL2
1.5H 0.3 C3 10pF
C1 10pF
C2 100pF
7544-30.EPS
Fq = 36.864MHz Thrird overtone CL = SERIAL
Operating range : 0 - 70 deg, 5V 5% Start-up : Max. = 10mS Typ. = 3.7 mS
14/28
ST7544 - UNIVERSAL ANALOG FRONT-END
II.1.2 - Double Crystal Oscillator Figure 11 The 3dB cut-off frequency of the 1st order filter inside the ST7544 is : Fc = TxOCLK / (2 10) E.g : 1st LP : Fsx = 7.2kHz over=4 then Fc = 14.7kHz 2nd LP : R =15k C=680pF then Fc = 15.6kHz As the transfer function of the filters are known,the digital signal can be compensated if needed. The C14=1F gives on BNC J5 a signal referenced to AGND. II.2.2 - Receive The receive part is single-ended to differential.There is a low-pass filter realised by R13,R14 and C16. Fc = 1 / ( 2 * PI * 1.2E03 * 2E-12 ) = 66kHz Having a Fc at 66kHz, we have a flat transfer function in working Band (0-4kHz). We DO NOT recommend the use of OP-AMP based filter as OP-AMP will present high impedance at high frequencies.This low-pass filter must be implemented as close as posssible to the pins RxA1 and RxA2. II.3 - APPLICATION 2 (duplexer) II.3.1 - Transmit We have a full differentiallow-pass filter on transmit the side before the DAA (see Figure 12) R1 = R21 = R22 = 13.2k R2 = R23 = R24 = 22k R3 = R25 = R26 = 22k C1 = 2 * C12 = 2*680pF = 1360pF C2 = C21 = 100pF Fc = 19.6kHz Ao = - R3/R1 = -1.66 X = 5 - Q= 0.1
ST7544
XTAL10 XTAL11 XTAL2
Fq1
C3 10pF Fq2
L1 1.5H 0.3
C1 10pF
Operating range : 0 - 70 deg, 5V 5% Start-up : Max. = 10mS Typ. = 1.5 mS II.1.3 - Quartz Specification When you order a quartz, you have to specify the following parameters : - Nominal frequency (e.g 36.864MHz ,25.848MHz) - MODE (3rd overtone, Fundamental) - Load capacitance (SERIAL, 30pF) - Frequency tolerance (50 ppm from 0 to 70oC) II.2 - APPLICATION 1 ( single-ended ) II.2.1 - Transmit The transmit part is a differential single-ended with lo w-p a s s f ilt er re alise d by R6 // C1 2 a n d R7//C13.The resistors R6 and R7 must be equal as must the capacitor C12 and C13.
7544-31.EPS
C2 100pF
C3 10pF
15/28
ST7544 - UNIVERSAL ANALOG FRONT-END
Figure 12
C21 C2
R25 R21 R23
R3 R1 V IN C12 V OUT V IN R22 R24 R26 C22 VOUT
VIN R3 R1 1
R2
C1
V OUT
FC = Q=
1 2 R2 R3 C1 C2
1 2X
=-
R2 R3 C2 P + R2 R3 C1 C2 P2 1 + R2 + R3 + R1 R3 R2R1R3 C2 + R2 C1
7544-32.EPS
X=
1 R2 + 2 2 R3
II.3.2 - Receive We have 2 filters as in application 1 (LPF, Fc = 66kHz) and describe below (DC offset suppress, Fc = 85Hz) Figure 13
R33 R36
R R37 V IN C19 R38 VIN R39 R34 V OUT R2 R1
VOUT
VIN
=1 +
R1 C P 1 + R2 C P
C = 2 C19 R1 = R36 = R39 R2 = R37 = R38
C
V OUT
16/28
7544-33.EPS
ST7544 - UNIVERSAL ANALOG FRONT-END
II.3.3 - Duplexer R,C : Improves the low frequency response.These values depend on the transfer function of the transformer.Filter transfer function realised by R,C must compensate for the loss in transformer at low frequency. Figure 14
X TRANSMIT X C 2xR R
7544-34.EPS
Phone Line
C 2 xR
RECEIVE
R
Z0 : Nominal line impedance.(e.g : Z0 = 600) TRANSFO : M = 1 , Rs = Rp = 100 2 * X = Z0/M2 - Rp - Rs/M2 2 * X = Z0 - 2 * Rp = 600 - 200 = 400 X = 200 II.4 - PERFORMANCE MEASUREMENT II.4.1 - Configuration The following measurements have been made with ST7544 application board on application (1) with crystal 36.864MHz.The analog transmit signal (J5) is connected to analog receive signal (J4). The IIR1 filter ( low-pass ) file is the following :
FFFF B7D8 48A0 3508 DD90 A000 0000 0000 42B0 2838 CFA0 A000 ADF0 0000 0000 0118 CB68 A000 AC18 5338 0008 A000 CA08 A000 AED8 6118 0858 0000 A000 B268 59D0 07A0 4098 0000 B570 5070 2898 3368 A000
The control registers are programmed as following : F9A4 TxCR1 M*Q=4*6 U=4 P0=3 and BS=0, Fsx = 9600Hz, Symbol rate = 2400 baud, Txhsclk = 12.288MHz, Band split Mode inactive F8F1 TxCR0 NRST=F1h, Bit rate clock frequency = 14400Hz FB40 TxCR3 V=010b , W=0 , Ts=000 , DL=0, Fcomp = Txrclk, Oversampling ratio = 160, Phase shift freq (Fsx/2 (Fq Fsx/2))normal mode FAC4 TxCR2 AT=11b, LTX=0, LC=0, SST=0, VF=0, R2=0, attenuation = 0dB, mode 7543, synchronize TxCLK on TxRCLK, Normal mode synchronization 01A4 RxCR1 idem TxCR1 00F1 RxCR0 idem TxCR0 0200 RxCR2 no phase shift 0340 RxCR3 V = 160 - Interpolation ratio II.4.2 - Measurement We generate a digital sinewave of 1003.125Hz (1024 samples).This signal is sent to Txsig.Then we do a FFT (1024 samples) on the digital receive signal RxTx. Figure 15
ST7544 ANALOG LOOP-BACK Fq = 36.864MHz, Fsx = 9600Hz, Oversampling = 5 0 -20 -40 S/N (dB) -60 -80 -100 -120 -140
7544-35.EPS
0
1
2
3
4
5
The IIR2 and IIR3 filter (band-pass filter) files are the following :
FFFF 3D88 4D18 0B58 CBE8 A000 0000 0000 0000 0CE0 C9A8 A000 B5A0 0000 0000 37E0 E000 A000 B7E8 5278 0020 3C88 E000 0000 B940 46E0 0238 E000 0000 BEB8 4210 0F98 1690 0000 B6A0 4278 0E68 D520 A000
(Thousands) FREQUENCY
We have S/N = 84.43 dB. The band noise is double because of analog loop-back ,so if we want to calculate the dynamic range of the ST7544 ,we add 3dB to the S/N. S/N = 84.43+3 = 87.43 dB at Signal = -6.13dBr S/N = 87.43 + 6.13 = 93.56dB = DYNAMIC S/N = 6.02 * Nbit + 1.76 Nbit = (93.56-1.76)/6.02 = 15.25 bits
17/28
ST7544 - UNIVERSAL ANALOG FRONT-END
III - INTERFACING ST7544 WITH DSP56000 (MOTOROLA) You will find below a suggested interface of our ST7544 with DSP56000 series from Motorola. We use the ST7544 in single SSI. The different connection are as following : Figure 16
ST7544 DSP56000
The DSP56000 control register bit has to be configured as following : Figure 17
SYN GCK SCKD SCD2 FSL WL1-WL0 DC4-DC0 Bit Set to 1 Bit Set to 0 Bit Set to 0 Bit Set to 0 Bit Set to 1 Bits Set to 10 Bits Set to X Synchronous Mode Continuous Clock External Source Clock SCK Set to Input Mode Frame Sync Length Equal 1 Bit Word Length Set to 16 bits Number of Timeslot (4, 5)
And you have to program the DSP in Network mode.
18/28
7544-47.EPS
7544-46.EPS
Bit Clock Frame Clock Transmit Data Receive Data
Output Output Output Input
BCLKX FSX TxDI TxDO
SCK SC2 SRD STD
Serial Bit Clock Frame Sync Receive Data Transmit Data
Input Output Output Output
ST7544 - UNIVERSAL ANALOG FRONT-END
ANNEXE 1 : Demoboard Schematics
Figure 18
C12
680pF
TXA2 1
TXA2 1
R4
R6
15k
6
15k U3B OP270
C14
1F
TX
J5
5+
7
TXA1 1
TXA1 1
R5
R7
15k
15k
C13
680pF
+1 2V
VCM
3
U3A OP270 1
8
+
4 -12V
+1 2V
2
U5B OP270
R13 1.2k
R10 5k 5 6 R9 5k
U4A OP270 1
8
+
3 2
RXA1 1
RXA1 1
7
+
4 -12V
R12 5k
C15 3.3nF
R19 1.2k
R11 5k
R20 1.2k
R18 1.2 k
R14 5k +12V U5A OP270 1 4 -12V R17 5k
8 3 2
RXA2 1
RXA2 1
+
R15 5k
U4B OP270
+
5 RCV 6
J4
-
R16 5k
7
-
R8 100k
+12V
+12V
DECOUPLING U2 U4 CD102 CD2 10F 100nF
CD2 0 2 1 0 0 nF
DECOUPLING U3 U5 CD 4 CD104 100nF 10F CD204 100nF
CD304 10F
7544-36.EPS
CD302 10F
-12V
-12V
19/28
ST7544 - UNIVERSAL ANALOG FRONT-END
Figure 19
R25 22k C12 100pF TXA1 2 TXA1 2 R21 13.2k VCM C20 680nF 3 TXA2 2 TXA2 2 R22 13.2k R24 22k 2 R23 22k 6
-
U6B TL072 7
R29 300 C23 220nF TP30 TP29 TP26 TP27 F1 LINE
5+
+12V
R27 40k R30 300 C24 220nF R28 40k
8 + 4
-12V
U6A TL072
1
C22 R26 22k
100pF +12V
RXA1 2
RXA1 2
R31 1.2k
U7A TL072 1
8
+
3 2
R33 20k
-
4 R36 20k -12V
R37 20k C19 47nF R38 20k
R39 20k TXA2 2 RXA2 2 R32 1.2k
+12V
8 7
-
6 R34 20k
U7B TL072
+5
4
DECOUPLING U6 U7 CD6 CD106 100nF 10F CD206 100nF
CD306 10F
7544-37.EPS
-12V
20/28
P1
TXA2 1
TXA2 1
TXA2
1
2
BCLKR
W3 TP1
3
4
FSR
5 BFRS
6
RXDO
TXA2 2 TXA2 2
RXA2 1
RXA2 1 TXA1 1 TXA1 1
Figure 20
7
8
TXCLK
TP2
9 TXA1 W5
10
BCLKX
SSIM
RXA2 C18 2.2nF
TXA1 2 TXA1 2 1nF C16 RXA2 2 CD1 100nF
11
12
FSX
13
RXA2 2 VCM C17 2.2nF
W6
14
DV DD RX A1 1
RXA1 1
TXDO
15
16
RX CLK
CD101 47F TP3
R40 10k
W4
R41 10k
17
18
RXDI
19
20
TXDI
BCLKR
RXA1
21
22
TP20 TP4
FSR
AVDD CD601
RXA1 2
23
24
SSIM
25 RxDO
26
BFRS
TP5
DV DD CD701 100nF DV DD
RXA1 2
27
28
RXRCLK
29
30
TXRCLK
NOT
TP6
RxDI S3 10 F
31
32
TP21 TP7
TxDI R43 10k R42 10k
WIRED
VCM
of R2 and R3
Double implantation
33
34
TP22
CD801 100nF
6 5 4 3 2 1 44 43 42 41 40
CD901 10 F
35
36
TP23
AV DD
V CM
TP8
TxDO
37
38
TP24
RxDI
TxA2
SSIM
TxA1
RxDO
BCLKR
DGND1
HE10 20X2 TP10
DD1 DV
BFRS
FSX
FSR
39
40
NRESET
TP9
R3 1.5k
AGNDT
U2 TLE2425
BCLKX
7 8 9 TxDO
TxDI
39
FSX
AV DD 37 BCLKX EYEY RxA1
TxOCLK (TEST2)
J1 EYEY
VCM 38
R2 1.5k
CD201 100nF CD301 47F
10 11 12 DGND2 AGNDR
RxA2 36
35 34
DV DD
EYEX
VCC
C1 100nF
J2
13 DV DD2
TP11
14 EYEX V REFN 32 15 16 RxCLK RxCLK
U1 ST7544
V REFP 33
S5
S6
S7
AV DD
TP12
C2 10 F
1
6
27
F2
RxHSCLK
TP13
17 RxSYNC
RxOCLK 31
EOCMODE 30
NLPR C3 100nF
Y0T : A
Y1T : B
IDT : C
RxHSCLK RxRCLK
C29
C28
TxRCLK
TxSYNC
TxSCLK
XTAL10
DGND3
XTAL11
RxSYNC
DVDD3
TxHSCLK
+5VD 47F
XTAL2
100nF
DV DD
29
C4 10F
3
TXOCLK
TXSYNC 13
TxCLK
TP25
TP26
TXHSCLK 14
RXHSCLK
16
27 28 S2 DV DD
Y0R : A
C26
W1
TP14 18 19 20 21 22 23 24 25
C27 47F RxRCLK
TP15
100nF
26
4
RXOCLK
RXSYNC
15
S4 TxRCLK
TP16
VCC
Y1R : B Q1 DV DD
IDR : C S1
S8 25.8048MHz U8 2 S9
ALTERA1
5 S10
28
CD8
C30 47F
100nF
TxSYNC
TP17
F4
TxHSCLK
TP18
+12V
oscillo
Q1
TP19
R44 10k
NRESET
VCC
-12V
CD401 100nF DV DD CD501 47F
TxCLK
C10 F3 47F
C8 47 F
C11
C9
100nF
100nF
36.864MHz
C5 10pF
J3
TxSCLK
R1 50
C6 10pF
Q2
C7 10pF
36.864MHz overtone L1 1.5 H
C31 100pF
ST7544 - UNIVERSAL ANALOG FRONT-END
21/28
7544-38.EPS
ST7544 - UNIVERSAL ANALOG FRONT-END
ANNEXE 2 : Layout
Figure 21
LINE
F1
APPLI2 R11
TX
C13
C12
R7
R5
C14
R12
J5
APPLI1 R23 C21
R25
CD204
C20
U5
U3
R29 R30
+
CD104
C23
C24 R27 R33
R34 R28
R10
R14
CD4
R15
R9
U6
CD205
R21 R22 R26 R24
R36
U4
R37
R39
C22
+
R8
19 R13 R32 R31
20
CD2 CD302
+
U2
J4
R18
CD901
D N
R3
R2
CD W6
W5
801
C3
W3 W4
RCV
+
CD
+
51 L14
C31 C7
U8
TXSCLK
A2 A1
C2
CD601 J1
C1
+
C4
R1 U9
1 A B C 2
J3
-21V +12V
U1
CD501
+
CD101
C5
Q1
C6
W1
RXMIT RCV
A B C
C9 +
TP25
TP19
1 10 12 13 AD
15
17
0
C
TP25 +5
R43
R44
CD8
+
10
2
8
4
6
TP1
14
16
18
23
21
22
TP24
TP20
11
R24 P1
C29
C27 C28
C26
R41
1
F2
EYEX R40
5
7
9
3
4
+SVD +SVA
C1
AGND
J2
+
+
F3
F4
EYEY
53
52
Q2
+
C8
R
C30
5 A
CD305
C19
R38
+
CD102 CD202
CD6
ST 7544 APPLICATION BOARD
CD304
CD105
U7
R4 R17
R16
R5
+
22/28
7544-39.EPS
ST7544 - UNIVERSAL ANALOG FRONT-END
Figure 22 : Layer 1 - Components Side
23/28
7544-40.TIF
ST7544 - UNIVERSAL ANALOG FRONT-END
Figure 23 : Layer 1
24/28
7544-41.TIF
ST7544 - UNIVERSAL ANALOG FRONT-END
Figure 24 : Layer 2 - GNDD, AGND
25/28
7544-42.TIF
ST7544 - UNIVERSAL ANALOG FRONT-END
Figure 25 : Layer 3 - DVDD, AVDD
26/28
7544-43.TIF
ST7544 - UNIVERSAL ANALOG FRONT-END
Figure 26 : Layer 4
27/28
7544-44.TIF
ST7544 - UNIVERSAL ANALOG FRONT-END
Figure 27 : Layer 4
28/28
7544-45.TIF
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

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