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DISCRETE SEMICONDUCTORS
DATA SHEET
BSP255 P-channel enhancement mode vertical D-MOS transistor
Product specification Supersedes data of 1996 Jun 13 File under Discrete Semiconductors, SC07 1996 Aug 05
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
FEATURES * Direct interface to C-MOS, TTL etc * Low threshold voltage * High speed switching * No secondary breakdown. APPLICATIONS * Line current interrupter in telephone sets * Relay, high speed and line transformer drivers.
handbook, halfpage
BSP255
PINNING - SOT223 PIN 1 2 3 4 SYMBOL g d s d gate drain source drain DESCRIPTION
4
d
DESCRIPTION P-channel enhancement mode vertical D-MOS transistor in a 4-pin plastic SOT223 SMD package.
1 2 3
MAM121
g
CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling.
s
Top view
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA SYMBOL VDS VSD VGS VGSth ID RDSon Ptot PARAMETER drain-source voltage (DC) source-drain diode forward voltage gate-source voltage (DC) gate-source threshold voltage drain current (DC) drain-source on-state resistance total power dissipation ID = -1 mA; VDS = VGS Ts = 100 C ID = -160 mA; VGS = -10 V Ts = 100 C IS = -0.5 A CONDITIONS - - - -0.8 - - - MIN. MAX. -300 -1.8 20 -2 -325 17 4 V V V V mA W UNIT
1996 Aug 05
2
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS VGS ID IDM Ptot Tstg Tj IS ISM Notes 1. Ts is the temperature at the soldering point of the drain lead. 2. Pulse width and duty cycle limited by maximum junction temperature. PARAMETER drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature operating junction temperature Ts = 100 C note 2 Ts = 100 C; note 1 note 2 Ts = 100 C CONDITIONS - - - - - -65 -65 - - MIN.
BSP255
MAX. -300 20 -325 -1.3 4 +150 +150 -0.5 -2 V V
UNIT
mA A W C C
Source-drain diode source current (DC) peak pulsed source current A A
handbook, halfpage
10 Ptot (W) 8
MBH446
handbook, halfpage
-10 ID (A) -1
MBH445
(1)
6 -10-1 4 -10-2 2 tp T 0 0 50 100 150 Ts (oC) 200 -10-3 -1 -10 -102 t P
tp = 10 s 100 s
= T
tp
DC
1 ms 10 ms
VDS (V)
-103
= 0.01; TS = 100 C. (1) RDSon limitation.
Fig.2 Power derating curve.
Fig.3 DC SOAR.
1996 Aug 05
3
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER thermal resistance from junction to soldering point VALUE 12
BSP255
UNIT K/W
102 handbook, full pagewidth
MBH444
Rth j-s (K/W) = 0.75 0.5 0.33 0.2 0.1 1 0.05 0.02 0.01 0 tp T 10-1 10-6 10-5 10-4 10-3 10-2 10-1 1 P
10
= T
tp
t
t p (s)
Fig.4
Transient thermal resistance from junction to soldering point as a function of pulse time; typical values.
1996 Aug 05
4
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL V(BR)DSS VGSth IDSS IGSS RDSon PARAMETER drain-source breakdown voltage gate-source threshold voltage drain-source leakage current gate leakage current drain-source on-state resistance CONDITIONS VGS = 0; ID = -10 A VGS = VDS ; ID = -1 mA VGS = 0; VDS = -240 V VGS = 20 V; VDS = 0 VGS = -10 V; ID = -160 mA VGS = -4.5 V; ID = -80 mA VGS = -2.8 V; ID = -50 mA Ciss Coss Crss Qg Qgs Qgd input capacitance output capacitance reverse transfer capacitance total gate charge gate-source charge gate-drain charge VGS = 0; VDS = -50 V; f = 1 MHz VGS = 0; VDS = -50 V; f = 1 MHz VGS = 0; VDS = -50 V; f = 1 MHz VGS = -10 V; VDD = -50 V; ID = -160 mA; Tamb = 25 C VGS = -10 V; VDD = -50 V; ID = -160 mA; Tamb = 25 C VGS = -10 V; VDD = -50 V; ID = -160 mA; Tamb = 25 C VGS = 0 to -10 V; VDD = -50 V; ID = -160 mA; Rgen = 50 VGS = -10 to 0 V; VDD = -50 V; ID = -160 mA; Rgen = 50 MIN. -300 -0.8 - - - - - - - - - - - TYP. - - - - - - - 45 15 3 2.3 0.1 0.7
BSP255
MAX. - -2 -100 100 17 20 25 - - - - - -
UNIT V V nA nA pF pF pF nC nC nC
Switching times (see Fig.11) td(on) tr ton td(off) tf toff VSD turn-on delay time rise time turn-on switching time turn-off delay time fall time turn-off switching time VGD = 0; IS = -0.5 A - - - - - - - 2.4 1.6 4 13 12 25 - - - - - - - -1.8 ns ns ns ns ns ns
Source-drain diode source-drain forward voltage V
1996 Aug 05
5
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
BSP255
handbook, halfpage
-10
MBH443
VGS (V)
handbook, halfpage
-800 ID (mA) -600
MBH441
VGS = -10 V
-8
-4.5 V -4.0 V
-6 -400 -4
-3.5 V -3.0 V
-2
-200
-2.5 V -2.0 V
0 0 0.5 1.0 1.5 2.0 2.5 Qg (nC)
0 0
-2
-4
-6
-8
-10 -12 VDS (V)
VDD = -50 V: ID = -180 mA. Tj = 25 C.
Fig.5
Gate-source voltage as a function of total gate charge; typical values.
Fig.6 Output characteristics; typical values.
handbook, halfpage
-800 ID (mA) -600
MBH440
handbook, halfpage
-2.5
MBH436
ISD (A) -2.0
-1.5 -400 -1.0 -200
(1) (2) (3)
-0.5
0 0
-2
-4
-6
-8 -10 VGS (V)
0 0
-0.4
-0.8
-1.2
-2.0 -1.6 VSD (V)
VGD = 0. (1) Tj = 150 C. (2) Tj = 25 C. (3) Tj = -65 C. VDS = -10 V; Tj = 25 C.
Fig.8
Fig.7 Transfer characteristics; typical values.
Source-drain current as a function of source-drain diode forward voltage; typical values.
1996 Aug 05
6
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
handbook, halfpage
MBH437
BSP255
102
handbook, halfpage
160
MBH442
RDSon ()
(1) (2) (3) (4) (5)
C (pF) 120
80
Ciss 40 Coss Crss 0 -10 -20 -30 -40 -50 VDS (V)
10 0
-2
-4
-6
-8 -10 VGS (V)
0
VDS ID x RDSon; Tj = 25 C. (1) ID = -10 mA. (2) ID = -50 mA.
(3) (4) (5)
ID = -80 mA. ID = -160 mA. ID = -325 mA.
VGS = 0; f = 1 MHz; Tj = 25 C.
Fig.9
Drain source on-state resistance as a function of gate-source voltage; typical values.
Fig.10 Capacitance as a function of drain-source voltage; typical values.
handbook, full pagewidth
0 -VDD Vin
10 %
RL Vout 0 10 % Vout Vin td(on) tr ton 90 %
90 %
10 %
90 % td(off) tf toff
MGD391
Fig.11 Switching time test circuit and input and output waveforms.
1996 Aug 05
7
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
BSP255
MBH438
MBH439
handbook, halfpage
1.4
handbook, halfpage
2.4
k 1.2
k 2.0
(1) (2)
1.6 1.0 1.2 0.8 0.8
0.6 -75
-25
25
75
125 175 Tj (C)
0.4 -75
-25
25
75
125 175 Tj (C)
V GSth at T j k = ------------------------------------V GSth at 25C VGSth at VDS =VGS ; ID = -1 mA.
R DSon at T j k = ---------------------------------------R DSon at 25 C (1) VGS = -4.5 V; ID = -80 mA. (2) VGS = -2.8 V; ID = -50 mA.
Fig.12 Temperature coefficient of gate-source threshold voltage as a function of junction temperature; typical values.
Fig.13 Temperature coefficient of drain-source on-state resistance as a function of junction temperature; typical values.
1996 Aug 05
8
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
PACKAGE OUTLINE Plastic surface mounted package; collector pad for good heat transfer; 4 leads
BSP255
SOT223
D
B
E
A
X
c y HE b1 vMA
4
Q A A1
1
e1 e
2
bp
3
wM B detail X
Lp
0
2 scale
4 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.8 1.5 A1 0.10 0.01 bp 0.80 0.60 b1 3.1 2.9 c 0.32 0.22 D 6.7 6.3 E 3.7 3.3 e 4.6 e1 2.3 HE 7.3 6.7 Lp 1.1 0.7 Q 0.95 0.85 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT223
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 96-11-11 97-02-28
1996 Aug 05
9

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