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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4731B; HEF4731V LSI Quadruple 64-bit static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple 64-bit static shift register DESCRIPTION The HEF4731B and HEF4731V are quadruple 64-bit static shift registers each with separate serial data inputs (DA to DD), clock inputs (CPA to CPD) and data outputs (O63A to O63D) from the 64th register position. HEF4731B; HEF4731V LSI Recommended supply voltage range for HEF4731B is 3 to 15 V and for HEF4731V is 4,5 to 12,5 V. Data are shifted to the next stage on the negative-going transitions of the clock. Low impedance outputs are provided for direct interface to TTL. Fig.2 Pinning diagram. HEF4731BP; HEF4731VP(N): HEF4731BD; HEF4731VD(F): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category LSI Fig.1 Functional diagram. See Family Specifications January 1995 2 Philips Semiconductors Product specification Quadruple 64-bit static shift register HEF4731B; HEF4731V LSI Fig.3 Logic diagram (one of 64-bits shift register). The values given at VDD = 15 V in the following DC and AC characteristics, are not applicable to the HEF4731V, because of its reduced supply voltage range. DC CHARACTERISTICS VSS = 0 V; VI = VSS or VDD Tamb (C) VDD V Output (source) current HIGH Output (sink) current LOW 5 5 10 15 4,75 10 15 0,4 0,5 1,5 IOL VOL V VOH V 2,5 4,6 9,5 13,5 -IOH SYMBOL -40 MIN. 3 1 3 10 2,3 6,0 20,0 MAX. + 25 MIN. 2,5 0,85 2,5 8,5 2,0 5,0 18,0 MAX. + 85 MIN. 2,0 0,65 2,0 6,5 1,6 4,0 14,0 MAX. mA mA mA mA mA mA mA AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 13 000 fi + (foCL) x VDD2 55 000 fi + (foCL) x VDD2 140 000 fi + (foCL) x VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 |
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