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L6910 L6910A
ADJUSTABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION
FEATURE s OPERATING SUPPLY VOLTAGE FROM 5V TO 12V BUSES s UP TO 1.3A GATE CURRENT CAPABILITY s ADJUSTABLE OUTPUT VOLTAGE s N-INVERTING E/A INPUT AVAILABLE s 0.9V 1.5% VOLTAGE REFERENCE s VOLTAGE MODE PWM CONTROL s VERY FAST LOAD TRANSIENT RESPONSE s 0% TO 100% DUTY CYCLE s POWER GOOD OUTPUT s OVERVOLTAGE PROTECTION s HICCUP OVERCURRENT PROTECTION s 200kHz INTERNAL OSCILLATOR s OSCILLATOR EXTERNALLY ADJUSTABLE FROM 50kHz TO 1MHz s SOFT START AND INHIBIT s PACKAGES: SO-16 & HTSSOP16 APPLICATIONS s SUPPLY FOR MEMORIES AND TERMINATIONS s COMPUTER ADD-ON CARDS s LOW VOLTAGE DISTRIBUTED DC-DC s MAG-AMP REPLACEMENT
SO-16 (Narrow) HTSSOP16 (Exposed Pad) ORDERING NUMBERS: L6910 (SO-16) L6910A (HTSSOP16) L6910TR (Tape & Reel) L6910ATR (Tape & Reel)
DESCRIPTION The device is a pwm controller for high performance dc-dc conversion from 3.3V, 5V and 12V buses. The output voltage is adjustable down to 0.9V; higher voltages can be obtained with an external voltage divider. High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20A. The device assures protections against load overcurrent and overvoltage. An internal crowbar is also provided turning on the low side mosfet as long as the over-voltage is detected. In case of over-current detection, the soft start capacitor is discharged and the system works in HICCUP mode.
BLOCK DIAGRAM
Vin 5V to12V
PGOOD
VCC
OCSET
BOOT VREF
SS
Monitor Protection and Ref
UGATE
OSC
PHASE
OSC Vo
RT
L6910
EAREF + -
LGATE
PGND
E/A
+
PWM
GND
300k
VFB COMP
July 2003
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L6910A L6910
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VBOOTVPHASE VHGATEVPHASE OCSET, LGATE, PHASE SS, FB, PGOOD, VREF, EAREF, RT COMP Tj Tstg Ptot Junction Temperature Range Storage temperature range Maximum power dissipation at Tamb = 25C Vcc to GND, PGND Boot Voltage Parameter Value 15 15 Unit V V
15
V
-0.3 to Vcc+0.3 7 6.5 -40 to 150 -40 to 150 1
V V V C C W
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient SO-16 120 HTSSOP16 110 HTSSOP16 (*) 50 Unit C/W
(*) Device soldered on 1 S2P PC board
PINS CONNECTION (Top view)
VREF OSC OCSET SS/INH COMP FB GND EAREF
1 2 3 4 5 6 7 8
SO16
16 15 14 13 12 11 10 9
N.C. VCC LGATE PGND BOOT HGATE PHASE PGOOD
VREF OSC OCSET SS/INH N.C. COMP FB GND
1 2 3 4 5 6 7 8
HTSSOP-16
16 15 14 13 12 11 10 9
VCC LGATE PGND BOOT HGATE PHASE PGOOD EAREF
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PINS FUNCTION
SO 1 HTSSOP 1 Name VREF Description Internal 0.9V 1.5% reference is available for external regulators or for the internal error amplifier (connecting this pin to EAREF) if external reference is not available. A minimum 1nF capacitor is required. If the pin is forced to a voltage lower than 70%, the device enters the hiccup mode. Oscillator switching frequency pin. Connecting an external resistor (RT) from this pin to GND, the external frequency is increased according to the equation: 4.94 10 f O SC,RT = 200KHz + -----------------------RT ( K ) Connecting a resistor (RT) from this pin to Vcc (12V), the switching frequency is reduced according to the equation: 4.306 10 f O SC,RT = 200KHz - ---------------------------RT ( K ) If the pin is not connected, the switching frequency is 200KHz. The voltage at this pin is fixed at 1.23V. Forcing a 50A current into this pin, the built in oscillator stops to switch. In Over Voltage condition this pin goes over 3V until that conditon is removed. 3 3 OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit protection. The internal 200A current generator sinks a constant current through the external resistor. The Over-Current threshold is due to the following equation: I OCSE T R O CS ET IP = --------------------------------------------R DS on The soft start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces through the capacitor 10A. This pin can be used to disable the device forcing a voltage lower than 0.4V This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. Connected to the output resistor divider, if used, or directly to Vout, it manages also overvoltage conditions and the PGOOD signal All the internal references are referred to this pin. Connect it to the PCB signal ground. Error amplifier non-inverting input. Connect to this pin an external reference (from 0.9V to 3V) for the PWM regulation or short it to VREF pin to use the internal reference. If this pin goes under 650mV (typ), the device shuts down.
7 6
2
2
OSC
4
4
SS/INH
5 6
6 7
COMP FB
7 8
8 9
GND EAREF
9 10
10 11
PGOOD This pin is an open collector output and it is pulled low if the output voltage is not within the above specified thresholds. If not used it may be left floating. PHASE This pin is connected to the source of the upper mosfet and provides the return path for the high side driver. This pin monitors the drop across the upper mosfet for the current limit together with OCSET. High side gate driver output. Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc (cathode vs. boot). Power ground pin. This pin has to be connected closely to the low side mosfet source in order to reduce the noise injection into the device This pin is the lower mosfet gate driver output Device supply voltage. The operative supply voltage ranges is from 5V to 12V. DO NOT CONNECT VIN TO A VOLTAGE GREATER THAN VCC. This pin is not internally bonded. It may be left floating or connected to GND.
11 12
12 13
HGATE BOOT
13 14 15 16
14 `5 16 5
PGND LGATE VCC N.C.
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ELECTRICAL CHARACTERISTICS (Vcc = 12V, TJ =25C unless otherwise specified)
Symbol Parameter Vcc SUPPLY CURRENT Icc Vcc Supply current POWER-ON Turn-On Vcc threshold Turn-Off Vcc threshold Rising VOCSET threshold Turn On EAREF threshold SOFT START AND INHIBIT Iss Soft start Current S.S. current in INH condition VOCSET = 4V SS = 2V SS = 0 to 0.4V OSC = OPEN OSC = OPEN; Tj = 0 to 125 16 K < RT to GND < 200 K 6 Test Condition OSC = open; SS to GND VOCSET = 4V VOCSET = 4V Min 4 4.0 3.8 Typ 7 4.3 4.1 1.24 650 10 35 200 Max 9 4.6 4.4 1.4 750 14 60 220 230 15 1.9 VOUT = VFB; VEAREF = VREF CREF = 1nF; IREF = 0 to 100A CREF = 1nF; TJ = 0 to 125C VEAREF = 3V Vs. GND VFB = 0V to 3V 0.8 0.5 70 COMP = 10pF VBOOT - VPHASE = 12V VHGATE - VPHASE = 6V VBOOT - VPHASE = 12V Vcc = 12V; VLGATE = 6V Vcc = 12V PHASE connected to GND VOCSET = 4V VFB Rising VFB > OVP Trip VFB Rising VFB Falling Upper and Lower threshold IPGOOD = -4mA VPGOOD = 6V 15 108 88 90 170 200 117 30 110 90 2 0.4 0.2 1 112 92 0.9 1 85 10 10 1.3 2 1.1 1.5 3 210 230 120 4 0.886 0.886 -2 10 300 0.01 0.5 3 4 0.900 0.900 0.913 0.913 +2 Unit mA V V V mV A A KHz kHz % V V V % A k A V V dB MHz V/s A A ns A % mA % % % V A
OSCILLATOR Initial Accuracy fOSC fOSC,RT Total Accuracy
180 170 -15
Vosc Ramp amplitude REFERENCE VOUT Output Voltage Accuracy VREF VREF Reference Voltage Reference Voltage
ERROR AMPLIFIER IEAREF N.I. bias current IFB VCM VCOMP GV EAREF Input Resistance I.I. bias current Common Mode Voltage Output Voltage Open Loop Voltage Gain
GBWP Gain-Bandwidth Product SR Slew-Rate GATE DRIVERS IHGATE High Side Source Current RHGATE ILGATE RLGATE High Side Sink Resistance Low Side Source Current Low Side Sink Resistance
Output Driver Dead Time PROTECTIONS IOCSET OCSET Current Source Over Voltage Trip (VFB / VEAREF) IOSC OSC Sourcing Current POWER GOOD Upper Threshold (VFB / VEAREF) Lower Threshold (VFB / VEAREF) Hysteresis (VFB / VEAREF) VPGOOD IPGOOD PGOOD Voltage Low Output Leakage Current
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Device Description The device is an integrated circuit realized in BCD technology. The controller provides complete control logic and protection for a high performance step-down DC-DC converter. It is designed to drive N Channel Mosfets in a synchronous-rectified buck topology. The output voltage of the converter can be precisely regulated down to 900mV with a maximum tolerance of 1.5% when the internal reference is used (simply connecting together EAREF and VREF pins). The device allows also using an external reference (0.9V to 3V) for the regulation. The device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth product and 10V/s slew rate that permits to realize high converter bandwidth for fast transient performance. The PWM duty cycle can range from 0% to 100%. The device protects against over-current conditions entering in HICCUP mode. The device monitors the current by using the rDS(ON) of the upper MOSFET(s) that eliminates the need for a current sensing resistor. The device is available in SO16 narrow package. Oscillator The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 50A (Fsw = 200KHz) and may be varied using an external resistor (RT) connected between OSC pin and GND or VCC. Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin. In particular connecting RT vs. GND the frequency is increased (current is sunk from the pin), according to the following relationship: 4.94 10 f OSC,RT = 200KH z + ------------------------R T ( K ) Connecting RT to VCC = 12V or to VCC = 5V the frequency is reduced (current is forced into the pin), according to the following relationships: 4.306 10 f OSC,RT = 200KH z - ---------------------------R T ( K ) 15 10 f OSC,RT = 200KH z - --------------------R T ( K )
6 7 6
VCC = 12V
VCC = 5V
Switching frequency variation vs. RT are repeated in Fig. 1. Note that forcing a 50A current into this pin, the device stops switching because no current is delivered to the oscillator. Figure 1.
10000
Reference A precise 1.5% 0.9V reference is available. This reference must be filtered with 1nF ceramic capacitor to avoid instability in the internal linear regulator. It is able to deliver up to 100A and may be used as reference for the device regulation and also for other devices. If forced under 70% of its nominal value, the device enters in Hiccup mode until this condition is removed. Through the EAREF pin the reference for the regulation is taken. This pin directly connects the non-inverting input of the error amplifier. An external reference (or the internal 0.9V 1.5%) may be used. The input for this pin can range from 0.9V to 3V. It has an internal pull-down (300k resistor) that forces the device shutdown if no reference is connected (pin floating). However the device is shut down if the voltage on the EAREF pin is lower than 650mV (typ).
1000
Resistance [kOhm]
100
10
RT to GND RT to VCC=12V RT to VCC=5V
10
100
1000
Frequency [kHz]
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Soft Start At start-up a ramp is generated charging the external capacitor CSS with an internal current generator. The initial value for this current is of 35A and speeds-up the charge of the capacitor up to 0.5V. After that it becames 10A until the final charge value of approximatively 4V. When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to discharge the output capacitor. As VSS reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper MOS begins to switch and the output voltage starts to increase. No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off. If VCC and OCSET pins are not above their own turn-on thresholds and VEAREF is not above 650mV, the SoftStart will not take place, and the relative pin is internally shorted to GND. During normal operation, if any undervoltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged. Figure 2. Soft Start (with Reference Present)
Vcc Turn-on threshold Vcc Vin Vin Turn-on threshold Vss
to GND
1V 0.5V
LGATE
Vout
Timing Diagram
Acquisition: CH1 = PHASE; CH2 = Vout; CH3 = PGOOD; CH4 = Vss
Driver Section The driver capability on the high and low side drivers allows using different types of power MOS (also multiple MOS to reduce the RDSON), maintaining fast switching transition. The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin. Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mosfets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the high side turn-off. The peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5V and 12V. A 3.3nF capacitive load has been used in these measurements. For the lower driver, the source peak current is 1.1A @ VCC = 12V and 500mA @ VCC = 5V, and the sink peak current is 1.3A @ VCC = 12V and 500mA @ VCC = 5V. Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ VbootVphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.
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Figure 3. High Side driver peak current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left)
CH1 = High Side Gate CH4 = Gate Current
Figure 4. Low Side driver peak current. VCC = 12V (right) VCC = 5V (left)
CH1 = Low Side Gate CH4 = Gate Current
Monitoring and Protections The output voltage is monitored by means of pin FB. If it is not within 10% (typ.) of the programmed value, the powergood output is forced low. The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.) greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the over-voltage is detected. Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of the upper MOS. Thus the overcurrent threshold (IP) can be calculated with the following relationship: R OCS I OCS I P = -------------------------------R ds O N Where the typical value of IOCS is 200A. To calculate the ROCS value it must be considered the maximum RdsON (also the variation with temperature) and the minimum value of IOCS. To avoid undesirable trigger of overcurrent protection this relationship must be satisfied:
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L6910A L6910
I I P I OUT MAX + ---- = I PE AK 2 Where I is the inductance ripple current and IOUTMAX is the maximum output current. In case of over current detectionthe soft start capacitor is discharged with constant current (10A typ.) and when the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is discharged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode, as shown in figure 5. After removing the cause of the over-current, the device restart working normally without power supplies turn off and on. Figure 5. Hiccup Mode Figure 6. Inductor ripple current vs. Vout
9 8
L=1.5H, Vin=12V L=2H, Vin=12V L=3H, Vin=12V L=1.5H, Vin=5V L=2H, Vin=5V L=3H, Vin=5V
Inductor Ripple [A]
7 6 5 4 3 2 1 0 0 .5 1.5 2.5
3 .5
CH1 = SS; CH4 = Inductor current
Output V oltage [V]
Inductor design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship: V IN - V OUT V OUT L = ----------------------------- -------------V IN f s w I L Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 6 shows the ripple current vs. the output voltage for different values of the inductor, with VIN = 5V and VIN = 12V. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. If the compensation network is well designed, the device is able to open or close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for I load transient in case of enough fast compensation network response: L I t a pplic atio n = ----------------------------V IN - V OUT L I t rem ov al = -------------V OUT
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available.
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Output Capacitor The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for first few microseconds they supply the current to the load. The controller recognizes immediately the load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): V OUT = I OUT ESR A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: I OUT L V OUT = --------------------------------------------------------------------------------------------2 C OUT ( V INM IN D M AX - V OUT ) Where DMAX is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. Input Capacitor The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must have a low ESR to minimize the losses. The rms value of this ripple is: I rm s = I OUT D ( 1 - D ) Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are: P = ESR I rm s Compensation network design The control loop is a voltage mode (figure 7). The output voltage is regulated to the input Reference voltage level (EAREF). The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. This wave is filtered by the output filter. The modulator transfer function is the small-signal transfer function of VOUT/VCOMP. This function has a double pole at frequency FLC depending on the L-Cout resonance and a zero at FESR depending on the output capacitor ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage VOSC.
2 2
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Figure 7. Compensation Network
Vin Vosc L ESR PWM Comparator C18 R5 C19 C20 Vcomp R3 R4 Cout Vout
-
EAREF
+ The compensation network consists in the internal error amplifier and the impedance networks ZIN (R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with the highest 0dB crossing frequency to have fast response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the load regulation. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45. Include worst-case component variations when determining phase margin. To locate poles and zeroes of the compensation networks, the following suggestions may be used: Modulator singularity frequencies: 1 LC = -------------------------L C OUT Compensation network singularity frequency: 1 P1 = ---------------------------------------------C18 C19 R5 ---------------------------C 18 + C 19 1 Z1 = ----------------------R5 C19

1 ESR = -------------------------------ESR C OUT
1 P2 = ----------------------R4 C 20 1 Z2 = -----------------------------------------( R3 + R 4 ) C20
- Put the gain R5/R3 in order to obtain the desired converter bandwidth; - Place Z1 before the output filter resonance LC; - Place Z2 at the output filter resonance LC; - Place P1 at the output capacitor ESR zero ESR; - Place P2 at one half of the switching frequency; - Check the loop gain considering the error amplifier open loop gain.
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Figure 8. Asymptotic Bode plot of Converter's gain
dB
Error Amplifier
R5/R3
1 LC 2
Modulator Gain Compensation Network Gain Error Amplifier
P1 P2 ESR
Closed Loop Gain
20A Demo Board Description The demo board shows the operation of the device in a general purpose application. This evaluation board allows voltage adjustability from 0.9V to 5V through the switches S2-S5 according to the reported table when the internal 0.9V reference is used (G1 closed). Output current in excess of 20A can be reached dependently on the kind of mosfet used: up to three SO8 mosfet may be used for both High side and Low side switches. External reference may be used for the regulation simply leaving open G1 and the switches S2-S5. The device may also be disabled with the switch S1. The 12V input rail supplies the device while the power conversion starts from the 5V input rail. The device is also able to operate with a single supply voltage; in this case the jumper G2 has to be closed and a 5V to 12V input can be directly connected to the VIN input. The four layers demo board's copper thickness is of 70m in order to minimize conduction losses considering the high current that the circuit is able to deliver. Figure 9 shows the demo board's schematic circuit Figure 9. 20A Demo Board Schematic
F1 VIN G2 GNDIN D1 R6 C17 GNDCC
VCC
L1 R7 C14 C13
UGATE
BOOT
OCSET
C1 -C3
12 15
VCC
3
11
PHASE
C15
GND
Q1 -3
L2 VOUT
10 7
LGATE
SS
4
OSC
U1 L6910
COMP
14
PGND
Q4 -6
D2
C4 -11
R2 GNDOU T
13
PGOOD
2
EAREF
9
VREF
PWRGD +Vref C12 R3 GNDref
5
GNDRef IN
C21
R1 C19 C18 R5
VFB
Ref IN
8 C16 6
1
R4
C20
S1 S2 S3 S4 S5 R10 R11 R12 R13
G1
Vout 0.9 1.2 1.5 1.8 2.5 3.3 5.0
S2 S3 S4 S5
Open Open Ope n Open
ON Open Open Open
Open ON Open Open
ON
ON Open Open
Open Open ON Open Open Open Open ON Open Open ON
ON
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Figure 10. PCB and Components Layouts
Component Side
Internal Signal GND Layer
Figure 11. PCB and Components Layouts
Internal Power GND Layer
Solder Side
Figures 10 and 11 show the demo board layout. Considering the flexibility in the power mosfet configuration (up to three mosfet for both high side and low side), it is possible to obtain different application idea with the same board. In the following paragraphs, it will be described the standard demo-board configuration (8A) and the high current configuration. APPLICATION IDEA: 5V TO 12V INPUT; 0.9V TO 5V / 8A OUTPUT This is a typical bus termination application in which the output voltage is programmed by the switch to 1.2V typ (it can range from 0.9V to 5V) and the maximum output current is of 8A DC. The power mosfet are configured with one STS12NF30L (30V, 10m typ @ Vgs=4.5V ) for both hgih side and low side. Inductor selection Since the maximum output current is 8A, to have a 15% ripple (1A) in worst case the inductor chosen is 4.1H. SUMIDA CEE125 series inductor has been chosen with a 4.2A typical value.
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Output Capacitor In the demo 5 POSCAP capacitors, model 6TPB330M, are used, with a maximum ESR equal to 40m each. Therefore the resultant ESR is of 8m. For load transient of 8A in the worst case the voltage drop is of: Vout = 8 * 0.008 = 64mV The voltage drop due to the capacitor discharge during load transient, considering that the maximum duty cycle is equal to 100% results in 16.4mV with 1.2V of programmed output. Input Capacitor For IOUT = 8A and D=0.5 (worst case for input ripple current), Irms is equal to 4A. Three OSCON electrolytic capacitors 20SA100M, with a maximum ESR equal to 30m, are chosen to sustain the ripple. Therefore, the resultant ESR is equal to 30m/3 = 10m. So the losses in worst case are: P = ESR * I rm s = 160mW Over-Current Protection The peak current is in this case equal to 12A, substituting the demo board parameters in the relationship reported in the relative section, (IOCSMIN = 170A; IP = 12A; RDSONMAX = 9m) it results that ROCS = 620. Table 1. Part List
R2 R3 R5 R6 R7 R10 R11 R12 R13 C1 C4...C11 C12, C13, C15, C21 C14 C19 L1 L2 U1 Q1, Q4 D1 D2 F1 10k 4.7k 47k 10 620 14k 6.98k 2.61k 1.74k 100 330 100n 1n 56n 1.5 4.2 L6910 STS12NF30L 1N4148 STPS3340U 251015A-15 E96 1% E96 1% (optional) E96 1% (optional) E96 1% (optional) OSCON - 20SA100M POSCAP - 6TPB330M Ceramic Ceramic Ceramic T44-52 Core, 7T-18AWG SUMIDA CEE125 series STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics Littlefuse 1% SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 Radial 10x10.5mm SMD 7343 SMD 0805 SMD 0805 SMD 0805
2
SO16 NARROW SO8 SOT23 SMB AXIAL
Efficiency Figure 12 shows the measured efficiency versus load current for different values of output voltage. The measure was done at Vin = 5V for different values of the output voltage (0.9V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V). IC supply voltage is of 12V. In the application one mosfets STS12NF30L (30V, 10m typ @ Vgs = 4.5V) is used for both the low and the high side. Since the board has been layed out with the possibility to use up to three SO8 mosfets for both high and low side switch, to increase efficiency at low output voltages, an additional mosfet on the low side can be considered because of the duty cycle.
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Figure 12. Demo Board Efficiency @ Vin = 5V
95 90 85 80 75 70 65 60 0 2 4 6 Output Current [A] 8 10
Vout = 0.9V Vout = 1.5V Vout = 2.5V Vout = 1.2V Vout = 1.8V Vout = 3.3V
APPLICATION IDEA: 5V TO 12V INPUT; 3.3V / 25A OUTPUT This is a typical application to replace the mag-amp in the silver box. The output voltage is programmed by the switch to 3.3V and the maximum output current is of 25A DC. The power mosfet are configured with three STS11NF30L (30V, 9m typ @ Vgs = 10V ) for high side and two of them for the low side. Inductor selection Since the maximum output current is 25A, to have a 20% ripple (5A) in worst case the inductor chosen is 1.1H. An iron powder core (TO50-52B) with 6 windings has been chosen. Output Capacitor 4 POSCAP capacitors, model 6TPB330M, are used, with a maximum ESR equal to 40m each. Therefore the resultant ESR is of 10m. For load transient of 20A in the worst case the voltage drop is lower than 5%: Vout = 20 * 0.01 = 200mV Input Capacitor For IOUT = 25A and D = 0.5 (worst case for input ripple current), Irms is equal to 12.5A. Three OSCON electrolytic capacitors 6SP680M, with a maximum ESR equal to 13m, are chosen to sustain the ripple. Therefore, the resultant ESR is equal to 13m/3 = 4.3m. So the losses in worst case are: P = ESR * I rm s = 670mW Over-Current Protection The peak current is in this case equal to 30A, substituting the demo board parameters in the relationship reported in the relative section, (IOCSMIN = 170A; IP = 30A; RDSONMAX = 3m) it results that ROCS = 530.
2
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Efficiency [%]
L6910A L6910
Table 2. Part List
R2 R3 R4 R5 R6 R7 R9 R10 C1,C2, C3 C4 to C8 C13, C15 C14, C16 C18 C19 C20 L1 L2 U1 Q1 to Q5 D1 D2 F1 10k 4.7k 220 10k 10 620 0 1.74k 680 330 100n 1n 2.2n 3.3n 6.8n 1.5 1.1 L6910 STS11NF30L 1N4148 STPS340U 251015A-15 1% OSCON - 6SP680M POSCAP - 6TPB330M Ceramic Ceramic Ceramic Ceramic Ceramic T44-52 Core, 7T-18AWG T50-52B Core, 6T STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics Littlefuse SO16 NARROW SO8 SOT23 SMB AXIAL 1% SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 Radial 10x10.5mm SMD 7343 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805
Efficiency Figure 13 shows the measured efficiency versus load current at Vin=5V. In the application three mosfets STS11NF30L (30V, 9m typ @ Vgs = 10V) are used for high side swith while two of them are used for the low side.. Figure 13. Demo Board Efficiency @ Vin = 5V & Vout = 3.3V
97 95 93 91 89 87 85 0 5 10 15 Output current 20 25
Efficiency
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5A Demo Board Description The demo board shows the operation of the device in a general purpose application. The interanl reference is used for the regulation. The external power mosfets are included in one SO8 package to save space and increase power density.The 12V input rail supplies the device while the power conversion starts from the 5V input rail. The device is also able to operate with a single supply voltage; in this case the jumper J1on the board bottom has to be closed and a 5V to 12V input can be directly connected to the VIN input. Figure 14. 5A Demo Board Schematic
VIN (+5V) J1 GNDIN D1 R6
VCC
R7
C7 C6
UGATE
BOOT
OCSET
C1,C2 R8 Q1/1 R11 C10 L1 VOUT
12 15
VCC (+12V) GNDCC
3
11
PHASE
C5
GND
10 7
SS
4 C9
OSC
U1 L6910
LGATE
14
PGND
R9 Q1/2
D2
C3, C4 R2 GNDOUT
13
PGOOD
2
EAREF
9
VREF
PWRGD
8 C8 R10
COMP
1 5
VFB
6 R3 C19 R5 C18 R4 C20
R1
Figure 15. PCB and Components Layouts
Component Side
Solder Side
Efficiency Figure 16 shows the measured efficiency versus load current for different values of output voltage. The measure was done at 5V and 12V input for different values of the output voltage (2.5V, 3.3V and 5V only when Vin=12V). Output voltage has been changed modifying the value of R1 in the demo board as reported in the part list.
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L6910A L6910
Figure 16. Demoboard efficiency with VCC = VIN = 5V (left), and with VCC = VIN = 12V (right).
95 94 93 92 91 90 89 88 87 86 85 0 1 2
95 90
Efficiency [%]
Efficiency [%]
85 80 75 70 65 60 0 1 2 3 Vout=2.5V Vout=3.3V Vout=5V
Vout=3.3V Vout=2.5V
3
4
5
4
5
Output Current [A]
Output Current [A]
Part List
Resistors
R1 560 375 220 10K 1K 33 2.7K 10 680 2.2 10F 100 F - 6.3V 100nF 1nF 1.5n 15n 47n 10H STS7DNF30L 1N4148 STPS125A L6910 STMicroelectronics STMicroelectronics T50-52B Core, 12T STMicroelectronics SO8 SOT23 SMA SO16Narrow TOKIN C34Y5U1E106ZTE12 POSCAP 6TPB100M 1%; (Vout = 2.5V) 1%; (Vout = 3.3V) 1%; (Vout = 5V) SMD 0805
R2 R3 R4 R5 R6 R7 R8, R9
SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 7343 SMD 7343 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805
Capacitors
C1,C2 C3, C4 C5,C6,C9 C7, C8 C18 C19 C20
Magnetics
L1
Transistors
Q1
Diodes
D1 D2 Ics U1
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L6910A L6910
APPLICATION IDEA: BUCK-BOOST CONVERTER 3V TO 10V INPUT / 5V 2A OUTPUT Figure 17. buck-boost converter 3V to 10V input / 5V 2A Output Circuit
VIN (+2.5V to +12V) R7 GNDIN D1 R6
VCC
C7 C6
UGATE
BOOT
OCSET
C1,C2 R8
12 15
VCC (+12V) GNDCC
3
11
PHASE
Q1/1 L1
D3 VOUT
C5
GND
10 7
SS
4 C9
OSC
U1 L6910
LGATE
14
PGND
R9 Q1/2
D2 Q2/2
Q2/1 C3, C4 R2 GNDOUT
13
PGOOD
2
EAREF
9
VREF
PWRGD
8 C8 R10
COMP
1 5
VFB
6 R3 C19 C18 R5 R4 C20
R1
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L6910A L6910
DIM. MIN. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 3.8 4.6 0.4 9.8 5.8 0.35 0.19 0.1
mm TYP. MAX. 1.75 0.25 1.6 0.46 0.25 0.5 45 (typ.) 10 6.2 1.27 8.89 4 5.3 1.27 0.62 8(max.) 0.150 0.181 0.016 0.386 0.228 0.014 0.007 0.004 MIN.
inch TYP. MAX. 0.069 0.009 0.063 0.018 0.010 0.020
OUTLINE AND MECHANICAL DATA
Weight: 0.20gr
0.394 0.244 0.050 0.350 0.157 0.209 0.050 0.024
SO16 Narrow
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
0016020
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L6910A L6910
mm DIM. MIN. A A1 A2 b c D (*) D1 E E1 (*) E2 e L L1 k aaa 0.45 0.8 0.19 0.09 4.9 1.7 6.2 4.3 1.5 0.65 0.6 1.0 0 (min), 8 (max) 0.10 0.75 0.018 6.4 4.4 5.0 1.0 TYP. MAX. 1.2 0.15 1.05 0.3 0.2 5.1 3.0 6.6 4.5 3.0 0.031 0.007 0.003 0.192 0.067 0.244 0.169 0.059 MIN.
inch TYP. MAX. 0.047 0.006 0.039 0.041 0.012 0.008 0.197 0.200 0.118 0.252 0.173 0.260 0.177 0.118 0.026 0.024 0.039 0.029
OUTLINE AND MECHANICAL DATA
0.004
(*) Dimensions D and E1 does not include mold flash or protusions. Mold flash or protusions shall not exeed 0.15mm per side.
HTSSOP16 (Exposed Pad)
7419276
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L6910A L6910
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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