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SDA 4330-2X
1 1.1 * * * * * *
Overview Features
155 MHz FM and 40 MHz AM input frequency 30 mVeff AM and 50 mVeff FM sensitivity 16 bit IF counter up to 50 MHz Additional open drain ports controlled by I2C 2-pin quartz oscillator P-DSO-24-1 Fast phase detector with short anti-backlash pulses and polarity reversal * Charge pump current programmable in four steps up to 4.5 mA * Frequency resolution of 1, 5 and 10 kHz AM and 12.5, 25 and 50 kHz FM * P-DSO-24 package
Type SDA 4330-2X 1.2 Application
Ordering Code Q67100-H5140
Package P-DSO-24-1
The SDA 4330-2X provides separated input and output ports for AM and FM and is well suited for extremely fast loop settling times in the FM mode.
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SDA 4330-2X
1.3
Pin Configuration (top view)
P-DSO-24-1
Figure 1
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1.4 Pin No. 1 2 3 4 5 6...9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Pin Definitions and Functions Symbol Input (I) Function Output (O) Supply voltage digital (5 V) I I/O I O O I I I/O I/O I O O O O I/O I Clock I2C Bus Data I2C Bus Address selection, sets the LSB of the IC address H-active lock detect output port 10 V open drain output, controlled via I2C Bus 10 V open drain output, indicating the operation mode (H = AM) Input for the FM signal from VCO Ground analog Input for the AM signal from VCO FM input of IF counter as long as the counter is enabled, otherwise pulled to ground AM input of IF counter as long as the counter is enabled, otherwise pulled to ground Reference current, setting the base current level for the charge pumps FM charge pump output AM charge pump output Source follower output FM Source follower output AM Supply voltage digital (up to 10 V) Oscillator feedback, quartz terminal Oscillator input, quartz terminal, optionally input for external reference Ground digital
VDD1
SCL SDA A0 LD AM/FM FMIN GNDAN AMIN IFFM IFAM
SA1 ... SA4 O
IREF
PDFM PDAM PDFMA PDAMA
VDD2
OSCFB OSCIN GND
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1.5
Functional Block Diagram
Figure 2 Block Diagram
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2
Functional Description
The SDA 4330-2X is a radio PLL controlled via I2C Bus for frequency synthesis in the AM and FM range. It includes an IF counter up to 50 MHz enabling a precise search tuning stop. 3 Circuit Description
The reference frequency for the PLL is derived from the quartz oscillator OSC1). The R-prescaler can be adapted to quartz frequencies of 4, 8 or 10.25 MHz, respectively, yielding an internal 50 kHz reference. Programming the R-counter sets the phase detector reference frequency to 1, 5 or 10 kHz in the AM mode or to 12.5, 25 or 50 kHz in the FM mode. The VCO frequency is set by programming the A/N-counter which operates as dual-modulus counter for FM and AM using a divide by 4/5 swallow counter. The phase detector drives two different charge pumps for AM and FM mode. Additional source followers are connected to the charge pump. There are four programmable current levels for each charge pump. The supply voltage for the charge pump and the source followers is supplied via the VDD2-pin and can reach 10 V maximum. AM/FM is an open drain output as well as the additional outputs SA1 ... SA4 which are controlled by I2C Bus. The IF counter is activated by the IF bit of the I2C status word. In the FM mode the IFFM signal is divided by 2 or 4 in the F-counter in the AM mode the IFAM input is switched directly to the gate. The G-counter provides four different gate intervals TG of 2, 4, 8, or 20 ms respectively. During this interval the D-counter counts up from zero and after closing the gate its content Z is transferred into the D-register where it can be read from the I2C Bus. The IF frequency is given by -fIFFM = Z ---------------- ; F = -- , -24 F x TG 1 11
fIFAM = Z -----TG
The relations between gate interval, resolution and measurement range are given in table 1. After being started by setting the IF bit the count-cycle is repeated continuously and the content of the D-register is updated after each cycle. So the first valid result in the D-register can be expected one gate length after starting with an additional delay of
1)
1
The power dissipation of the quartz is given by: Pv = 2 x R1 ( x fQ x (CO + CL) x VDD)2 R1 : Series resistance of the quartz fQ : Quartz frequency CO: Parallel capacitance of the quartz CL: Load capacitance, including input capacitance of the IC
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100 s. Afterwards always the latest count is stored in the D-register and can be read via I2C Bus at any time. In order to achieve a valid result after the first gate cycle the control bits for G-counter, F-counter and R-prescaler have to be set to the actual value prior to setting the IF bit. The I2C Bus interface provides slave receiver and slave transmitter functions. There are two addresses selected by the A0 pin. The I2C-protocol (see diagram 1) contains one string for programming all counters and functions. The transfer may be stopped optionally after each word if the remaining functions are not to be altered. After power ON all control signals are undefined, so that the complete write sequence must be executed. In the read mode only the contents of the D-register can be accessed. The programming of the counters and functions is shown in tables 2-4.
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4 4.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. 6 10.5 10 t.b.d. - 40 -2 125 10.5 2 V V mW mW C V kV - 0.3 - 0.3 - 0.3 Unit Remarks
TA = - 25 C to 85 C
Parameter Supply voltage
VDD1 Supply voltage VDD2 Input voltage VIN Power dissipation per output PQ Power dissipation Ptot Storage temperature TS Output voltage SA1-SA4, AM/FM VQH ESD voltage (HBM: 1.5 k, 100 pF) VESD
VDD1 + 0.3 V
Note: Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
4.2 Operating Range Symbol min. Supply voltage Supply voltage Supply current1) Supply current2) Ambient temperature Output voltage SA1 ... SA4, AM/FM
1) 2)
Parameter
Limit Values typ. 5 max. 5.5 10.3 20 0.5 - 25 + 85 4.5 9
Unit V V mA mA C V
VDD1 VDD2 IDD1 IDD2 TU VQH
VDD2
Measurement conditions: IF counter disabled Measurement conditions: Pins PDFM, PDAM, PDFMA, and PDAMA: Output current = 0 mA
Note: In the operating range the functions given in the circuit description are fulfilled.
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4.3
AC/DC Characteristics Symbol Limit Values min. typ. max. Unit Test Condition
Parameter
Input AMIN Input voltage (sine wave) Input capacitance
VIN
30 4 - 10 10
mVeff VDD1 = 4.5 V 0.5 MHz < fIN < 40 MHz pF A 0 VQ VDD1
C Input leakage current ILeakage
Input FMIN Input voltage (sine wave) Input capacitance
VIN
50 120 4 - 10 10
VDD1 = 4.5 V mVeff 20 MHz < fIN < 120 MHz mVeff 10 MHz < fIN < 155 MHz
pF A 0 VQ VDD1
C Input leakage current ILeakage
Input OSCIN Input voltage (sine wave)
VIN
100 150 200 10 - 30 30
VDD1 = 4.5 V mVeff fIN = 4 MHz mVeff fIN = 8 MHz mVeff fIN = 10.25 MHz
pF A 0 VQ VDD1
C Input leakage current ILeakage
Input/Output IFAM
Input capacitance
VAC Input frequency fIN Input leakage current ILeakage
AC input voltage L-output voltage DC Input capacitance
50 0.3 - 10 15 10 1 4
mVeff 2 V VDC 3 V MHz A V pF
VDD1 = 4.5 V 0 VQ VDD1,
counter enabled
VQL C
IQL = 2 mA,
counter disabled
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4.3
AC/DC Characteristics (cont'd) Symbol Limit Values min. typ. max. Unit Test Condition
Parameter
Input/Output IFFM AC input voltage
VAC
50 120
2 V VDC 3 V VDD1 = 4.5 V mVeff 3 MHz fIN 30 MHz mVeff 30 MHz < fIN 50 MHz 10 1 4 A V pF 0 VQ VDD1, counter enabled
Input leakage current L-output voltage DC Input capacitance Input/Output SDA H-input voltage L-input voltage L-output voltage Input leakage current Input capacitance Inputs SCL, A0 H-input voltage L-input voltage Input leakage current Input capacitance
ILeakage VQL C
- 10
IQL = 2 mA,
counter disabled
VIH VIL VQL ILeakage C
0.7 x
VDD1
V
VDD1
0 0.3 x V
VDD1
0.4 -1 1 10 V A pF
IQL = 3 mA, VDD1 = 5 V, CL = 400 pF 0 VQ VDD1
VIH VIL ILeakage C
0.7 x
VDD1
V
VDD1
0 -1 0.3 x V
VDD1
1 10 A pF 0 VQ VDD1
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4.3
AC/DC Characteristics (cont'd) Symbol Limit Values min. typ. max. Unit Test Condition
Parameter
Outputs SA1, SA2, SA3, SA4, AM/FM (open drain outputs) L-output voltage
VQL VQL
0.4 0.1
V V
IQL = 1 mA VDD1 = 5 V IQL = 0.1 mA
Output LD H-output voltage L-output voltage Input IREF Input current Voltage at IREF Output PDFM PD current A PD current B PD current C PD current D Output PDAM PD current A PD current B PD current C PD current D
VQH VQL
VDD -
0.4 0.4
V V
IQH = 1 mA IQL = 1 mA
IIN VIREF
t.b.d. 100 1.2
t.b.d. A V
IIN = 100 A
IQ IQ IQ IQ
4.5 3 1.5 150
mA mA mA A
VPD = 4 V
IQ IQ IQ IQ
450 300 150 30
A A A A
VPD = 4 V
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4.3
AC/DC Characteristics (cont'd) Symbol Limit Values min. typ. max. Unit Test Condition
Parameter
Output PDFMA H-output voltage H-output current L-output current Output PDAMA H-output voltage L-output current
VQH IQH IQL
7.5
7.7 2 5
V mA A
10
IQH = 2 mA VPDFM = VDD2 = 9 V VPDFM = VDD2 = 9 V VPDFM = GND
IQH IQL
1 t.b.d.
2.5
mA mA
VPDAM = 5 V VPDAM = GND VQ = 5 V
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
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Table 1 IF counter
TG [ms]
FM 2 4 4 8 8 20 20 AM 2 4 8 20
1)
F-counter Resolution[Hz] Accuracy [Hz]1) Frequency Range [MHz]
1:2 1:4 1:2 1:4 1:2 1:4 1:2
1000 1000 500 500 250 200 100
3000 3000 1500 1500 750 600 300
65.5 65.5 32.8 32.8 16.4 13 6.5
500 250 125 50
1500 750 375 150
32.8 16.4 8.2 3.25
Accuracy due to gate uncertainty; there is an additional inaccuracy due o the quartz frequency.
Table 2 Programming of Mode and Frequency Resolution AM/FM 0 0 0 1 1 1 R1 0 1 1 0 1 1 R0 1 0 1 1 0 1 Mode FM FM FM AM AM AM Frequency Range [kHz] 12.5 25 50 1 5 10
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Table 3 Programming R-prescaler RP1 0 0 1 1 RP0 0 1 0 1 Divide ratio 1:1 1:80 1:160 1:205 Quartz Frequency [MHz] Test mode only 4 8 10.25
Table 4 Programming IF counter G1 0 0 1 1 G0 0 1 0 1 G-Divide Ratio TG [ms] 1:100 1:200 1:400 1:1000 2 4 8 20 IF 0 1 Table 5 Programming Phase Detector PD1 0 0 1 1 PD0 0 1 0 1 Current Level D C B A PPD 0 1 Polarity Normal Invers Function Disable IF counter Enable IF counter F0 0 1 F-Divide Ratio 1:2 1:4
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Table 6 Programming Test Mode T1 0 0 T0 0 0 T2 0 1 PD_MUX SA1 SA2 SA3 SA4 D_INX T3 Operation 0 1 Normal Test-reset Controlled by I2C Bus Clk_50 kHz N_A_CLN
Output LD Disabled Enabled
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Diagram 1: I2C Protocol
Slave-receive (Write) Slave-receive (Read) START START 1 1 1 1 0 0 0 0 1 1 0 0 0/1 0/1 0 0 ACK ACK MSB MSB N14 D14 N13 D13 N12 D12 N11 D11 N10 D10 N9 D9 N8 D8 ACK ACK A/N-counter D-register N7 D7 N6 D6 N5 D5 N4 D4 N3 D3 N2 D2 N1 D1 LSB LSB ACK ACK [STOP or START] STOP or START AM/FM PD1 PD0 IF SA4 SA3 SA2 SA1 ACK [STOP or START]: [STOP or START] Optional STOP or START condition, after power ON G1 the complete sequence has to be programmed. G0 F0 R1 R0 RP1 RP0 0 ACK [STOP or START] PPD T0 (= `0') T1 (= `0') T2 (= `0') T3 (= `0') X X X ACK STOP or START
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Figure 3 Application Circuit for AM and FM Charge Pump Output
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Package Outlines P-DSO-24-1 (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 17
Dimensions in mm 04.96
GPS05144

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